diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-23 13:33:16 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2017-05-09 13:02:58 +0800 |
| commit | e7b8e072fd6da92d7820b0a18c30bd3eea6ffc44 (patch) | |
| tree | 99cae09b138c37a958c7e4e80e318ad20dab553f /Platform/BroxtonPlatformPkg/Common/Include/Guid | |
| parent | 54901c47dd992753dfce0a234c8cd53492e70d1a (diff) | |
| download | edk2-platforms-e7b8e072fd6da92d7820b0a18c30bd3eea6ffc44.tar.xz | |
BroxtonPlatformPkg: Add package Include and Library
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Common/Include/Guid')
15 files changed, 2808 insertions, 0 deletions
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/AcpiTableStorage.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/AcpiTableStorage.h new file mode 100644 index 0000000000..449790d6b0 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/AcpiTableStorage.h @@ -0,0 +1,25 @@ +/** @file
+ GUID for the ACPI Table Storage filename.
+
+ Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ACPI_TABLE_STORAGE_H_
+#define _ACPI_TABLE_STORAGE_H_
+
+#define EFI_ACPI_TABLE_STORAGE_GUID \
+ { 0x7e374e25, 0x8e01, 0x4fee, {0x87, 0xf2, 0x39, 0xc, 0x23, 0xc6, 0x6, 0xcd} }
+
+extern EFI_GUID gEfiAcpiTableStorageGuid;
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/BiosId.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/BiosId.h new file mode 100644 index 0000000000..ad60290fd2 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/BiosId.h @@ -0,0 +1,26 @@ +/** @file
+ GUIDs used for Bios ID.
+
+ Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BIOS_ID_H_
+#define _BIOS_ID_H_
+
+
+#define EFI_BIOS_ID_GUID \
+{ 0xC3E36D09, 0x8294, 0x4b97, 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 }
+
+extern EFI_GUID gEfiBiosIdGuid;
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/BoardFeatures.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/BoardFeatures.h new file mode 100644 index 0000000000..79b9631c22 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/BoardFeatures.h @@ -0,0 +1,113 @@ +/** @file
+ EFI Platform Board Features.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef BoardFeatures_h_included
+#define BoardFeatures_h_included
+
+#include <Base.h>
+
+#pragma pack(1)
+
+//
+// Board Features
+//
+#define B_BOARD_FEATURES_CHIPSET_LAN BIT0
+#define B_BOARD_FEATURES_CHIPSET_VIDEO BIT1
+#define B_BOARD_FEATURES_VIDEO_SLOT BIT2
+#define B_BOARD_FEATURES_AA_NOT_FOUND BIT3
+#define B_BOARD_FEATURES_SIO_NO_COM1 BIT4
+#define B_BOARD_FEATURES_SIO_COM2 BIT5
+#define B_BOARD_FEATURES_SIO_NO_PARALLEL BIT6
+#define B_BOARD_FEATURES_NO_FLOPPY BIT7
+#define B_BOARD_FEATURES_PS2WAKEFROMS5 BIT8 // Wake from S5 via PS2 keyboard
+#define B_BOARD_FEATURES_ECIR BIT9 // Enhanced Consumer IR
+#define B_BOARD_FEATURES_LEGACY_FREE BIT10
+#define B_BOARD_FEATURES_MINI_CARD BIT11
+#define B_BOARD_FEATURES_DISCRETE_1394 BIT12
+#define B_BOARD_FEATURES_USB_HUB BIT13
+#define B_BOARD_FEATURES_TPM BIT14
+#define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
+#define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15
+#define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16
+#define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
+#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT20
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR3 BIT22
+#define B_BOARD_FEATURES_MEMORY_SLOT_MASK (BIT24 | BIT23)
+#define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT23=0, BIT24=0
+#define V_BOARD_FEATURES_2_MEMORY_SLOT BIT23 // BIT23=1, BIT24=0
+#define V_BOARD_FEATURES_3_MEMORY_SLOT BIT24 // BIT23=0, BIT24=1
+#define V_BOARD_FEATURES_4_MEMORY_SLOT (BIT24 | BIT23) // BIT23=1, BIT24=1
+#define B_BOARD_FEATURES_2_C0_MEMORY_SLOT BIT25 // 2 Channel 0 memory slot
+#define B_BOARD_FEATURES_SLEEP_MASK BIT26
+#define V_BOARD_FEATURES_SLEEP_S1 0 // BIT26=0
+#define V_BOARD_FEATURES_SLEEP_S3 BIT26 // BIT26=1
+#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION BIT27 // 0/1= 5/3 Rear Jacks
+#define B_BOARD_FEATURES_HDAUDIOLINK BIT28 // HD audio link support
+#define B_BOARD_FEATURES_DISCRETE_SATA BIT29
+#define B_BOARD_FEATURES_2_SATA BIT30 // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8)
+#define B_BOARD_FEATURES_NO_SATA_PORT2_3 BIT31 // No SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag
+#define B_BOARD_FEATURES_RVP BIT32 // Board is an RVP board
+#define B_BOARD_FEATURES_ESATA_PORT0 BIT33 // E-SATA on Port0
+#define B_BOARD_FEATURES_ESATA_PORT1 BIT34 // E-SATA on Port1
+#define B_BOARD_FEATURES_ESATA_PORT2 BIT35 // E-SATA on Port2
+#define B_BOARD_FEATURES_ESATA_PORT3 BIT36 // E-SATA on Port3
+#define B_BOARD_FEATURES_ESATA_PORT4 BIT37 // E-SATA on Port4
+#define B_BOARD_FEATURES_ESATA_PORT5 BIT38 // E-SATA on Port5
+#define B_BOARD_FEATURES_IDCC2_SUPPORT BIT39 // Include IDCC2 support
+#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE BIT40
+#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT BIT41 // Limited CPU support
+#define B_BOARD_FEATURES_PMP_SUPPORT BIT42 // Support for over-voltaging memory
+#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER BIT43 // Support for the HW-based 555 Watchdog Timer feature
+#define B_BOARD_FEATURES_LVDS BIT44 // Support for LVDS
+#define B_BOARD_FEATURES_VERB_TABLE_MASK (BIT45|BIT46|BIT47|BIT48) // Verb table
+#define B_BOARD_FEATURES_VERB_TABLE1 BIT45 // Verb table 1
+#define B_BOARD_FEATURES_VERB_TABLE2 BIT46 // Verb table 2
+#define B_BOARD_FEATURES_VERB_TABLE3 BIT47 // Verb table 3
+#define B_BOARD_FEATURES_VERB_TABLE4 BIT48 // Verb table 4
+#define B_BOARD_FEATURES_NO_MINIPCIE BIT49 // Mini PCIe slot
+#define B_BOARD_FEATURES_HDMI_SLOT BIT50 // HDMI slot
+#define B_BOARD_FEATURES_PS2_HIDE BIT51 // PS2 hide
+#define B_BOARD_FEATURES_DVID_SLOT BIT52 // DVID slot
+
+#define B_BOARD_FEATURES_SIO_COM3 BIT53
+#define B_BOARD_FEATURES_SIO_COM4 BIT54
+
+#define B_BOARD_FEATURES_LAN2 BIT55
+#define B_BOARD_FEATURES_PCIe_SLOT BIT56
+
+typedef UINT64 EFI_BOARD_FEATURES;
+
+#pragma pack()
+
+//
+// Global ID for the Platform Boot Mode Protocol
+//
+
+#define EFI_BOARD_FEATURES_GUID \
+ { 0x94b9e8ae, 0x8877, 0x479a, 0x98, 0x42, 0xf5, 0x97, 0x4b, 0x82, 0xce, 0xd3 }
+
+extern EFI_GUID gEfiBoardFeaturesGuid;
+
+#define BOARD_FEATURES_NAME L"BoardFeatures"
+
+#define EFI_BOARD_ID_GUID \
+ { 0x6b2dd245, 0x3f2, 0x414a, 0x8c, 0x2, 0x9f, 0xfc, 0x23, 0x52, 0xe3, 0x1e }
+#define EFI_BOARD_ID_NAME (L"BoardId")
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/EfiVpdData.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/EfiVpdData.h new file mode 100644 index 0000000000..13530b9e8a --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/EfiVpdData.h @@ -0,0 +1,178 @@ +/** @file
+ Constants and declarations that are common accross PEI and DXE.
+
+ Copyright (c) 2003 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_VPD_DATA_H_
+#define _EFI_VPD_DATA_H_
+
+
+#pragma pack(1)
+
+//
+// DMI data
+//
+typedef struct {
+ CHAR8 DmiGpnvHeader[4]; // $DMI
+ CHAR8 SystemInfoManufacturer[0x20]; // Structure Type 1 String 1
+ CHAR8 SystemInfoProductName[0x20]; // Structure Type 1 String 2
+ CHAR8 SystemInfoVersion[0x18]; // Structure Type 1 String 3
+ CHAR8 SystemInfoSerialNumber[0x20]; // Structure Type 1 String 4
+ CHAR8 BaseBoardManufacturer[0x20]; // Structure Type 2 String 1
+ CHAR8 BaseBoardProductName[0x20]; // Structure Type 2 String 2
+ CHAR8 BaseBoardVersion[0x18]; // Structure Type 2 String 3
+ CHAR8 BaseBoardSerialNumber[0x20]; // Structure Type 2 String 4
+ CHAR8 ChassisManufacturer[0x20]; // Structure Type 3 String 1
+ UINT8 ChassisType; // Enumerated
+ CHAR8 ChassisVersion[0x18]; // Structure Type 3 String 2
+ CHAR8 ChassisSerialNumber[0x20]; // Structure Type 3 String 3
+ CHAR8 ChassisAssetTag[0x20]; // Structure Type 3 String 4
+ UINT8 MfgAccessKeyWorkspace;
+ UINT8 ChecksumFixupPool[0xd]; // Checksum Fix-ups
+ UINT8 SwitchboardData[4]; // 32 switch switchboard
+ UINT8 IntelReserved; // Reserved for Future Use
+} DMI_DATA;
+
+#define DMI_DATA_GUID \
+ { \
+ 0x70e56c5e, 0x280c, 0x44b0, 0xa4, 0x97, 0x09, 0x68, 0x1a, 0xbc, 0x37, 0x5e \
+ }
+
+#define DMI_DATA_NAME (L"DmiData")
+#define ASCII_DMI_DATA_NAME ("DmiData")
+
+extern EFI_GUID gDmiDataGuid;
+extern CHAR16 gDmiDataName[];
+
+//
+// UUID - universally unique system id
+//
+#define UUID_VARIABLE_GUID \
+ { \
+ 0xd357c710, 0x0ada, 0x4717, 0x8d, 0xba, 0xc6, 0xad, 0xc7, 0xcd, 0x2b, 0x2a \
+ }
+
+#define UUID_VARIABLE_NAME (L"UUID")
+#define ASCII_UUID_VARIABLE_NAME ("UUID")
+
+//
+// UUID data
+//
+typedef struct {
+ UINT32 UuidHigh;
+ UINT32 UuidLow;
+} SYSTEM_1394_UUID;
+
+typedef struct {
+ EFI_GUID SystemUuid; // System Unique ID
+ SYSTEM_1394_UUID System1394Uuid; // Onboard 1394 UUID
+} UUID_DATA;
+
+extern EFI_GUID gUuidVariableGuid;
+extern CHAR16 gUuidVariableName[];
+
+//
+// MB32GUID for Computrace
+//
+
+#define MB32_GUID \
+ { 0x539D62BA, 0xDE35, 0x453E, 0xBA, 0xB0, 0x85, 0xDB, 0x8D, 0xA2, 0x42, 0xF9 }
+
+#define MB32_VARIABLE_NAME (L"MB32")
+#define ASCII_MB32_VARIABLE_NAME ("MB32")
+
+extern EFI_GUID gMb32Guid;
+extern CHAR16 gMb32VariableName[];
+
+//
+// SLP 2.0 OEM Public Key
+//
+#define SLP20_OEMPUBLICKEY_VARIABLE_GUID \
+ {0xa4d622d, 0x1f4, 0x4974, 0xb3, 0xf5, 0x2b, 0xfe, 0x98, 0x88, 0xef, 0x92}
+#define SLP20_OEMPUBLICKEY_VARIABLE_NAME (L"SLP20OEMPublicKey")
+#define ASCII_SLP20_OEMPUBLICKEY_VARIABLE_NAME ("SLP20OEMPublicKey")
+
+extern EFI_GUID gSLP20OEMPublicKeyVariableGuid;
+extern CHAR16 gSLP20OEMPublicKeyVariableName[];
+
+//
+// SLP 2.0 Marker
+//
+#define SLP20_MARKER_VARIABLE_GUID \
+ {0xec2a6c28, 0x2286, 0x44ed, 0x91, 0x6b, 0x24, 0x3a, 0xb5, 0x25, 0x35, 0x46}
+#define SLP20_MARKER_VARIABLE_NAME (L"SLP20Marker")
+#define ASCII_SLP20_MARKER_VARIABLE_NAME ("SLP20Marker")
+
+extern EFI_GUID gSLP20MarkerVariableGuid;
+extern CHAR16 gSLP20MarkerVariableName[];
+
+//
+// SLP 2.0 Encrypted OEM Public Key
+//
+#define SLP20_ENCRYPTEDOEMPUBLICKEY_VARIABLE_GUID \
+ {0x6d9bf711, 0xa90d, 0x42f9, 0xa3, 0xfb, 0xdd, 0x8, 0xb6, 0xe8, 0x90, 0x37}
+#define SLP20_ENCRYPTEDOEMPUBLICKEY_VARIABLE_NAME (L"SLP20EncryptedOEMPublicKey")
+#define ASCII_SLP20_ENCRYPTEDOEMPUBLICKEY_VARIABLE_NAME ("SLP20EncryptedOEMPublicKey")
+
+extern EFI_GUID gSLP20EncryptedOEMPublicKeyVariableGuid;
+extern CHAR16 gSLP20EncryptedOEMPublicKeyVariableName[];
+
+//
+// ACPI OSFR Manufacturer String
+//
+#define ACPI_OSFR_MFG_STRING_VARIABLE_GUID \
+ {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
+#define ACPI_OSFR_MFG_STRING_VARIABLE_NAME (L"OcurMfg")
+#define ASCII_ACPI_OSFR_MF_STRING_VARIABLE_NAME ("OcurMfg")
+
+extern EFI_GUID gACPIOSFRMfgStringVariableGuid;
+
+//
+// ACPI OSFR Model String
+//
+#define ACPI_OSFR_MODEL_STRING_VARIABLE_GUID \
+ {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
+#define ACPI_OSFR_MODEL_STRING_VARIABLE_NAME (L"OcurModel")
+#define ASCII_ACPI_OSFR_MODEL_STRING_VARIABLE_NAME ("OcurModel")
+
+extern EFI_GUID gACPIOSFRModelStringVariableGuid;
+
+//
+// ACPI OSFR Reference Data Block
+//
+#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_GUID \
+ {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
+#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME (L"OcurRef")
+#define ASCII_ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME ("OcurRef")
+extern EFI_GUID gACPIOSFRRefDataBlockVariableGuid;
+
+//
+// Manufacturing mode GUID
+//
+#define MfgMode_GUID \
+ { 0xEF14FD78, 0x0793, 0x4e2b, 0xAC, 0x6D, 0x06, 0x28, 0x47, 0xE0, 0x17, 0x91 }
+
+#define MFGMODE_VARIABLE_NAME (L"MfgMode")
+#define ASCII_MFGMODE_VARIABLE_NAME ("MfgMode")
+
+typedef struct {
+ UINT8 MfgModeData;
+} MFG_MODE_VAR;
+
+extern EFI_GUID gMfgModeVariableGuid;
+extern CHAR16 gMfgModeVariableName[];
+
+#pragma pack()
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/FirmwareId.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/FirmwareId.h new file mode 100644 index 0000000000..b4ad7db611 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/FirmwareId.h @@ -0,0 +1,60 @@ +/** @file
+ Header file for Firmware ID.
+
+ Copyright (c) 2003 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FirmwareId_h_GUID_included
+#define _FirmwareId_h_GUID_included
+
+#pragma pack(1)
+
+//
+// Firmware ID
+//
+
+#define FIRMWARE_ID_MAX_LENGTH 35
+
+typedef struct {
+ CHAR8 BiosId[8];
+ CHAR8 Separator1;
+ CHAR8 OemId[3];
+ CHAR8 Separator2;
+ CHAR8 BuildId[4];
+ CHAR8 Separator3;
+ CHAR8 Century[2];
+ CHAR8 Year[2];
+ CHAR8 Separator4;
+ CHAR8 Month[2];
+ CHAR8 Date[2];
+ CHAR8 Separator5;
+ CHAR8 Hour[2];
+ CHAR8 Minute[2];
+ CHAR8 Dummy[3];
+} FIRMWARE_ID_DATA;
+
+#define OLD_FIRMWARE_ID_GUID \
+ {0xefc071ae, 0x41b8, 0x4018, 0xaf, 0xa7, 0x31, 0x4b, 0x18, 0x5e, 0x57, 0x8b}
+
+#define FIRMWARE_ID_GUID \
+ {0x5e559c23, 0x1faa, 0x4ae1, 0x8d, 0x4a, 0xc6, 0xcf, 0x02, 0x6c, 0x76, 0x6f}
+
+#define FIRMWARE_ID_NAME L"FirmwareId"
+#define FIRMWARE_ID_NAME_WITH_PASSWORD FIRMWARE_ID_NAME L"H#8,^-!t"
+
+extern EFI_GUID gFirmwareIdGuid;
+extern CHAR16 gFirmwareIdName[];
+
+#pragma pack()
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/HwWatchdogTimerHob.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/HwWatchdogTimerHob.h new file mode 100644 index 0000000000..7ee63fb51d --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/HwWatchdogTimerHob.h @@ -0,0 +1,133 @@ +/** @file
+ GUID used for Watchdog Timer status in the HOB list.
+
+ Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_WATCHDOG_TIMER_HOB_GUID_H_
+#define _EFI_WATCHDOG_TIMER_HOB_GUID_H_
+
+#define EFI_WATCHDOG_TIMER_HOB_GUID \
+ { 0x226cd3f, 0x69b5, 0x4150, 0xac, 0xbe, 0xbf, 0xbf, 0x18, 0xe3, 0x3, 0xd5 }
+
+#define EFI_WATCHDOG_TIMER_DEFINITION_HOB_GUID \
+ { 0xd29302b0, 0x11ba, 0x4073, 0xa2, 0x27, 0x53, 0x8d, 0x25, 0x42, 0x70, 0x9f }
+
+typedef enum {
+ HWWD_NONE,
+ HWWD_TIMER_EXPIRED,
+ HWWD_SPONTANEOUS_REBOOT,
+ HWWD_FORCED_TIMEOUT
+} HW_WATCHDOG_TIMEOUT;
+
+typedef struct {
+ HW_WATCHDOG_TIMEOUT TimeoutStatus;
+} HW_WATCHDOG_INFO;
+
+//
+// Watchdog timer action values
+//
+#define WDT_ACTION_RESET 0x01 // reload/reset timer
+#define WDT_ACTION_QUERY_CURRENT_VALUE 0x04 // get current value // DON'T NEED FOR OVERCLOCK UTILITY
+#define WDT_ACTION_QUERY_COUNTDOWN_PERIOD 0x05 // get countdown period
+#define WDT_ACTION_SET_COUNTDOWN_PERIOD 0x06 // set countdown period
+#define WDT_ACTION_QUERY_RUNNING_STATE 0x08 // query if running
+#define WDT_ACTION_SET_RUNNING_STATE 0x09 // start timer
+#define WDT_ACTION_QUERY_STOPPED_STATE 0x0A // query if stopped
+#define WDT_ACTION_SET_STOPPED_STATE 0x0B // stop timer
+#define WDT_ACTION_QUERY_STATUS 0x20 // is current boot cause by wdt timeout?
+#define WDT_ACTION_SET_STATUS 0x21 // resets wdt status bit
+
+//
+// Watchdog timer instruction values
+//
+#define WDT_INSTR_VALUE_MASK 0x03 // Mask for just the value
+#define WDT_INSTR_READ_CMP_VALUE 0x00 // Read / compare value
+#define WDT_INSTR_READ_COUNTDOWN 0x01 // read countdown value
+#define WDT_INSTR_WRITE_VALUE 0x02 // Write value
+#define WDT_INSTR_WRITE_COUNTDOWN 0x03 // write countdown value
+#define WDT_INSTR_PRESERVE_REG 0x80 // preserve reg; used in Write Value / Write Countdown
+#define WDT_INSTR_WRITE_VALUE_PRES (0x02 | WDT_INSTR_PRESERVE_REG) // Write value with preserve
+#define WDT_INSTR_WRITE_COUNTDOWN_PRES (0x03 | WDT_INSTR_PRESERVE_REG) // write countdown value with preserve
+
+//
+// The Generic Address Structure is defined in the ACPI Specification and should only be
+// changed to match updated revisions of that specification. The GAS_ADDRESS_SPACE and
+// GAS_ACCESS_SIZE enumerations are also defined by the ACPI Specification.
+//
+
+typedef enum {
+ GAS_SYSTEM_MEMORY,
+ GAS_SYSTEM_IO,
+ GAS_PCI_CONFIG_SPACE,
+ GAS_EMBEDDED_CONTROLLER,
+ GAS_SMBUS
+} GAS_ADDRESS_SPACE;
+
+typedef enum {
+ GAS_UNDEFINED,
+ GAS_BYTE_ACCESS,
+ GAS_WORD_ACCESS,
+ GAS_DWORD_ACCESS,
+ GAS_QWORD_ACCESS
+} GAS_ACCESS_SIZE;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} GENERIC_ADDRESS_STRUCTURE;
+
+//
+// GAS_SYSTEM_MEMORY - When used as the AddressSpaceId, the 64-bit physical memory address
+// of the register. 32-bit platforms must have the high DWORD set to 0.
+// GAS_SYSTEM_IO - The 64-bit I/O address of the register. 32-bit platforms must have
+// the high DWORD set to 0.
+// GAS_PCI_CONFIG_SPACE - PCI Configuration space addresses must be confined to devices on PCI
+// Sepment Group 0, Bus 0. This restriction exists to accommodate access
+// to fixed hardware prior to PCI bus enumeration. The format of addresses
+// are defined as follows:
+// Highest WORD: Reserved and must be -0-
+// ... PCI Device number on bus 0
+// ... PCI Function number
+// Lowest WORD: Offset in the configuration space header
+//
+
+
+typedef struct {
+ UINT8 WdAction;
+ UINT8 Flag;
+ UINT16 Res;
+ GENERIC_ADDRESS_STRUCTURE GenericAddressStructures;
+ UINT32 Value;
+ UINT32 Mask;
+} WD_INSTRUCTION;
+
+typedef struct {
+ UINT32 TimerPeriod;
+ UINT32 MaxTimerCount;
+ UINT32 MinTimerCount;
+ UINT16 InstructionCount;
+ WD_INSTRUCTION ActionDefinitions[1];
+} WD_HOB_DEFINITION;
+
+#pragma pack()
+
+extern EFI_GUID gWatchdogTimerHobGuid;
+extern EFI_GUID gWatchdogTimerDefinitionHobGuid;
+
+#endif // _EFI_WATCHDOG_TIMER_HOB_GUID_H_
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/IdccData.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/IdccData.h new file mode 100644 index 0000000000..14cbb08b90 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/IdccData.h @@ -0,0 +1,102 @@ +/** @file
+ Header file for IccData.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IDCCDATAHUB_GUID_H_
+#define _IDCCDATAHUB_GUID_H_
+
+//
+// This GUID is for the IDCC related data found in the Data Hub
+//
+#define IDCC_DATA_HUB_GUID \
+ { 0x788e1d9f, 0x1eab, 0x47d2, 0xa2, 0xf3, 0x78, 0xca, 0xe8, 0x7d, 0x60, 0x12 }
+
+extern EFI_GUID gIdccDataHubGuid;
+
+#pragma pack(1)
+typedef struct {
+ UINT32 Type;
+ UINT32 RecordLength;
+} EFI_IDCC_DATA_HEADER;
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 Tcontrol;
+} EFI_IDCC_TCONTROL;
+
+typedef struct {
+ UINT32 EntryCount;
+} EFI_IDCC_CLOCK_COMMON;
+
+typedef struct {
+ UINT8 Polarity;
+ UINT8 Percent;
+ UINT32 FpValue;
+} EFI_IDCC_TYPE_2_DATA;
+
+typedef struct {
+ UINT8 SetupVal;
+ UINT32 FpValue;
+} EFI_IDCC_TYPE_3_4_DATA;
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 ProcessorRatio;
+} EFI_IDCC_PROCESSOR_RATIO;
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 BoardFormFactor;
+} EFI_IDCC_BOARD_FORM_FACTOR;
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 ProcessorInfo;
+} EFI_IDCC_PROCESSOR_INFO;
+
+#define EFI_IDCC_PROCESSOR_UNCON (1 << 0) // Bit 0: UnCon CPU
+#define EFI_IDCC_PROCESSOR_UNLOCK (1 << 1) // Bit 1: UnLock CPU
+#define EFI_IDCC_PROCESSOR_CNR (1 << 2) // Bit 2: CNR CPU
+#define EFI_IDCC_PROCESSOR_KNF (1 << 3) // Bit 3: KNF CPU
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 MinFSB;
+ UINT32 MaxFSB;
+ UINT8 StepFSB;
+} EFI_IDCC_FSB_DATA;
+
+#pragma pack()
+
+#define EFI_IDCC_POSITIVE 0
+#define EFI_IDCC_NEGATIVE 1
+
+//
+// Board Form Factor equates
+//
+#define ATX_FORM_FACTOR 0x00
+#define BTX_FORM_FACTOR 0x01
+
+
+#define EFI_IDCC_TCONTROL_TYPE 1
+#define EFI_IDCC_FSB_TYPE 2
+#define EFI_IDCC_PCI_TYPE 3
+#define EFI_IDCC_PCIE_TYPE 4
+#define EFI_IDCC_PROC_RATIO_TYPE 5
+#define EFI_IDCC_BOARD_FORM_FACTOR_TYPE 6
+#define EFI_IDCC_PROC_INFO_TYPE 7
+#define EFI_IDCC_FSB_DATA_TYPE 8
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/MemoryConfigData.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..bad759911d --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/MemoryConfigData.h @@ -0,0 +1,29 @@ +/** @file
+ GUID used for Memory Configuration Data entries in the HOB list.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEMORY_CONFIG_DATA_GUID_H_
+#define _MEMORY_CONFIG_DATA_GUID_H_
+
+#define EFI_MEMORY_CONFIG_DATA_GUID \
+ { \
+ 0x80dbd530, 0xb74c, 0x4f11, 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 \
+ }
+
+#define EFI_MEMORY_CONFIG_VARIABLE_NAME L"MemoryConfig"
+extern EFI_GUID gEfiMemoryConfigDataGuid;
+extern CHAR16 EfiMemoryConfigVariable[];
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PciLanInfo.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PciLanInfo.h new file mode 100644 index 0000000000..7142646af9 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PciLanInfo.h @@ -0,0 +1,38 @@ +/** @file
+ Header file for Pci Lan Info.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCI_LAN_INFO_GUID_H_
+#define _PCI_LAN_INFO_GUID_H_
+
+#pragma pack(1)
+
+//
+// structure used for Pci Lan variable
+//
+typedef struct {
+ UINT8 PciBus;
+ UINT8 PciDevice;
+ UINT8 PciFunction;
+} PCI_LAN_INFO;
+
+#pragma pack()
+
+#define EFI_PCI_LAN_INFO_GUID \
+ {0xd9a1427, 0xe02a, 0x437d, 0x92, 0x6b, 0xaa, 0x52, 0x1f, 0xd7, 0x22, 0xba};
+
+extern EFI_GUID gEfiPciLanInfoGuid;
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformCpuInfo.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformCpuInfo.h new file mode 100644 index 0000000000..f46b260dba --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformCpuInfo.h @@ -0,0 +1,179 @@ +/** @file
+ GUID used for Platform CPU Info Data entries in the HOB list.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_CPU_INFO_GUID_H_
+#define _PLATFORM_CPU_INFO_GUID_H_
+
+#include <CpuType.h>
+#include <CpuDataStruct.h>
+
+
+#define EFI_PLATFORM_CPU_INFO_GUID \
+ {\
+ 0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \
+ }
+
+extern EFI_GUID gEfiPlatformCpuInfoGuid;
+extern CHAR16 EfiPlatformCpuInfoVariable[];
+
+//
+// Tri-state for feature capabilities and enable/disable.
+// [0] clear=feature isn't capable
+// [0] set =feature is capable
+// [1] clear=feature is disabled
+// [1] set =feature is enabled
+//
+#define CPU_FEATURES_CAPABLE BIT0
+#define CPU_FEATURES_ENABLE BIT1
+
+#define MAX_CACHE_DESCRIPTORS 64
+#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48
+
+#pragma pack(1)
+
+typedef struct {
+ UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF
+ UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0
+ UINT8 ExtendedFamilyId; // [27:20]
+ UINT8 ExtendedModelId; // [19:16]
+ UINT8 ProcessorType; // [13:11]
+ UINT8 FamilyId; // [11:8]
+ UINT8 Model; // [7:4]
+ UINT8 SteppingId; // [3:0]
+} EFI_CPU_VERSION_INFO; // CPUID.1.EAX
+
+typedef struct {
+ UINT32 L1InstructionCacheSize;
+ UINT32 L1DataCacheSize;
+ UINT32 L2CacheSize;
+ UINT32 L3CacheSize;
+ UINT32 TraceCacheSize;
+ UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS];
+} EFI_CPU_CACHE_INFO; // CPUID.2.EAX
+
+typedef struct {
+ UINT8 PhysicalPackages;
+ UINT8 LogicalProcessorsPerPhysicalPackage;
+ UINT8 CoresPerPhysicalPackage;
+ UINT8 ThreadsPerCore;
+} EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX
+
+typedef struct {
+ UINT32 RegEdx; // CPUID.5.EAX
+ UINT8 MaxCState;
+ UINT8 C0SubCStatesMwait; // EDX [3:0]
+ UINT8 C1SubCStatesMwait; // EDX [7:4]
+ UINT8 C2SubCStatesMwait; // EDX [11:8]
+ UINT8 C3SubCStatesMwait; // EDX [15:12]
+ UINT8 C4SubCStatesMwait; // EDX [19:16]
+ UINT8 C5SubCStatesMwait; // EDX [23:20]
+ UINT8 C6SubCStatesMwait; // EDX [27:24]
+ UINT8 C7SubCStatesMwait; // EDX [31:28]
+ UINT8 MonitorMwaitSupport; // ECX [0]
+ UINT8 InterruptsBreakMwait; // ECX [1]
+} EFI_CPU_CSTATE_INFO; // CPUID.5.EAX
+
+typedef struct {
+ UINT8 Turbo; // EAX [1]
+ UINT8 PECI; // EAX [0]
+ UINT8 NumIntThresholds; // EBX [3:0]
+ UINT8 HwCoordinationFeedback; // ECX [0]
+} EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX
+
+//
+// IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.
+// - Keep the respective feature entry variable as default value (0x00)
+// if the CPU is not capable for the feature.
+// - Use the specially defined programming convention to update the variable
+// to indicate capable, enable or disable.
+// ie. F_CAPABLE for feature available
+// F_ENABLE for feature enable
+// F_DISABLE for feature disable
+//
+typedef struct {
+ EFI_CPUID_REGISTER Regs; // CPUID.1.EAX
+ UINT8 Aes; // ECX [25]
+ UINT8 Xapic; // ECX [21]
+ UINT8 SSE4_2; // ECX [20]
+ UINT8 SSE4_1; // ECX [19]
+ UINT8 Dca; // ECX [18]
+ UINT8 SupSSE3; // ECX [9]
+ UINT8 Tm2; // ECX [8]
+ UINT8 Eist; // ECX [7]
+ UINT8 Lt; // ECX [6]
+ UINT8 Vt; // ECX [5]
+ UINT8 Mwait; // ECX [3]
+ UINT8 SSE3; // ECX [0]
+ UINT8 Tcc; // EDX [29]
+ UINT8 Mt; // EDX [28]
+ UINT8 SSE2; // EDX [26]
+ UINT8 SSE; // EDX [25]
+ UINT8 MMX; // EDX [23]
+ EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX
+ UINT8 ExtLahfSahf64; // ECX [0]
+ UINT8 ExtIntel64; // EDX [29]
+ UINT8 ExtXd; // EDX [20]
+ UINT8 ExtSysCallRet64; // EDX [11]
+ UINT16 Ht; // CPUID.0B.EAX EBX [15:0]
+} EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX
+
+typedef struct {
+ UINT8 PhysicalBits;
+ UINT8 VirtualBits;
+} EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX
+
+typedef struct {
+ UINT8 PlatformID; // MSR 0x17 [52:50]
+ UINT32 MicrocodeRevision; // MSR 0x8B [63:32]
+ UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40]
+ UINT8 DdrRatioUnlockCap; // MSR 0xCE [30]
+ UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29]
+ UINT8 RatioLimitsTurbo; // MSR 0xCE [28]
+ UINT8 PreProduction; // MSR 0xCE [27]
+ UINT8 DcuModeSelect; // MSR 0xCE [26]
+ UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8]
+ UINT8 Emrr; // MSR 0xFE [12]
+ UINT8 Smrr; // MSR 0xFE [11]
+ UINT8 VariableMtrrCount; // MSR 0xFE [7:0]
+ UINT16 PState; // MSR 0x198 [15:0]
+ UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16]
+ UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8]
+ UINT32 PCIeBar; // MSR 0x300 [39:20]
+ UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1]
+} EFI_MSR_FEATURES;
+
+typedef struct {
+ BOOLEAN IsIntelProcessor;
+ UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];
+ UINT32 CpuidMaxInputValue;
+ UINT32 CpuidMaxExtInputValue;
+ EFI_CPU_UARCH CpuUarch;
+ EFI_CPU_FAMILY CpuFamily;
+ EFI_CPU_PLATFORM CpuPlatform;
+ EFI_CPU_TYPE CpuType;
+ EFI_CPU_VERSION_INFO CpuVersion;
+ EFI_CPU_CACHE_INFO CpuCache;
+ EFI_CPU_FEATURES CpuFeatures;
+ EFI_CPU_CSTATE_INFO CpuCState;
+ EFI_CPU_PACKAGE_INFO CpuPackage;
+ EFI_CPU_POWER_MANAGEMENT CpuPowerManagement;
+ EFI_CPU_ADDRESS_BITS CpuAddress;
+ EFI_MSR_FEATURES Msr;
+} EFI_PLATFORM_CPU_INFO;
+
+#pragma pack()
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h new file mode 100644 index 0000000000..aed58998c7 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h @@ -0,0 +1,250 @@ +/** @file
+ GUID used for Platform Info Data entries in the HOB list.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_INFO_GUID_H_
+#define _PLATFORM_INFO_GUID_H_
+
+#include <PiPei.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Protocol/DevicePath.h>
+
+#include <SmipGenerated.h>
+
+
+#define SMIP_GPIO_ENABLE FALSE
+#define PLATFORM_INFO_REVISION 1 // revision id for current platform information struct
+//
+// Start::Broxton Board Defines
+//
+#define BOARD_REVISION_DEFAULT 0xff
+#define UNKNOWN_FABID 0x0F
+#define FAB_ID_MASK 0x0F
+#define BOARD_ID_2 0x01
+#define BOARD_ID_1 0x40
+#define BOARD_ID_0 0x04
+
+#define BOARD_ID_DT_CRB 0x0
+
+#define DC_ID_DDR3L 0x00
+#define DC_ID_DDR3 0x04
+#define DC_ID_LPDDR3 0x02
+#define DC_ID_LPDDR2 0x06
+#define DC_ID_DDR4 0x01
+#define DC_ID_DDR3L_ECC 0x05
+#define DC_ID_NO_MEM 0x07
+//
+// End::Broxton Board Defines
+//
+
+#define MAX_FAB_ID_RETRY_COUNT 100
+#define MAX_FAB_ID_CHECK_COUNT 3
+
+#define PLATFORM_INFO_HOB_REVISION 0x1
+
+#define EFI_PLATFORM_INFO_GUID \
+ { \
+ 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
+ }
+
+#define GetCommOffset(Community, Offset) (((UINT32)Community) << 16) + GPIO_PADBAR + Offset
+
+//
+// Setup option for multi-BOM selection
+//
+#define BOM_MANUALLY 0x80
+#define BOM_FROM_PSS 0xFF
+
+extern EFI_GUID gEfiPlatformInfoGuid;
+extern EFI_GUID gIFWIVersionHobGuid;
+
+
+typedef enum {
+ FlavorUnknown = 0,
+ //
+ // Mobile
+ //
+ FlavorMobile = 1,
+ //
+ // Desktop
+ //
+ FlavorDesktop = 2,
+ //
+ // Tablet
+ //
+ FlavorTablet = 3
+} PLATFORM_FLAVOR;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT16 PciResourceIoBase;
+ UINT16 PciResourceIoLimit;
+ UINT32 PciResourceMem32Base;
+ UINT32 PciResourceMem32Limit;
+ UINT64 PciResourceMem64Base;
+ UINT64 PciResourceMem64Limit;
+ UINT64 PciExpressBase;
+ UINT32 PciExpressSize;
+ UINT8 PciHostAddressWidth;
+ UINT8 PciResourceMinSecBus;
+} EFI_PLATFORM_PCI_DATA;
+
+typedef struct {
+ UINT8 CpuAddressWidth;
+ UINT32 CpuFamilyStepping;
+} EFI_PLATFORM_CPU_DATA;
+
+typedef struct {
+ UINT8 SysIoApicEnable;
+ UINT8 SysSioExist;
+} EFI_PLATFORM_SYS_DATA;
+
+typedef struct {
+ UINT32 MemTolm;
+ UINT32 MemMaxTolm;
+ UINT32 MemTsegSize;
+ UINT32 MemTsegBase;
+ UINT32 MemIedSize;
+ UINT32 MemIgdSize;
+ UINT32 MemIgdBase;
+ UINT32 MemIgdGttSize;
+ UINT32 MemIgdGttBase;
+ UINT64 MemMir0;
+ UINT64 MemMir1;
+ UINT32 MemConfigSize;
+ UINT16 MmioSize;
+} EFI_PLATFORM_MEM_DATA;
+
+typedef struct {
+ UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address
+ UINT8 IgdBootType; // IGD Boot Display Device
+ UINT8 IgdPanelType; // IGD Panel Type CMOs option
+ UINT8 IgdTvFormat; // IGD TV Format CMOS option
+ UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option
+ UINT8 IgdPanelScaling; // IGD Panel Scaling
+ UINT8 IgdBlcConfig; // IGD BLC Configuration
+ UINT8 IgdBiaConfig; // IGD BIA Configuration
+ UINT8 IgdSscConfig; // IGD SSC Configuration
+ UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size
+ UINT8 IgdFunc1Enable; // IGD Function 1 Enable
+ UINT8 IgdHpllVco; // HPLL VCO
+ UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)
+ UINT8 IgdPAVP; // IGD PAVP data
+} EFI_PLATFORM_IGD_DATA;
+
+//
+// Read Board ID and FAB ID from PSS chip that prefix 2 additional characters to IPN string,
+// This design start from FAB-D board. (e.g. RDH28336-201, RD for Broxton RVP FAB-D)
+// The first character can be used for identify different board (RVP, PR, FFD...),
+// and second character can be used for different Board revision (FAB-A, FAB-B...)
+//
+
+typedef enum {
+ BOARD_ID_BXT_GrosseTete = 0x82, // Grosse Tete Board
+ UNKNOWN_BOARD = 0xFF // Unknown Board
+} BOARD_ID_LIST;
+
+#define BOARD_ID_BXT_KsankaGt_MASK 0x8F
+
+typedef enum {
+ BOARD_ID_LFH_CRB = 0x07, // Leaf Hill
+ BOARD_ID_MINNOW = 0x80, // Minnow Board
+ BOARD_ID_APL_UNKNOWN = 0xFF
+} APL_BOARD_ID_LIST;
+
+typedef enum {
+ FAB_ID_RVP_B_C = 0x0, // For Broxton FAB B/C, special define
+ FAB_ID_A = 0x1, // FAB A
+ FAB_ID_B = 0x2, // FAB B
+ FAB_ID_C = 0x3, // FAB C
+ FAB_ID_D = 0x4, // FAB D
+ FAB_ID_E = 0x5, // FAB E
+ FAB_ID_F = 0x6, // FAB F
+ UNKNOWN_FAB = 0xFF // Unknown FAB
+} FAB_ID_LIST;
+
+typedef enum {
+ TPM_DISABLE = 0, // TPM Disable
+ TPM_PTT = 1, // PTT (fTPM)
+ TPM_DTPM_1_2 = 2, // Discrete TPM 1.2
+ TPM_DTPM_2_0 = 3 // Discrete TPM 2.0
+} TPM_DEVICE;
+
+typedef struct _EFI_PLATFORM_INFO_HOB {
+ UINT16 PlatformType; // Platform Type
+ UINT8 BoardId; // Board ID
+ UINT8 BoardRev; // Board Revision
+ UINT8 DockId; // Dock ID
+ UINT8 OsSelPss; // PSS OS Selection
+ UINT8 BomIdPss; // PSS BOM ID
+ PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor
+ UINT8 ECOId; // ECO applied on platform
+ UINT16 IohSku;
+ UINT8 IohRevision;
+ UINT16 IchSku;
+ UINT8 IchRevision;
+ EFI_PLATFORM_PCI_DATA PciData;
+ EFI_PLATFORM_CPU_DATA CpuData;
+ EFI_PLATFORM_MEM_DATA MemData;
+ EFI_PLATFORM_SYS_DATA SysData;
+ EFI_PLATFORM_IGD_DATA IgdData;
+ UINT8 RevisonId; // Structure Revision ID
+ UINT32 SsidSvid;
+ UINT16 AudioSubsystemDeviceId;
+ UINT64 AcpiOemId;
+ UINT64 AcpiOemTableId;
+ UINT16 FABID;
+ UINT8 CfioEnabled;
+ UINT8 OsSelection; // OS Selection 0: WOS 1:AOS 2:Win7
+ UINT32 FvMain3Base;
+ UINT32 FvMain3Length;
+ UINT8 ECPresent;
+ UINT8 PmicVersion;
+ UINT8 TxeMeasurementHash[32];
+ UINT8 RTEn;
+ UINT8 EcMajorRevision;
+ UINT8 EcMinorRevision;
+ PlatfromMultiBOMConf PlatformBOMValue;
+ PlatfromFeatureConf PlatformFeatureValue;
+ UINT32 SmipGpioBaseTableLength;
+ UINT32 SmipGpioDiffTableLength;
+ GPIO_CONFIG_SMIP SmipGpioBaseTable[16]; // Temp solution MRC stack overflow
+ GPIO_CONFIG_SMIP SmipGpioDiffTable[16];
+
+ //
+ // Caveat: Must place pointer entries at the end of the structure.
+ // Pointer in structure will result in size difference between 32bit and 64bit compilation.
+ //
+} EFI_PLATFORM_INFO_HOB;
+
+typedef enum {
+ TOUCH_DISABLE = 0,
+ TOUCH_DISCRETE = 1,
+ TOUCH_INTEGRATED = 2
+} TOUCH_ID_LIST;
+
+#pragma pack()
+
+EFI_STATUS
+GetPlatformInfoHob (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h new file mode 100644 index 0000000000..d02afcbd22 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h @@ -0,0 +1,283 @@ +/** @file
+ GUID used for Platform Info Data entries in the HOB list.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_INFO_GUID_H_
+#define _PLATFORM_INFO_GUID_H_
+
+#include <PiPei.h>
+
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/SmbusLib.h>
+#include <IndustryStandard/SmBus.h>
+
+#define PLATFORM_INFO_REVISION 1 // revision id for current platform information structure
+
+//
+// Start::BayLake Board Defines
+//
+#define BOARD_REVISION_DEFAULT 0xff
+#define UNKNOWN_FABID 0x0F
+#define FAB_ID_MASK 0x0F
+#define BOARD_ID_2 0x01
+#define BOARD_ID_1 0x40
+#define BOARD_ID_0 0x04
+
+#define BOARD_ID_DT_CRB 0x0
+#define BOARD_ID_DT_VLVR 0x1
+#define BOARD_ID_SVP_VLV 0xC
+#define BOARD_ID_SVP_EV_VLV 0xD
+//
+// End::BayLake Board Defines
+//
+
+//
+// Start::Alpine Valley Board Defines
+//
+#define DC_ID_DDR3L 0x00
+#define DC_ID_DDR3 0x04
+#define DC_ID_LPDDR3 0x02
+#define DC_ID_LPDDR2 0x06
+#define DC_ID_DDR4 0x01
+#define DC_ID_DDR3L_ECC 0x05
+#define DC_ID_NO_MEM 0x07
+//
+// End::Alpine Valley Board Defines
+//
+
+#define MAX_FAB_ID_RETRY_COUNT 100
+#define MAX_FAB_ID_CHECK_COUNT 3
+
+#define PLATFORM_INFO_HOB_REVISION 0x1
+
+#define EFI_PLATFORM_INFO_GUID \
+ { \
+ 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
+ }
+
+#define GetCommOffset(Community, Offset) (((UINT32)Community) << 16) + GPIO_PADBAR + Offset
+extern EFI_GUID gEfiPlatformInfoGuid;
+extern EFI_GUID gIFWIVersionHobGuid;
+
+typedef enum {
+ FlavorUnknown = 0,
+ //
+ // Mobile
+ //
+ FlavorMobile = 1,
+ //
+ // Desktop
+ //
+ FlavorDesktop = 2,
+ //
+ // Tablet
+ //
+ FlavorTablet = 3
+} PLATFORM_FLAVOR;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT16 PciResourceIoBase;
+ UINT16 PciResourceIoLimit;
+ UINT32 PciResourceMem32Base;
+ UINT32 PciResourceMem32Limit;
+ UINT64 PciResourceMem64Base;
+ UINT64 PciResourceMem64Limit;
+ UINT64 PciExpressBase;
+ UINT32 PciExpressSize;
+ UINT8 PciHostAddressWidth;
+ UINT8 PciResourceMinSecBus;
+} EFI_PLATFORM_PCI_DATA;
+
+typedef struct {
+ UINT8 CpuAddressWidth;
+ UINT32 CpuFamilyStepping;
+} EFI_PLATFORM_CPU_DATA;
+
+typedef struct {
+ UINT8 SysIoApicEnable;
+ UINT8 SysSioExist;
+} EFI_PLATFORM_SYS_DATA;
+
+typedef struct {
+ UINT32 MemTolm;
+ UINT32 MemMaxTolm;
+ UINT32 MemTsegSize;
+ UINT32 MemTsegBase;
+ UINT32 MemIedSize;
+ UINT32 MemIgdSize;
+ UINT32 MemIgdBase;
+ UINT32 MemIgdGttSize;
+ UINT32 MemIgdGttBase;
+ UINT64 MemMir0;
+ UINT64 MemMir1;
+ UINT32 MemConfigSize;
+ UINT16 MmioSize;
+} EFI_PLATFORM_MEM_DATA;
+
+typedef struct {
+ UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address
+ UINT8 IgdBootType; // IGD Boot Display Device
+ UINT8 IgdPanelType; // IGD Panel Type CMOs option
+ UINT8 IgdTvFormat; // IGD TV Format CMOS option
+ UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option
+ UINT8 IgdPanelScaling; // IGD Panel Scaling
+ UINT8 IgdBlcConfig; // IGD BLC Configuration
+ UINT8 IgdBiaConfig; // IGD BIA Configuration
+ UINT8 IgdSscConfig; // IGD SSC Configuration
+ UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size
+ UINT8 IgdFunc1Enable; // IGD Function 1 Enable
+ UINT8 IgdHpllVco; // HPLL VCO
+ UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)
+ UINT8 IgdPAVP; // IGD PAVP data
+} EFI_PLATFORM_IGD_DATA;
+
+typedef enum {
+ BOARD_ID_LFH_CRB = 0x07, // Leaf Hill
+ BOARD_ID_MINNOW = 0x80, // Minnow Board
+ BOARD_ID_APL_UNKNOWN = 0xFF
+} APL_BOARD_ID_LIST;
+
+typedef enum {
+ FAB1 = 0,
+ FAB2 = 1,
+ FAB3 = 2,
+ FAB_ID_D = 0x4, // FAB D
+} FAB_ID_LIST;
+
+typedef enum {
+ PR0 = 0, // FFRD10 PR0
+ PR05 = 1, // FFRD10 PR0.3 and PR 0.5
+ PR1 = 2, // FFRD10 PR1
+ PR11 = 3 // FFRD10 PR1.1
+} FFRD_ID_LIST;
+
+typedef enum {
+ FFRD_8_PR0 = 1, // FFRD8 PR0
+ FFRD_8_PR1 = 2 // FFRD8 PR1
+} FFRD_8_ID_LIST;
+
+typedef union {
+ UINT32 famCnf;
+ struct {
+ UINT32 CurrSrcStr:3;
+ UINT32 reserve:14;
+ UINT32 odpullEn:1;
+ UINT32 odpulldir:1;
+ UINT32 hsMode:1;
+ UINT32 Reseve3:1;
+ UINT32 vpMode:1;
+ UINT32 Reseve2:2;
+ UINT32 HYSCTL:2;
+ UINT32 parkMode:1;
+ UINT32 reseve1:5;
+ } r;
+} CONF_FAMILY;
+
+typedef union {
+ UINT32 mics1;
+ struct {
+ UINT32 RCOMP_ENABLE:1; // 0 set if rcomp is enable.
+ } r;
+} BXT_FAMILY_MISC;
+
+typedef struct {
+ CONF_FAMILY confg;
+ CONF_FAMILY confg_change;
+ BXT_FAMILY_MISC family_misc;
+ UINT32 mmioAddr;
+//#ifdef EFI_DEBUG
+ CHAR16* family_name; // GPIO Family Name for debug purpose
+//#endif
+} GPIO_CONF_FAMILY_INIT;
+
+typedef enum {
+ TPM_DISABLE = 0, // TPM Disable
+ TPM_PTT = 1, // PTT (fTPM)
+ TPM_DTPM_1_2 = 2, // Discrete TPM 1.2
+ TPM_DTPM_2_0 = 3 // Discrete TPM 2.0
+} TPM_DEVICE;
+
+typedef struct _EFI_PLATFORM_INFO_HOB {
+ UINT16 PlatformType; // Platform Type
+ UINT8 BoardId; // Board ID
+ UINT8 BoardRev; // Board Revision
+ UINT8 DockId; // Dock ID
+ UINT8 OsSelPss; // PSS OS Selection
+ UINT8 BomIdPss; // PSS BOM ID
+ PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor
+ UINT8 ECOId; // ECO applied on platform
+ UINT16 IohSku;
+ UINT8 IohRevision;
+ UINT16 IchSku;
+ UINT8 IchRevision;
+ EFI_PLATFORM_PCI_DATA PciData;
+ EFI_PLATFORM_CPU_DATA CpuData;
+ EFI_PLATFORM_MEM_DATA MemData;
+ EFI_PLATFORM_SYS_DATA SysData;
+ EFI_PLATFORM_IGD_DATA IgdData;
+ UINT8 RevisonId; // Structure Revision ID
+ UINT32 SsidSvid;
+ UINT16 AudioSubsystemDeviceId;
+ UINT64 AcpiOemId;
+ UINT64 AcpiOemTableId;
+ UINT16 FABID;
+ UINT8 CfioEnabled;
+ UINT8 OsSelection; // OS Selection 0: WOS 1:AOS 2:Win7
+ UINT32 FvMain3Base;
+ UINT32 FvMain3Length;
+ UINT8 ECPresent;
+ UINT8 PmicVersion;
+ UINT8 TxeMeasurementHash[32];
+ UINT8 RTEn;
+
+ //
+ // Caveat: Must place pointer entries at the end of the structure.
+ // Pointer in structure will result in size difference between 32bit and 64bit compilation.
+ //
+ GPIO_CONF_FAMILY_INIT* PlatfornGpioFamiliesSetting;
+ BXT_GPIO_PAD_INIT* PlatformGpioSetting_S; // south Community
+ BXT_GPIO_PAD_INIT* PlatformGpioSetting_SW; // South west Community
+ BXT_GPIO_PAD_INIT* PlatformGpioSetting_W; // West Community
+ BXT_GPIO_PAD_INIT* PlatformGpioSetting_NW; // NorthWest west Community
+ BXT_GPIO_PAD_INIT* PlatformGpioSetting_N; // North Community
+ BXT_GPIO_PAD_INIT* PlatformGpioSetting_S0ix; // S0ix Based Config
+ BXT_GPIO_PAD_INIT* PlatformGpioSetting_S3; // S3 Based Config
+ BXT_GPIO_PAD_INIT* PlatformGpioSetting_SetupConfig; // Setup Based Config
+} EFI_PLATFORM_INFO_HOB;
+
+#pragma pack()
+
+EFI_STATUS
+GetPlatformInfoHob (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
+ );
+
+EFI_STATUS
+InstallPlatformClocksNotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+InstallPlatformSysCtrlGPIONotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PttPTPInstanceGuid.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PttPTPInstanceGuid.h new file mode 100644 index 0000000000..277e7f2107 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PttPTPInstanceGuid.h @@ -0,0 +1,25 @@ +/** @file
+ GUID definition for the PTT device instance.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PTT_PTP_INSTANCE_GUID_H__
+#define __PTT_PTP_INSTANCE_GUID_H__
+
+#define TPM_DEVICE_INTERFACE_TPM20_PTT_PTP \
+{ 0x93d66f66, 0x55da, 0x4f03, { 0x9b, 0x5f, 0x32, 0xcf, 0x9e, 0x54, 0x3b, 0x3a } }
+
+extern EFI_GUID gTpmDeviceInstanceTpm20PttPtpGuid;
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/SensorInfoVariable.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SensorInfoVariable.h new file mode 100644 index 0000000000..ba87ae31dd --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SensorInfoVariable.h @@ -0,0 +1,225 @@ +/** @file
+ GUID used for Sensor Info variable.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SENSOR_INFO_VAR_GUID_H_
+#define _SENSOR_INFO_VAR_GUID_H_
+
+#define SENSOR_INFO_VAR_GUID \
+ { \
+ 0xE59E7B4D, 0x06DC, 0x44AB, 0xB3, 0x6D, 0x5E, 0xD7, 0x78, 0x9C, 0x53, 0x0A \
+ }
+
+extern EFI_GUID gEfiSensorInfoVarGuid;
+extern CHAR16 gEfiSensorInfoVarName[];
+extern CHAR16 gEfiSensorInfoVarNameWithPassword[];
+
+#define SENSOR_INFO_VAR_NAME L"SensorInfoVar"
+#define SENSOR_INFO_VAR_NAME_WITH_PASSWORD SENSOR_INFO_VAR_NAME L"S4k?A^7!"
+
+//
+// Sensor/Controller usage definitions
+//
+
+#define UNKNOWN_OTHER 0
+//
+// Temperature Sensors
+//
+#define CPU_CORE_TEMPERATURE 1
+#define CPU_DIE_TEMPERATURE 2
+#define ICH_TEMPERATURE 3
+#define MCH_TEMPERATURE 4
+#define VR_TEMPERATURE 5
+#define MEMORY_TEMPERATURE 6
+#define MOTHERBOARD_AMBIENT_TEMPERATURE 7
+#define SYSTEM_AMBIENT_AIR_TEMPERATURE 8
+#define CPU_INLET_AIR_TEMPERATURE 9
+#define SYSTEM_INLET_AIR_TEMPERATURE 10
+#define SYSTEM_OUTLET_AIR_TEMPERATURE 11
+#define PSU_HOTSPOT_TEMPERATURE 12
+#define PSU_INLET_AIR_TEMPERATURE 13
+#define PSU_OUTLET_AIR_TEMPERATURE 14
+#define DRIVE_TEMPERATURE 15
+#define GPU_TEMPERATURE 16
+#define IOH_TEMPERATURE 17
+
+#define LAST_TEMPERATURE 17
+//
+// Voltage Sensors
+//
+#define PLUS_12_VOLTS 1
+#define NEG_12_VOLTS 2
+#define PLUS_5_VOLTS 3
+#define PLUS_5_VOLT_BACKUP 4
+#define NEG_5_VOLTS 5
+#define PLUS_3P3_VOLTS 6
+#define PLUS_2P5_VOLTS 7
+#define PLUS_1P5_VOLTS 8
+#define CPU_1_VCCP_VOLTAGE 9
+#define CPU_2_VCCP_VOLTAGE 10
+#define CPU_3_VCCP_VOLTAGE 11
+#define CPU_4_VCCP_VOLTAGE 12
+#define PSU_INPUT_VOLTAGE 13
+#define MCH_VCC_VOLTAGE 14
+#define PLUS_3P3_VOLT_STANDBY 15
+#define CPU_VTT_VOLTAGE 16
+#define PLUS_1P8_VOLTS 17
+
+#define LAST_VOLTAGE 17
+//
+// Fan Speed Sensors and Controllers
+//
+#define CPU_COOLING_FAN 1
+#define SYSTEM_COOLING_FAN 2
+#define MCH_COOLING_FAN 3
+#define VR_COOLING_FAN 4
+#define CHASSIS_COOLING_FAN 5
+#define CHASSIS_INLET_FAN 6
+#define CHASSIS_OUTLET_FAN 7
+#define PSU_COOLING_FAN 8
+#define PSU_INLET_FAN 9
+#define PSU_OUTLET_FAN 10
+#define DRIVE_COOLING_FAN 11
+#define GPU_COOLING_FAN 12
+#define AUX_COOLING_FAN 13
+#define IOH_COOLING_FAN 14
+
+#define LAST_FAN 14
+
+//
+// Fan Type Definitions
+//
+#define FAN_TYPE_UNKNOWN 0
+#define FAN_3WIRE_PULSE 1
+#define FAN_3WIRE_VOLTAGE 2
+#define FAN_4WIRE 3
+
+#pragma pack(1)
+
+//
+// TEMP_SENSOR_INFO - Structure providing info for a temperature sensor
+//
+typedef struct _TEMP_SENSOR_INFO {
+ UINT8 byDevice; // Device index
+ UINT8 byIndex; // Physical sensor index
+ UINT8 byUsage; // Usage indicator
+ UINT8 bRelative; // Relative vs. Absolute readings
+} TEMP_SENSOR_INFO, *P_TEMP_SENSOR_INFO;
+
+//
+//TYPEDEF_TEMP_SENSOR_SECTION - Macro that can be used to typedef the
+// TEMP_SENSOR_SECTION structure, which provides information about all
+// temperature sensors
+//
+#define TYPEDEF_TEMP_SENSOR_SECTION(count) \
+typedef struct _TEMP_SENSOR_SECTION \
+{ \
+ UINT8 byCount; \
+ TEMP_SENSOR_INFO stSensor[count]; \
+ \
+} TEMP_SENSOR_SECTION, *P_TEMP_SENSOR_SECTION
+
+//
+//VOLT_SENSOR_INFO - Structure providing info for a voltage sensor
+//
+typedef struct _VOLT_SENSOR_INFO {
+ UINT8 byDevice; // Device index
+ UINT8 byIndex; // Physical sensor index
+ UINT8 byUsage; // Usage indicator
+} VOLT_SENSOR_INFO, *P_VOLT_SENSOR_INFO;
+
+//
+//TYPEDEF_VOLT_SENSOR_SECTION - Macro that can be used to typedef the
+//VOLT_SENSOR_SECTION structure, which provides information about all
+// voltage sensors
+//
+#define TYPEDEF_VOLT_SENSOR_SECTION(count) \
+typedef struct _VOLT_SENSOR_SECTION \
+{ \
+ UINT8 byCount; \
+ VOLT_SENSOR_INFO stSensor[count]; \
+ \
+} VOLT_SENSOR_SECTION, *P_VOLT_SENSOR_SECTION
+
+//
+// FAN_SENSOR_INFO - Structure providing info for a fan speed sensor
+//
+
+typedef struct _FAN_SENSOR_INFO {
+ UINT8 byDevice; // Device index
+ UINT8 byIndex; // Physical sensor index
+ UINT8 byUsage; // Usage indicator
+ UINT8 byType; // Fan type
+ UINT8 byController; // Associated Fan Controller
+} FAN_SENSOR_INFO, *P_FAN_SENSOR_INFO;
+
+//
+//TYPEDEF_FAN_SENSOR_SECTION - Macro that can be used to typedef the
+//FAN_SENSOR_SECTION structure, which provides information about all fan
+//speed sensors
+//
+#define TYPEDEF_FAN_SENSOR_SECTION(count) \
+typedef struct _FAN_SENSOR_SECTION \
+{ \
+ UINT8 byCount; \
+ FAN_SENSOR_INFO stSensor[count]; \
+ \
+} FAN_SENSOR_SECTION, *P_FAN_SENSOR_SECTION
+
+//
+// FAN_CONTROLLER_INFO - Structure providing info for a fan speed controller
+//
+#define MAX_ASSOC_FANS 4
+#define ASSOC_UNUSED 0xFF
+
+typedef struct _FAN_CONTROLLER_INFO {
+ UINT8 byDevice; // Device index
+ UINT8 byIndex; // Physical Controller Index
+ UINT8 byUsage; // Usage Indicator
+ UINT8 byFan[MAX_ASSOC_FANS]; // Associated Fan Sensors
+} FAN_CONTROLLER_INFO, *P_FAN_CONTROLLER_INFO;
+
+//
+//TYPEDEF_FAN_CONTROLLER_SECTION - Macro that can be used to typedef the
+// FAN_CONTROLLER_SECTION structure, which provides information about all
+//fan speed controllers
+//
+#define TYPEDEF_FAN_CONTROLLER_SECTION(count) \
+typedef struct _FAN_CONTROLLER_SECTION \
+{ \
+ UINT8 byCount; \
+ FAN_CONTROLLER_INFO stController[count]; \
+ \
+} FAN_CONTROLLER_SECTION, *P_FAN_CONTROLLER_SECTION
+
+//
+// SENSOR_INFO_VAR structure, which provides information about all sensors
+// and fan speed controllers. The other TYPEDEF macros must be invoked
+// before using this one
+//
+
+#define TYPEDEF_SENSOR_INFO_VAR \
+typedef struct _SENSOR_INFO_VAR \
+{ \
+ TEMP_SENSOR_SECTION stTemps; \
+ VOLT_SENSOR_SECTION stVolts; \
+ FAN_SENSOR_SECTION stFans; \
+ FAN_CONTROLLER_SECTION stCtrls; \
+ \
+} SENSOR_INFO_VAR, *P_SENSOR_INFO_VAR
+
+#pragma pack()
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h new file mode 100644 index 0000000000..fe95ee7c9c --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/SetupVariable.h @@ -0,0 +1,1142 @@ +/** @file
+ Header file for Setup Variable.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SETUP_VARIABLE_H
+#define _SETUP_VARIABLE_H
+
+#include <ScLimits.h>
+
+//
+// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9}
+//
+#define SYSTEM_CONFIGURATION_GUID { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 }
+
+#define ROOT_SECURITY_GUID { 0xd387d688, 0xeba4, 0x45b5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0x37 }
+
+//
+// {6936B3BD-4350-46d9-8940-1FA20961AEB1}
+//
+#define SYSTEM_ROOT_MAIN_GUID { 0x6936b3bd, 0x4350, 0x46d9, 0x89, 0x40, 0x1f, 0xa2, 0x9, 0x61, 0xae, 0xb1 }
+
+//
+// {21FEE8DB-0D29-477e-B5A9-96EB343BA99C}
+//
+#define ADDITIONAL_SYSTEM_INFO_GUID { 0x21fee8db, 0xd29, 0x477e, 0xb5, 0xa9, 0x96, 0xeb, 0x34, 0x3b, 0xa9, 0x9c }
+
+//
+// {EC87D643-EBA4-4BB5-A1E5-3F3E36B20DA9}
+//
+#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }
+
+//
+// {1B838190-4625-4ead-ABC9-CD5E6AF18FE0}
+//
+#define EFI_HII_EXPORT_DATABASE_GUID { 0x1b838190, 0x4625, 0x4ead, 0xab, 0xc9, 0xcd, 0x5e, 0x6a, 0xf1, 0x8f, 0xe0 }
+
+#define PASSWORD_MAX_SIZE 20
+#define MAX_CUSTOM_VID_TABLE_STATES 6
+#define OVERCLOCK_SOURCE_BIOS 0
+#define OVERCLOCK_SOURCE_OS 1
+#define PCIE_MAX_ROOT_PORT 6
+#define LPSS_I2C_DEVICE_NUM 8
+#define LPSS_HSUART_DEVICE_NUM 4
+#define LPSS_SPI_DEVICE_NUM 3
+#define HDAUDIO_FEATURES 10
+#define HDAUDIO_PP_MODULES 32
+#define GUID_CHARS_NUMBER 37 // 36 GUID chars + null termination
+
+#define TPM2_SUPPORTED_BANK_NULL 0
+#define TPM2_SUPPORTED_BANK_SHA1 1
+#define TPM2_SUPPORTED_BANK_SHA2 2
+#define TPM2_SUPPORTED_BANK_BOTH 3
+
+#define PS2_CONSOLE 0x00
+#define RECONNECT_LAST_GOOD_INPUT_CONSOLE 0x01
+#define WINDOWS_CONSOLE 0x02
+
+//
+// #defines for Drive Presence
+//
+#define EFI_HDD_PRESENT 0x01
+#define EFI_HDD_NOT_PRESENT 0x00
+#define EFI_CD_PRESENT 0x02
+#define EFI_CD_NOT_PRESENT 0x00
+
+#define EFI_HDD_WARNING_ON 0x01
+#define EFI_CD_WARNING_ON 0x02
+#define EFI_SMART_WARNING_ON 0x04
+#define EFI_HDD_WARNING_OFF 0x00
+#define EFI_CD_WARNING_OFF 0x00
+#define EFI_SMART_WARNING_OFF 0x00
+#define OFFSET_0 0x00
+
+#ifndef VFRCOMPILE
+ extern EFI_GUID gEfiSetupVariableGuid;
+#endif
+
+#ifndef PLATFORM_SETUP_VARIABLE_NAME
+ #define PLATFORM_SETUP_VARIABLE_NAME L"Setup"
+#endif
+#define SETUP_DATA SYSTEM_CONFIGURATION
+
+
+#pragma pack(push,1)
+
+typedef struct {
+
+ //
+ // Floppy
+ //
+ UINT8 Floppy;
+ UINT8 FloppyWriteProtect;
+
+ //
+ // System ports
+ //
+ UINT8 UsbLegacy;
+
+ //
+ // Keyboard
+ //
+ UINT8 Numlock;
+
+ //
+ // Power State
+ //
+ UINT8 PowerState;
+ UINT8 PciDelayOptimizationEcr;
+
+ //
+ // Wake on RTC variables
+ //
+ UINT8 WakeOnRtcS5;
+ UINT8 RTCWakeupDate;
+ UINT8 RTCWakeupTimeHour;
+ UINT8 RTCWakeupTimeMinute;
+ UINT8 RTCWakeupTimeSecond;
+
+ //
+ // Wake On Lan
+ //
+ UINT8 WakeOnLanS5;
+
+ //
+ // Boot Order
+ //
+ UINT8 BootOrder[8];
+
+ //
+ // Hard Drive Boot Order
+ //
+ UINT8 HardDriveBootOrder[8];
+
+ //
+ // CD Drive Boot Order
+ //
+ UINT8 CdDriveBootOrder[4];
+
+ //
+ // FDD Drive Boot Order
+ //
+ UINT8 FddDriveBootOrder[4];
+
+ //
+ // Drive Boot Order
+ //
+ UINT8 DriveBootOrder[16];
+
+ //
+ // Boot Menu Type
+ //
+ UINT8 BootMenuType;
+
+ //
+ // Boot from Network
+ //
+ UINT8 BootNetwork;
+
+ //
+ // Boot USB
+ //
+ UINT8 BootUsb;
+
+ //
+ // Dummy place holder to prevent VFR compiler problem.
+ //
+ UINT16 DummyDataForVfrBug; // Don't change or use.
+
+ //
+ // Fixed Disk Boot Sector (Fdbs)
+ //
+ UINT8 Fdbs;
+
+ //
+ // Event Logging
+ //
+ UINT8 EventLogging;
+
+ //
+ // Video Adaptor
+ //
+ UINT8 PrimaryVideoAdaptor;
+
+ //
+ // Hybrid Graphics
+ //
+ UINT8 HgCardSelect;
+ UINT16 DelayAfterPwrEn;
+ UINT16 DelayAfterHoldReset;
+
+ //
+ // Maximum FSB Automatic/Disable
+ //
+ UINT8 MaxFsb;
+
+ //
+ // Hard Disk Pre-delay
+ //
+ UINT8 HddPredelay;
+
+ //
+ // S.M.A.R.T. Mode
+ //
+ UINT8 SmartMode;
+
+ //
+ // ACPI Suspend State
+ //
+ UINT8 AcpiSuspendState;
+
+ //
+ // PCI Latency Timer
+ //
+ UINT8 PciLatency;
+
+ //
+ // Processor (CPU)
+ //
+
+ //
+ // EIST or GV3 setup option
+ //
+ UINT8 ProcessorEistEnable;
+
+ //
+ // C1E Enable
+ //
+ UINT8 ProcessorC1eEnable;
+
+ //
+ // Enabling CPU C-States of processor
+ //
+ UINT8 ProcessorCcxEnable;
+
+ //
+ // Package C-State Limit
+ //
+ UINT8 PackageCState;
+
+ //
+ // Enable/Disable NHM C3(ACPI C2) report to OS
+ //
+ UINT8 OSC2Report;
+
+ //
+ // Enable/Disable NHM C6(ACPI C3) report to OS
+ //
+ UINT8 C6Enable;
+
+ //
+ // Enable/Disable NHM C7(ACPI C3) report to OS
+ //
+ UINT8 C7Enable;
+
+ //
+ // EIST/PSD Function select option
+ //
+ UINT8 ProcessorEistPsdFunc;
+
+ //
+ // CPU Active Cores and SMT
+ //
+ UINT8 ActiveProcessorCores;
+ //
+ // Core0 is always Enable.
+ //
+ UINT8 Core0;
+ //
+ // Enable/Disable Individual core1
+ //
+ UINT8 Core1;
+ //
+ // Enable/Disable Individual core2
+ //
+ UINT8 Core2;
+ //
+ // Enable/Disable Individual core3
+ //
+ UINT8 Core3;
+ //
+ // Hyper Threading
+ //
+ UINT8 ProcessorHyperThreadingDisable;
+
+ //
+ // Enabling VMX
+ //
+ UINT8 ProcessorVmxEnable;
+
+ //
+ // Enabling VTD
+ //
+ UINT8 VTdEnable;
+
+ //
+ // Enabling BIST
+ //
+ UINT8 ProcessorBistEnable;
+
+ //
+ // Disabling XTPR
+ //
+ UINT8 ProcessorxTPRDisable;
+
+ //
+ // Enabling XE
+ //
+ UINT8 ProcessorXEEnable;
+
+ //
+ // Fast String
+ //
+ UINT8 FastStringEnable;
+
+ //
+ // Monitor/Mwait
+ //
+ UINT8 MonitorMwaitEnable;
+
+ //
+ // Machine Check
+ //
+ UINT8 MachineCheckEnable;
+
+ //
+ // Turbo mode
+ //
+ UINT8 TurboModeEnable;
+
+ //
+ // Enable Processor XAPIC
+ //
+ UINT8 ProcessorXapic;
+
+ //
+ // Select BSP
+ //
+ UINT8 BspSelection;
+
+ //
+ // Turbo-XE Mode Processor TDC Limit Override Enable
+ //
+ UINT8 ProcessorTDCLimitOverrideEnable;
+
+ //
+ // Turbo-XE Mode Processor TDC Limit
+ //
+ UINT16 ProcessorTDCLimit;
+
+ //
+ // Turbo-XE Mode Processor TDP Limit Override Enable
+ //
+ UINT8 ProcessorTDPLimitOverrideEnable;
+
+ //
+ // Turbo-XE Mode Processor TDP Limit
+ //
+ UINT16 ProcessorTDPLimit;
+
+ //
+ // Virtual wire A or B
+ //
+ UINT8 ProcessorVirtualWireMode;
+
+ //
+ // FSB Frequency Override in MHz
+ //
+ UINT16 FsbFrequency;
+
+ //
+ // Ecc 0/1 Disable/Enable if supported
+ //
+ UINT8 EccEnable;
+
+ //
+ // Memory
+ //
+ UINT16 ChannelHashMask;
+ UINT16 SliceHashMask;
+ UINT8 InterleavedMode;
+ UINT8 ChannelsSlicesEnabled;
+ UINT8 MinRefRate2xEnabled;
+ UINT8 DualRankSupportEnabled;
+ UINT8 DualRankSupportEnableLockHide;
+
+ //
+ // Port 80 decode 0/1 - PCI/LPC
+ //
+ UINT8 Port80Route;
+
+ //
+ // ECC Event Logging
+ //
+ UINT8 EccEventLogging;
+
+ //
+ // VT-d Option
+ //
+ UINT8 InterruptRemap;
+ UINT8 Isoc;
+ UINT8 ATS;
+
+ //
+ // IGD option
+ //
+ UINT8 GraphicsDriverMemorySize;
+
+ //
+ // IGD Aperture Size question
+ //
+ UINT8 IgdApertureSize;
+
+ //
+ // Boot Display Device
+ //
+ UINT8 BootDisplayDevice;
+
+ //
+ // Integrated Graphics Device
+ //
+ UINT8 Igd;
+
+ //
+ // Flash update sleep delay
+ //
+ UINT8 FlashSleepDelay;
+
+ //
+ // FSC system Variable
+ //
+ UINT8 IgdFlatPanel;
+ UINT8 EnableC10;
+ UINT8 FastBoot;
+ UINT8 EfiNetworkSupport;
+ UINT8 PxeRom;
+
+ UINT8 Knob001;
+ UINT8 EnableGv;
+ UINT8 EnableCx;
+ UINT8 EnableCxe;
+ UINT8 EnableTm;
+ UINT8 EnableProcHot;
+ UINT8 BootPState;
+ UINT8 FlexRatio;
+ UINT8 FlexVid;
+ UINT8 QuietBoot;
+
+ //
+ // Thermal Policy Values
+ //
+ UINT8 AutoThermalReporting;
+ UINT8 EnableDigitalThermalSensor;
+ UINT8 PassiveThermalTripPoint;
+ UINT8 PassiveTc1Value;
+ UINT8 PassiveTc2Value;
+ UINT8 PassiveTspValue;
+ UINT8 CriticalThermalTripPoint;
+ UINT8 ActiveTripPoint;
+ UINT8 DeepStandby;
+ UINT8 AlsEnable;
+ UINT8 IgdLcdIBia;
+ UINT8 LogBootTime;
+
+ //
+ // EM-1 related
+ //
+ UINT16 IaAppsRun;
+ UINT8 IaAppsCap;
+ UINT8 CapOrVoltFlag;
+ UINT8 BootOnInvalidBatt;
+ UINT8 ScramblerSupport;
+ UINT8 SecureBoot;
+ UINT8 SecureBootCustomMode;
+ UINT8 MaxPkgCState;
+ UINT8 PanelScaling;
+ UINT8 IgdLcdIGmchBlc;
+ UINT8 SecEnable;
+ UINT8 TPM;
+ UINT8 TPMSupportedBanks;
+ UINT8 TpmDetection;
+ UINT8 PttSuppressCommandSend; // For PTT Debug
+ UINT8 SecFlashUpdate;
+ UINT8 SecFirmwareUpdate;
+ //
+ //Image Processing Unit PCI Device Configuration
+ //
+ UINT8 IpuEn;
+ UINT8 IpuAcpiMode;
+ //
+ // Passwords
+ //
+ UINT8 Recovery;
+ UINT8 Suspend;
+
+ //
+ // South Cluster Area - START
+ //
+ //
+ // Security options
+ //
+ UINT8 ScBiosLock;
+ //
+ // Miscellaneous options
+ //
+ UINT8 Hpet;
+ UINT8 Cg8254;
+ UINT8 EnableClockSpreadSpec;
+ UINT8 StateAfterG3;
+ UINT8 UartInterface;
+ UINT8 Wol;
+
+ //
+ // SCC Configuration
+ //
+ UINT8 SccSdcardEnabled;
+ UINT8 ScceMMCEnabled;
+ UINT8 ScceMMCHostMaxSpeed;
+ UINT8 SccSdioEnabled;
+ UINT8 GPPLock;
+ UINT8 GppLockOptionHide;
+ //
+ // LPSS Configuration
+ //
+ UINT8 LpssI2C0Enabled;
+ UINT8 LpssI2C1Enabled;
+ UINT8 LpssI2C2Enabled;
+ UINT8 LpssI2C3Enabled;
+ UINT8 LpssI2C4Enabled;
+ UINT8 LpssI2C5Enabled;
+ UINT8 LpssI2C6Enabled;
+ UINT8 LpssI2C7Enabled;
+
+ UINT8 LpssHsuart0Enabled;
+ UINT8 LpssHsuart1Enabled;
+ UINT8 LpssHsuart2Enabled;
+ UINT8 LpssHsuart3Enabled;
+
+ UINT8 LpssSpi0Enabled;
+ UINT8 LpssSpi1Enabled;
+ UINT8 LpssSpi2Enabled;
+
+ UINT8 LpssNFCSelect;
+
+ UINT8 LpssI2cClkGateCfg[LPSS_I2C_DEVICE_NUM];
+ UINT8 LpssHsuartClkGateCfg[LPSS_HSUART_DEVICE_NUM];
+ UINT8 LpssSpiClkGateCfg[LPSS_SPI_DEVICE_NUM];
+ UINT8 S0ixEnable;
+
+ //
+ // Usb Config
+ //
+ UINT8 UsbXhciSupport;
+ UINT8 ScUsb30Mode;
+ UINT8 ScUsb30Streams;
+ UINT8 ScUsb20;
+ UINT8 ScUsbPortDisable;
+ UINT8 PortUsb20[SC_MAX_USB2_PORTS];
+ UINT8 ScUsbOtg;
+ UINT8 ScUsbVbusOn; //OTG VBUS control
+ UINT8 DisableComplianceMode;
+ UINT8 IddigComp;
+ //
+ //Hsic and SSic Config
+ //
+ UINT8 Hsic1Support;
+ UINT8 Ssic1Support;
+ UINT8 Ssic2Support;
+ UINT8 Ssic1Rate;
+ UINT8 Ssic2Rate;
+ UINT8 SsicDlanePg;
+ //
+ // Lan Config
+ //
+ UINT8 Lan;
+ UINT8 SlpLanLowDc;
+
+ //
+ // HD-Audio Config
+ //
+ UINT8 ScHdAudio;
+ UINT8 ScHdAudioDsp;
+ UINT8 ScHdAudioCtlPwrGate; // Deprecated option
+ UINT8 ScHdAudioDspPwrGate; // Deprecated option
+ UINT8 ScHdAudioMmt;
+ UINT8 ScHdAudioHmt;
+ UINT8 ScHdAudioIoBufferOwnership;
+ UINT8 ScHdAudioBiosCfgLockDown;
+ UINT8 ScHdAudioPwrGate;
+ UINT8 ScHdAudioClkGate;
+ UINT8 ScHdAudioPme;
+ UINT8 ScHdAudioFeature[HDAUDIO_FEATURES];
+ UINT8 ScHdAudioPostProcessingMod[HDAUDIO_PP_MODULES];
+ CHAR16 ScHdAudioPostProcessingModCustomGuid1[GUID_CHARS_NUMBER];
+ CHAR16 ScHdAudioPostProcessingModCustomGuid2[GUID_CHARS_NUMBER];
+ CHAR16 ScHdAudioPostProcessingModCustomGuid3[GUID_CHARS_NUMBER];
+ UINT8 ScHdAudioNhltEndpointDmic;
+ UINT8 ScHdAudioNhltEndpointBt;
+ UINT8 ScHdAudioNhltEndpointI2sSKP;
+ UINT8 ScHdAudioNhltEndpointI2sHP;
+ UINT8 ScHdAduioRsvd1;
+ UINT8 SvHdaVcType;
+ UINT8 HdAudioLinkFrequency;
+ UINT8 IDispLinkFrequency;
+ UINT8 IDispLinkTmode;
+
+ //
+ // GMM Config
+ //
+ UINT8 Gmm;
+ UINT8 GmmCgPGCBEnabled;
+ UINT8 GmmCgSBDEnabled;
+ UINT8 GmmCgSBTEnabled;
+ UINT8 GmmCgSBPEnabled;
+ UINT8 GmmCgCoreEnabled;
+ UINT8 GmmCgDmaEnabled;
+ UINT8 GmmCgRAEnabled;
+ UINT8 GmmCgHostEnabled;
+ UINT8 GmmCgPEnabled;
+ UINT8 GmmCgTEnabled;
+ UINT8 GmmPgHwAutoEnabled;
+ UINT8 GmmPgD3HotEnabled;
+ UINT8 GmmPgI3Enabled;
+ UINT8 GmmPgPMCREnabled;
+
+ //
+ // ISH Config
+ //
+ UINT8 ScIshEnabled;
+ UINT8 IshI2c0PullUp;
+ UINT8 IshI2c1PullUp;
+
+ //
+ // SATA_CONFIG
+ //
+ UINT8 Sata;
+ UINT8 SataTestMode;
+ UINT8 SataInterfaceMode;
+ UINT8 SataPort[SC_MAX_SATA_PORTS];
+ UINT8 SataHotPlug[SC_MAX_SATA_PORTS];
+ UINT8 SataMechanicalSw[SC_MAX_SATA_PORTS];
+ UINT8 SataSpinUp[SC_MAX_SATA_PORTS];
+ UINT8 SataExternal[SC_MAX_SATA_PORTS];
+ UINT8 SataType[SC_MAX_SATA_PORTS];
+ UINT8 SataSalp;
+ UINT8 PxDevSlp[SC_MAX_SATA_PORTS];
+ UINT8 EnableDitoConfig[SC_MAX_SATA_PORTS];
+ UINT16 DitoVal[SC_MAX_SATA_PORTS];
+ UINT8 DmVal[SC_MAX_SATA_PORTS];
+
+ //
+ // PCI_EXPRESS_CONFIG, 6 ROOT PORTS
+ //
+ UINT8 PcieClockGatingDisabled;
+ UINT8 PcieRootPort8xhDecode;
+ UINT8 Pcie8xhDecodePortIndex;
+ UINT8 PcieRootPortPeerMemoryWriteEnable;
+ UINT8 PcieComplianceMode;
+ UINT8 PcieRootPortEn[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortAspm[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortURE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortFEE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortNFE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortCEE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortCTD[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortPIE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortSFE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortSNE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortSCE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortPMCE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortHPE[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortSpeed[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortTHS[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortL1SubStates[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieRootPortACS[SC_MAX_PCIE_ROOT_PORTS];
+ //
+ // PCIe LTR Configuration
+ //
+ UINT8 PchPcieLtrEnable[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PchPcieLtrConfigLock[SC_MAX_PCIE_ROOT_PORTS];
+ UINT16 PcieLtrMaxSnoopLatency[SC_MAX_PCIE_ROOT_PORTS];
+ UINT16 PcieLtrMaxNoSnoopLatency[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PchPcieSnoopLatencyOverrideMode[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PchPcieSnoopLatencyOverrideMultiplier[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PchPcieNonSnoopLatencyOverrideMode[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[SC_MAX_PCIE_ROOT_PORTS];
+ UINT16 PchPcieSnoopLatencyOverrideValue[SC_MAX_PCIE_ROOT_PORTS];
+ UINT16 PchPcieNonSnoopLatencyOverrideValue[SC_MAX_PCIE_ROOT_PORTS];
+
+ //
+ // PCI Bridge Resources
+ //
+ UINT8 PcieExtraBusRsvd[SC_MAX_PCIE_ROOT_PORTS];
+ UINT16 PcieMemRsvd[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 PcieIoRsvd[SC_MAX_PCIE_ROOT_PORTS];
+
+ //
+ // South Cluster Area - END
+ //
+
+ UINT8 GTTSize;
+ UINT8 PeiGraphicsPeimInit;
+ //
+ // DVMT5.0 Graphic memory setting
+ //
+ UINT8 IgdDvmt50PreAlloc;
+ UINT8 IgdDvmt50TotalAlloc;
+ UINT8 GOPEnable;
+ UINT8 GOPBrightnessLevel; //Gop Brightness level
+ UINT8 VbtSelect;
+ //
+ // Gt Config
+ //
+ UINT8 PmSupport;
+ UINT8 EnableRenderStandby;
+ UINT8 PavpEnable;
+ UINT8 CdClock;
+
+ UINT8 SeCOpEnable;
+ UINT8 SeCModeEnable;
+ UINT8 SeCEOPEnable;
+ UINT8 SeCEOPDone;
+ UINT8 SeCLockDir;
+
+ //
+ // DPTF
+ //
+ UINT8 EnableDptf; // Option to enable/disable DPTF
+ UINT16 EnableDCFG; // Option to enable/disable DPTF Configuration
+ UINT8 DptfProcessor; // Enable processor participant
+ UINT16 DptfProcCriticalTemperature; // Processor critical temperature
+ UINT16 DptfProcPassiveTemperature; // Processor passive temperature
+ UINT16 DptfProcActiveTemperature; // Processor active temperature
+ UINT16 DptfProcCriticalTemperatureS3; // Processor warm temperature
+ UINT16 DptfProcHotThermalTripPoint; // Processor hot temperature
+ UINT16 GenericCriticalTemp0; // Critical temperature value for generic sensor0 participant
+ UINT16 GenericPassiveTemp0; // Passive temperature value for generic sensor0 participant
+ UINT16 GenericCriticalTemp1; // Critical temperature value for generic sensor1 participant
+ UINT16 GenericPassiveTemp1; // Passive temperature value for generic sensor1 participant
+ UINT16 GenericCriticalTemp2; // Critical temperature value for generic sensor2 participant
+ UINT16 GenericPassiveTemp2; // Passive temperature value for generic sensor2 participant
+ UINT16 GenericCriticalTemp3; // Critical temperature value for generic sensor3 participant
+ UINT16 GenericPassiveTemp3; // Passive temperature value for generic sensor3 participant
+ UINT16 GenericCriticalTemp4; // Critical temperature value for generic sensor3 participant
+ UINT16 GenericPassiveTemp4; // Passive temperature value for generic sensor3 participant
+ UINT8 ThermalSamplingPeriodTCPU; //
+ UINT8 Clpm; // Current low power mode
+ UINT32 LPOEnable; // DPTF: Instructs the policy to use Active Cores if they are available. If this option is set to 0, then policy does not use any active core controls ?even if they are available
+ UINT32 LPOStartPState; // DPTF: Instructs the policy when to initiate Active Core control if enabled. Returns P state index.
+ UINT32 LPOStepSize; // DPTF: Instructs the policy to take away logical processors in the specified percentage steps
+ UINT32 LPOPowerControlSetting; // DPTF: Instructs the policy whether to use Core offliing or SMT offlining if Active core control is enabled to be used in P0 or when power control is applied. 1 ?SMT Off lining 2- Core Off lining
+ UINT32 LPOPerformanceControlSetting; // DPTF: Instructs the policy whether to use Core offliing or SMT offlining if Active core control is enabled to be used in P1 or when performance control is applied.1 ?SMT Off lining 2- Core Off lining
+ UINT8 EnableDppm; // DPTF: Controls DPPM Policies (enabled/disabled)
+
+ UINT8 EnableSen0Participant;
+ UINT8 PassiveThermalTripPointSen0;
+ UINT8 CriticalThermalTripPointSen0;
+ UINT8 CriticalThermalTripPointSen0S3;
+ UINT8 HotThermalTripPointSen0;
+
+ UINT8 EnableSen3Participant;
+ UINT8 PassiveThermalTripPointSen3;
+ UINT8 CriticalThermalTripPointSen3;
+ UINT8 CriticalThermalTripPointSen3S3;
+ UINT8 HotThermalTripPointSen3;
+
+ UINT8 DptfChargerDevice;
+ UINT8 DptfDisplayDevice;
+ UINT8 DisplayHighLimit;
+ UINT8 DisplayLowLimit;
+ UINT8 EnablePowerParticipant;
+ UINT16 PowerParticipantPollingRate;
+ UINT8 DptfFanDevice;
+ UINT8 DptfWwanDevice;
+ UINT8 PassiveThermalTripPointWWAN;
+ UINT8 CriticalThermalTripPointWWANS3;
+ UINT8 HotThermalTripPointWWAN;
+ UINT8 CriticalThermalTripPointWWAN;
+ UINT8 HighPerfMode;
+ UINT8 PmicEnable;
+ UINT8 APEIBERT;
+ UINT8 ACPIMemDbg;
+ UINT8 BatteryChargingSolution; //0-non ULPMC 1-ULPMC
+ UINT8 EnableActivePolicy;
+ UINT8 EnablePassivePolicy;
+ UINT8 TrtRevision;
+ UINT8 EnableCriticalPolicy;
+ UINT8 EnableAPPolicy;
+ UINT8 EnablePowerBossPolicy;
+ UINT8 EnableVSPolicy;
+
+ UINT8 EnableMemoryDevice;
+ UINT8 ActiveThermalTripPointTMEM;
+ UINT8 PassiveThermalTripPointTMEM;
+ UINT8 CriticalThermalTripPointTMEM;
+ UINT8 ThermalSamplingPeriodTMEM;
+
+ UINT8 EnableSen1Participant;
+ UINT8 ActiveThermalTripPointSen1;
+ UINT8 PassiveThermalTripPointSen1;
+ UINT8 CriticalThermalTripPointSen1;
+ UINT8 CriticalThermalTripPointSen1S3;
+ UINT8 HotThermalTripPointSen1;
+ UINT8 SensorSamplingPeriodSen1;
+
+ UINT8 EnableGen1Participant;
+ UINT8 ActiveThermalTripPointGen1;
+ UINT8 PassiveThermalTripPointGen1;
+ UINT8 CriticalThermalTripPointGen1;
+ UINT8 CriticalThermalTripPointGen1S3;
+ UINT8 HotThermalTripPointGen1;
+ UINT8 ThermistorSamplingPeriodGen1;
+
+ UINT8 EnableGen2Participant;
+ UINT8 ActiveThermalTripPointGen2;
+ UINT8 PassiveThermalTripPointGen2;
+ UINT8 CriticalThermalTripPointGen2;
+ UINT8 CriticalThermalTripPointGen2S3;
+ UINT8 HotThermalTripPointGen2;
+ UINT8 ThermistorSamplingPeriodGen2;
+
+ UINT8 EnableGen3Participant;
+ UINT8 ActiveThermalTripPointGen3;
+ UINT8 PassiveThermalTripPointGen3;
+ UINT8 CriticalThermalTripPointGen3;
+ UINT8 CriticalThermalTripPointGen3S3;
+ UINT8 HotThermalTripPointGen3;
+ UINT8 ThermistorSamplingPeriodGen3;
+
+ UINT8 EnableGen4Participant;
+ UINT8 ActiveThermalTripPointGen4;
+ UINT8 PassiveThermalTripPointGen4;
+ UINT8 CriticalThermalTripPointGen4;
+ UINT8 CriticalThermalTripPointGen4S3;
+ UINT8 HotThermalTripPointGen4;
+ UINT8 ThermistorSamplingPeriodGen4;
+
+ UINT8 OemDesignVariable0;
+ UINT8 OemDesignVariable1;
+ UINT8 OemDesignVariable2;
+ UINT8 OemDesignVariable3;
+ UINT8 OemDesignVariable4;
+ UINT8 OemDesignVariable5;
+
+ UINT8 EnableVS1Participant;
+ UINT8 ActiveThermalTripPointVS1;
+ UINT8 PassiveThermalTripPointVS1;
+ UINT8 CriticalThermalTripPointVS1;
+ UINT8 CriticalThermalTripPointVS1S3;
+ UINT8 HotThermalTripPointVS1;
+
+ UINT8 EnableVS2Participant;
+ UINT8 ActiveThermalTripPointVS2;
+ UINT8 PassiveThermalTripPointVS2;
+ UINT8 CriticalThermalTripPointVS2;
+ UINT8 CriticalThermalTripPointVS2S3;
+ UINT8 HotThermalTripPointVS2;
+
+ UINT8 EnableVS3Participant;
+ UINT8 ActiveThermalTripPointVS3;
+ UINT8 PassiveThermalTripPointVS3;
+ UINT8 CriticalThermalTripPointVS3;
+ UINT8 CriticalThermalTripPointVS3S3;
+ UINT8 HotThermalTripPointVS3;
+
+ UINT8 PnpSettings;
+ UINT8 EhciDebug;
+ UINT8 IrmtConfiguration;
+ UINT8 CRIDSettings;
+ //
+ //Dnx/Fastboot enable for PO
+ //
+ UINT8 OSDnX;
+
+#if _SVBIOS_
+ //
+ // SV-SSA
+ //
+#if _SVSSABIOS_
+ UINT16 MemorySize;
+#endif
+ //
+ // SV-MRC
+ //
+#if _SVMRCBIOS_
+ UINT8 MrcDebugMsgLevel;
+#endif
+
+ //
+ // For FW Debug Menu Options
+ //
+#if _SVSECBIOS_
+ UINT8 EndOfPostEnabled;
+ UINT8 HeciCommunication;
+ UINT8 TdtAssertStolen;
+#endif
+#endif //end _SVBIOS_
+
+ //
+ //OEM1 table
+ //
+ UINT8 CStateAutoDemotion;
+ UINT8 CStateUnDemotion;
+ UINT8 PkgCStateDemotion;
+ UINT8 PkgCStateUnDemotion;
+
+ UINT8 ProcTraceMemSize;
+ UINT8 ProcTraceEnable;
+ UINT8 ProcTraceOutputScheme;
+
+ // TDO
+ UINT8 TDO;
+
+ //
+ // Kernel Debugger (WinDBG)
+ //
+ UINT8 OsDbgEnable;
+
+#ifdef PRAM_SUPPORT
+ UINT8 Pram;
+#endif
+
+ //
+ // GNSS/GPS mode selection
+ //
+ UINT8 GpsModeSel;
+ UINT8 PreOsSelection;
+ //
+ //Trunk clock enable
+ //
+ UINT8 TrunkClockEnable;
+ UINT8 MaxCoreCState;
+ //
+ //Multi-BOM
+ //
+ UINT8 BomSelection;
+ UINT8 PanelSel;
+ UINT8 WorldCameraSel;
+ UINT8 UserCameraSel;
+ UINT8 AudioSel;
+ UINT8 ModemSel; // Modem selection: 0: Disabled, 1: 7260; 2: 7360;
+ UINT8 TouchSel; // Touch selection: 0: Disabled, 1: Atmel mXT1066T2; 2: Atmel mXT1668T2
+ UINT8 WifiSel; // Wi-Fi Device Select 0: SDIO Lightning Peak 1: SDIO Broadcom 2. PCIe Lightning Peak
+
+ UINT8 FirmwareConfiguration;
+ //
+ // ACPI
+ //
+ UINT8 PciExpNative;
+ UINT8 NativeAspmEnable;
+ UINT8 LowPowerS0Idle;
+ UINT8 TenSecondPowerButtonEnable;
+ UINT8 EcLowPowerMode;
+ UINT8 CSNotifyEC;
+ UINT8 CSDebugLightEC;
+ //
+ // RTD3
+ //
+ UINT8 Rtd3Support;
+ UINT8 Rtd3P0dl;
+ UINT8 Rtd3P3dl;
+ UINT8 RTD3UsbPt1;
+ UINT8 RTD3UsbPt2;
+ UINT8 RTD3I2C0SensorHub;
+ UINT16 RTD3AudioDelay;
+ UINT16 RTD3TouchPadDelay;
+ UINT16 RTD3TouchPanelDelay;
+ UINT16 RTD3SensorHub;
+ UINT16 VRStaggeringDelay;
+ UINT16 VRRampUpDelay;
+ UINT8 PstateCapping;
+ UINT8 RTD3ZPODD;
+ UINT8 RTD3Camera;
+ UINT8 RTD3SataPort1;
+ UINT8 RTD3SataPort2;
+ UINT8 RTD3SataPort3;
+ UINT8 Rtd3WaGpio;
+ UINT16 RTD3I2C0ControllerPS0Delay;
+ UINT16 RTD3I2C1ControllerPS0Delay;
+ UINT8 ConsolidatedPR;
+
+ UINT8 DciEn;
+ UINT8 DciAutoDetect;
+ //
+ // Secure NFC
+ //
+ UINT8 NfcSelect;
+ UINT8 SelectBtDevice;
+
+ UINT8 ResetSelect;
+ UINT8 FprrEnable;
+ //
+ // WIGIG enable switch
+ //
+ UINT8 WiGigEnable;
+ UINT16 WiGigSPLCPwrLimit;
+ UINT32 WiGigSPLCTimeWindow;
+ UINT16 RfemSPLCPwrLimit;
+ UINT32 RfemSPLCTimeWindow;
+ //
+ //PSM
+ //
+ UINT8 PsmEnable;
+ UINT8 PsmSPLC0DomainType;
+ UINT16 PsmSPLC0PwrLimit;
+ UINT32 PsmSPLC0TimeWindow;
+ UINT8 PsmSPLC1DomainType;
+ UINT16 PsmSPLC1PwrLimit;
+ UINT32 PsmSPLC1TimeWindow;
+
+ UINT8 PsmDPLC0DomainType;
+ UINT8 PsmDPLC0DomainPerference;
+ UINT8 PsmDPLC0PowerLimitIndex;
+ UINT16 PsmDPLC0PwrLimit;
+ UINT32 PsmDPLC0TimeWindow;
+
+ UINT8 PsmDPLC1DomainType;
+ UINT8 PsmDPLC1DomainPerference;
+ UINT8 PsmDPLC1PowerLimitIndex;
+ UINT16 PsmDPLC1PwrLimit;
+ UINT32 PsmDPLC1TimeWindow;
+
+ UINT8 VirtualKbEnable;
+
+ UINT8 EPIEnable;
+ UINT8 TypeCEnable;
+
+ //
+ //DDR and High Speed Serial IO SSC
+ //
+ UINT8 DDRSSCEnable;
+ UINT8 DDRSSCSelection;
+ UINT8 DDRCLKBending;
+ UINT8 HSSIOSSCEnable;
+ UINT8 HSSIOSSCSelection;
+ //
+ // LPSS devices
+ //
+ UINT8 I2s343A;
+ UINT8 I2s34C1;
+ UINT8 I2cNfc;
+ UINT8 I2cPss;
+ UINT8 UartBt;
+ UINT8 UartGps;
+ UINT8 Spi1SensorDevice;
+
+ UINT32 Uart2KernelDebugBaseAddress;
+
+ //
+ // SMRR for SMM source level debug
+ //
+ UINT8 SMRREnable;
+
+ //
+ // Windows Offline Crash Dump
+ //
+#ifdef CRASHDUMP_SUPPORT
+ UINT8 CrashDump;
+#endif
+
+ //
+ // S3 Setupvairable
+ //
+ UINT64 AcpiVariableSetCompatibility;
+ UINT32 BootPerformanceTablePointer;
+ UINT32 S3PerformanceTablePointer;
+ UINT8 CseBootDevice; // 0 - eMMC, 1- UFS, 2 - SPI
+
+ //
+ // Platform Default
+ //
+ UINT8 BoardId;
+ UINT8 PlatformSettingEn;
+ UINT8 Max2G;
+ UINT8 PmicSetupDefault;
+ UINT8 RTEn; //Real Time
+
+ //
+ // CPU Power Limit
+ //
+ UINT8 PowerLimit1Enable;
+ UINT8 PowerLimit1Clamp;
+ UINT8 PowerLimit1Time;
+ UINT8 PowerLimit1;
+
+ //
+ // IPC1 (PMI) device
+ //
+ UINT8 RtcLock;
+ UINT8 UseProductKey;
+ UINT8 PowerButterDebounceMode;
+ UINT8 PcieRootPortSelectableDeemphasis[SC_MAX_PCIE_ROOT_PORTS];
+ UINT8 ConInBehavior;
+ //
+ // Number Of Processors
+ //
+ UINT8 NumOfProcessors;
+ UINT8 GpioLock;
+
+ UINT8 CameraRotationAngle;
+ UINT8 PortUsb30[SC_MAX_USB3_PORTS];
+
+ //
+ // Touch Panel and Pad setting
+ //
+ UINT8 I2cTouchPanel;
+ UINT8 I2cTouchPad;
+
+ //
+ //I2C Speed
+ //
+ UINT8 I2C0Speed;
+ UINT8 I2C1Speed;
+ UINT8 I2C2Speed;
+ UINT8 I2C3Speed;
+ UINT8 I2C4Speed;
+ UINT8 I2C5Speed;
+ UINT8 I2C6Speed;
+ UINT8 I2C7Speed;
+ UINT8 TcoLock;
+
+ UINT8 EnableSen2Participant;
+ UINT8 PassiveThermalTripPointSen2;
+ UINT8 CriticalThermalTripPointSen2;
+ UINT8 CriticalThermalTripPointSen2S3;
+ UINT8 HotThermalTripPointSen2;
+
+} SYSTEM_CONFIGURATION;
+#pragma pack(pop)
+
+#endif // #ifndef _SETUP_VARIABLE
+
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