diff options
| author | lushifex <shifeix.a.lu@intel.com> | 2017-05-10 14:18:07 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2017-05-11 09:55:05 +0800 |
| commit | 836c825cf64ca43e4a8c1f7a558563a8d46d7471 (patch) | |
| tree | 0fafaff546532d86d8c90e2698d853edaf5d978c /Platform/BroxtonPlatformPkg/Common/PlatformSettings | |
| parent | 75dec49f960b06eb545c2042a9dfb1f4e72329bb (diff) | |
| download | edk2-platforms-836c825cf64ca43e4a8c1f7a558563a8d46d7471.tar.xz | |
Fixed reconnect -r issue.
System will hang up when run reconnect -r with SD Card insert.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: lushifex <shifeix.a.lu@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Common/PlatformSettings')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c index b8645a2771..8c1c621e0b 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c @@ -1,7 +1,7 @@ /** @file
Platform PCI Bus Initialization Driver.
- Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -405,6 +405,8 @@ PciBusEvent ( UINTN Index;
UINT8 mCacheLineSize = 0x10;
UINTN Seg, Bus, Dev, Fun;
+ UINT32 AcpiIoPortBaseAddr;
+ UINT32 CmdValue;
while (TRUE) {
BufferSize = sizeof (EFI_HANDLE);
@@ -448,6 +450,35 @@ PciBusEvent ( //
Status = PciIo->GetLocation (PciIo, &Seg, &Bus, &Dev, &Fun);
if ((Seg ==0) && (Bus == 0) && (Dev == 13) && (Fun == 1)) {
+ //
+ // Set PMC acpi io port address
+ //
+ AcpiIoPortBaseAddr = (UINT32) PcdGet16 (PcdScAcpiIoPortBaseAddress);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0x20,
+ 1,
+ &AcpiIoPortBaseAddr
+ );
+
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_COMMAND_OFFSET,
+ 1,
+ &CmdValue
+ );
+
+ CmdValue |= BIT0;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_COMMAND_OFFSET,
+ 1,
+ &CmdValue
+ );
+
Supports |= BIT0;
}
//
|