Minnowboard3 Next Pre-production.

Add code for Minnowboard3 Next pre-production board.
Build Command: BuildBios /vs13 /MX /A Broxton Release.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david.wei@intel.com>

12 files changed, 52 insertions, 11 deletions

diff --git a/Platform/BroxtonPlatformPkg/Common/Console/LpssUartSerialDxe/LpssUartSerialDxe.inf b/Platform/BroxtonPlatformPkg/Common/Console/LpssUartSerialDxe/LpssUartSerialDxe.inf
index 138cf73104..4509ec1180 100644
--- a/Platform/BroxtonPlatformPkg/Common/Console/LpssUartSerialDxe/LpssUartSerialDxe.inf
+++ b/Platform/BroxtonPlatformPkg/Common/Console/LpssUartSerialDxe/LpssUartSerialDxe.inf
@@ -45,6 +45,7 @@
   IntelFrameworkPkg/IntelFrameworkPkg.dec

   IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec

   BroxtonSiPkg/BroxtonSiPkg.dec

+  BroxtonPlatformPkg/PlatformPkg.dec

 

 [LibraryClasses]

   PcdLib

@@ -78,6 +79,7 @@
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8       ## CONSUMES

   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1         ## CONSUMES

   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1       ## CONSUMES

+  gPlatformModuleTokenSpaceGuid.PcdSerialIoUartNumber      ## CONSUMES

 

 [UserExtensions.TianoCore."ExtraFiles"]

   IsaSerialDxeExtra.uni

diff --git a/Platform/BroxtonPlatformPkg/Common/Console/LpssUartSerialDxe/Serial.c b/Platform/BroxtonPlatformPkg/Common/Console/LpssUartSerialDxe/Serial.c
index fa6a2667e9..c273d78f8c 100644
--- a/Platform/BroxtonPlatformPkg/Common/Console/LpssUartSerialDxe/Serial.c
+++ b/Platform/BroxtonPlatformPkg/Common/Console/LpssUartSerialDxe/Serial.c
@@ -1652,7 +1652,7 @@ IsaSerialWrite (
 

   CharBuffer  = (UINT8 *) Buffer;

 

-  PchSerialIoUartOut (Uart2, CharBuffer, *BufferSize);

+  PchSerialIoUartOut (PcdGet8 (PcdSerialIoUartNumber), CharBuffer, *BufferSize);

 

   gBS->RestoreTPL (Tpl);

 

@@ -1696,7 +1696,7 @@ IsaSerialRead (
 

   Tpl     = gBS->RaiseTPL (TPL_NOTIFY);

 

-  *BufferSize = PchSerialIoUartIn(Uart2, Buffer, *BufferSize, FALSE);

+  *BufferSize = PchSerialIoUartIn(PcdGet8 (PcdSerialIoUartNumber), Buffer, *BufferSize, FALSE);

 

   gBS->RestoreTPL (Tpl);

 

diff --git a/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/BaseFspPlatformInfoLibSample/BaseFspWrapperPlatformLibSample.inf b/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/BaseFspPlatformInfoLibSample/BaseFspWrapperPlatformLibSample.inf
index e9b20a452f..d12dccd975 100644
--- a/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/BaseFspPlatformInfoLibSample/BaseFspWrapperPlatformLibSample.inf
+++ b/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/BaseFspPlatformInfoLibSample/BaseFspWrapperPlatformLibSample.inf
@@ -88,4 +88,5 @@
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspStackSize          ## CONSUMES

   gPlatformModuleTokenSpaceGuid.PcdFlashFvIBBLSize   ## CONSUMES

   gPlatformModuleTokenSpaceGuid.PcdUpdateFspmUpdFunc

+  gPlatformModuleTokenSpaceGuid.PcdSerialIoUartNumber

 

diff --git a/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/BaseFspPlatformInfoLibSample/FspPlatformInfoLibSample.c b/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/BaseFspPlatformInfoLibSample/FspPlatformInfoLibSample.c
index 5eae2165dd..d085f265b3 100644
--- a/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/BaseFspPlatformInfoLibSample/FspPlatformInfoLibSample.c
+++ b/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/BaseFspPlatformInfoLibSample/FspPlatformInfoLibSample.c
@@ -126,7 +126,7 @@ UpdateFspUpdConfigs (
   FspmUpd = (FSPM_UPD *)FspUpdRgnPtr;

   DEBUG ((DEBUG_INFO, "GetFspFspmUpdDataPointer - 0x%x\n", FspmUpd));

 

-  FspmUpd->FspmConfig.SerialDebugPortDevice     = 2;

+  FspmUpd->FspmConfig.SerialDebugPortDevice     = PcdGet8(PcdSerialIoUartNumber);

   FspmUpd->FspmConfig.SerialDebugPortType       = 2;// Skip the serial port init since we already did it

   FspmUpd->FspmConfig.SerialDebugPortStrideSize = 2;

   FspmUpd->FspmConfig.SerialDebugPortAddress    = 0;

diff --git a/Platform/BroxtonPlatformPkg/Common/Include/BoardFunctionsPei.h b/Platform/BroxtonPlatformPkg/Common/Include/BoardFunctionsPei.h
index 366b275e3c..92e10b3bae 100644
--- a/Platform/BroxtonPlatformPkg/Common/Include/BoardFunctionsPei.h
+++ b/Platform/BroxtonPlatformPkg/Common/Include/BoardFunctionsPei.h
@@ -36,6 +36,7 @@
 #include <FspmUpd.h>

 #include <FspsUpd.h>

 #include <SmipGenerated.h>

+#include <ScPreMemPolicyCommon.h>

 

 typedef

 EFI_STATUS

@@ -55,5 +56,11 @@ EFI_STATUS
   IN  UINT8                            BoardId

   );

 

+typedef

+EFI_STATUS

+(EFIAPI *UPDATE_PCIE_CONFIG_FUNC) (

+  IN  SC_PCIE_PREMEM_CONFIG  *PciePreMemConfig

+  );

+

 #endif

 

diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h
index 455c6833ef..b2fbd0bd27 100644
--- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h
+++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h
@@ -165,6 +165,7 @@ typedef enum {
   BOARD_ID_LFH_CRB         = 0x07,     // Leaf Hill

   BOARD_ID_MINNOW          = 0x0F,     // Minnow Board

   BOARD_ID_BENSON          = 0x0C,     // Benson Glacier

+  BOARD_ID_MINNOW_NEXT     = 0x03,     // Minnow Board Next

   BOARD_ID_APL_UNKNOWN     = 0xFF

 } APL_BOARD_ID_LIST;

 

diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h
index b29bd62e8b..0bf9fb6eb7 100644
--- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h
+++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h
@@ -150,6 +150,7 @@ typedef struct {
 typedef enum {

   BOARD_ID_LFH_CRB         = 0x07,     // Leaf Hill

   BOARD_ID_MINNOW          = 0x0F,     // Minnow Board

+  BOARD_ID_MINNOW_NEXT     = 0x03,     // Minnow Board Next

   BOARD_ID_BENSON          = 0x0C,     // Benson Glacier

   BOARD_ID_APL_UNKNOWN     = 0xFF

 } APL_BOARD_ID_LIST;

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.c b/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.c
index 2c63f9878f..7770619f97 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.c
+++ b/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.c
@@ -171,8 +171,11 @@ SerialPortInitialize (
   VOID

   )

 {

-

-  PchSerialIoUartInit (PcdGet8 (PcdSerialIoUartNumber), TRUE, 115200, 3, FALSE);

+  //

+  //PchSerialIoUartInit (PcdGet8 (PcdSerialIoUartNumber), TRUE, 115200, 3, FALSE);

+  //

+  PchSerialIoUartInit (0, TRUE, 115200, 3, FALSE);

+  PchSerialIoUartInit (2, TRUE, 115200, 3, FALSE);

 

   return RETURN_SUCCESS;

 }

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.inf b/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.inf
index 5ea0c46577..d986462276 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.inf
+++ b/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLib.inf
@@ -54,7 +54,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate

   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

   gClientCommonModuleTokenSpaceGuid.PcdStatusCodeFlagsCmosIndex

-  gBxtRefCodePkgTokenSpaceGuid.PcdSerialIoUartNumber

+  gPlatformModuleTokenSpaceGuid.PcdSerialIoUartNumber

 

 [Sources]

   BaseSerialPortLib.c

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLibNoInit.inf b/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLibNoInit.inf
index 6a9cf86b25..38964c4a3d 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLibNoInit.inf
+++ b/Platform/BroxtonPlatformPkg/Common/Library/BaseSerialPortLib/BaseSerialPortLibNoInit.inf
@@ -54,7 +54,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate

   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

   gClientCommonModuleTokenSpaceGuid.PcdStatusCodeFlagsCmosIndex

-  gBxtRefCodePkgTokenSpaceGuid.PcdSerialIoUartNumber

+  gPlatformModuleTokenSpaceGuid.PcdSerialIoUartNumber

 

 [Sources]

   BaseSerialPortLibNoInit.c

diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/BoardGpiosPreMem.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/BoardGpiosPreMem.c
index 7116ba19bd..b95e907b68 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/BoardGpiosPreMem.c
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/BoardGpiosPreMem.c
@@ -71,6 +71,17 @@ BXT_GPIO_PAD_INIT  IshI2cGpio[] =
 };

 

 //

+// Turn on an LED so we know there is life in this board

+//

+BXT_GPIO_PAD_INIT  SignsOfLifeGpio[] =

+{

+  //

+  //                  Group Pin#:  pad_name,    PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,  Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, IOSTerm,     MMIO_Offset,      Community

+  //

+  BXT_GPIO_PAD_CONF(L"GPIO_26",                  M0   ,    GPO   , GPIO_D,  LO    ,   NA       , Wake_Disabled, P_NONE ,   NA    ,    NA,     NA   ,DisPuPd,    GPIO_PADBAR+0x00D0,  NORTH), // MB3N - SATA_LED

+};

+

+//

 // North Peak GPIO settings before memory initialization, as it needs to be enabled before memory init

 //

 BXT_GPIO_PAD_INIT  NorthPeakGpio[] =

@@ -162,8 +173,14 @@ BXT_GPIO_PAD_INIT  UartGpio [] =
   //

   //                   Group Pin#:  pad_name,    PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L, Inverted,GPI_ROUT,IOSstae, IOSTerm,   MMIO_Offset,      Community

   //

-  BXT_GPIO_PAD_CONF(L"GPIO_46 LPSS_UART2_RXD",   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,   NA    ,    NA,      NA  ,     NA, GPIO_PADBAR+0x0170,  NORTH),

-  BXT_GPIO_PAD_CONF(L"GPIO_47 LPSS_UART2_TXD",   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,   NA    ,    NA,      NA  ,     NA, GPIO_PADBAR+0x0178,  NORTH),

+  BXT_GPIO_PAD_CONF(L"GPIO_38 LPSS_UART0_RXD",   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,    NA   ,    NA,     NA   ,     NA, GPIO_PADBAR+0x0130, NORTH),     // SOC_UART1_TXD

+  BXT_GPIO_PAD_CONF(L"GPIO_39 LPSS_UART0_TXD",   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,    NA   ,    NA,     NA   ,     NA, GPIO_PADBAR+0x0138, NORTH),     // SOC_UART1_RXD

+  BXT_GPIO_PAD_CONF(L"GPIO_42 LPSS_UART1_RXD",   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,    NA   ,    NA,     NA   ,     NA, GPIO_PADBAR+0x0150, NORTH),     // SOC_UART1_TXD

+  BXT_GPIO_PAD_CONF(L"GPIO_43 LPSS_UART1_TXD",   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,    NA   ,    NA,     NA   ,     NA, GPIO_PADBAR+0x0158, NORTH),     // SOC_UART1_RXD

+  BXT_GPIO_PAD_CONF(L"GPIO_46 LPSS_UART2_RXD",   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,    NA   ,    NA,     NA   ,     NA, GPIO_PADBAR+0x0170, NORTH),     // SOC_UART2_TXD

+  BXT_GPIO_PAD_CONF(L"GPIO_47 LPSS_UART2_TXD",   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,    NA   ,    NA,     NA   ,     NA, GPIO_PADBAR+0x0178, NORTH),     // SOC_UART2_RXD

+  BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0",    M2   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,    NA   ,    NA,     NA   ,     NA, GPIO_PADBAR+0x0218, NORTHWEST), // SOC_UART3_RXD

+  BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1",    M2   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_H,    NA   ,    NA,     NA   ,     NA, GPIO_PADBAR+0x0220, NORTHWEST), // SOC_UART3_TXD

 };

 

 

@@ -214,16 +231,16 @@ MultiPlatformGpioProgramPreMem (
   )

 {

   // PAD programming

+  GpioPadConfigTable (sizeof (SignsOfLifeGpio) / sizeof (SignsOfLifeGpio[0]), SignsOfLifeGpio);

   GpioPadConfigTable (sizeof (IshI2cGpio) / sizeof (IshI2cGpio[0]), IshI2cGpio);

   GpioPadConfigTable (sizeof (NorthPeakGpio) / sizeof (NorthPeakGpio[0]), NorthPeakGpio);

   GpioPadConfigTable (sizeof (LpssSpi1Gpio) / sizeof (LpssSpi1Gpio[0]), LpssSpi1Gpio);

 

   GpioPadConfigTable (sizeof (PcieGpio) / sizeof (PcieGpio[0]), PcieGpio);

   *StartTimerTick = GetPerformanceCounter ();

-  GpioPadConfigTable (sizeof (SataGpio) / sizeof (SataGpio[0]), SataGpio);

   GpioPadConfigTable (sizeof (LpcGpio) / sizeof (LpcGpio[0]), LpcGpio);

   GpioPadConfigTable (sizeof (SmbusGpio) / sizeof (SmbusGpio[0]), SmbusGpio);

-  GpioPadConfigTable (sizeof (UartGpio) / sizeof (UartGpio[0]), UartGpio);

+  GpioPadConfigTable (sizeof (UartGpio)/sizeof (UartGpio[0]), UartGpio);

 

   return EFI_SUCCESS;

 }

diff --git a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
index 42375ce87f..134807ead1 100644
--- a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
+++ b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
@@ -48,6 +48,10 @@ if /i "%~3"=="BG" (
     set BoardId=BG

 )

 

+if /i "%~3"=="MX" (

+    set BoardId=MX

+)

+

 :OptLoop1

 

 if /i "%~1"=="/FspW" (

@@ -154,6 +158,11 @@ if %BoardId%==BG (
            copy /y /b ..\..\Binaries\IFWI\MinnowBoard3\FAB_A\SpiChunk3.bin .

            copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COMPONENTS\IBB.Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvStorage.Fv+SpiChunk3.bin spi_out.bin

          )

+) else if %BoardId%==MX (

+           copy /y /b ..\..\Binaries\IFWI\MinnowBoard3Next\FAB_A\SpiChunk1.bin .

+           copy /y /b ..\..\Binaries\IFWI\MinnowBoard3Next\FAB_A\SpiChunk2.bin .

+           copy /y /b ..\..\Binaries\IFWI\MinnowBoard3Next\FAB_A\SpiChunk3.bin .

+           copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COMPONENTS\IBB.Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvStorage.Fv+SpiChunk3.bin spi_out.bin

 )

 move /y spi_out.bin %BIOS_ID%.bin  >> Stitching.log