diff options
| author | zwei4 <david.wei@intel.com> | 2017-05-09 17:33:16 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2017-05-09 17:33:16 +0800 |
| commit | 3a6119e1bed47febdfafc465136f59659c42d385 (patch) | |
| tree | 3278e69758fef2a55d835783c271a280e07c7878 /Platform/BroxtonPlatformPkg | |
| parent | 757fe5efee58d72b8312bc1e6cc4aaa2ded53395 (diff) | |
| download | edk2-platforms-3a6119e1bed47febdfafc465136f59659c42d385.tar.xz | |
Extend IBB region.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/BuildBios.bat | 4 | ||||
| -rw-r--r-- | Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc | 2 | ||||
| -rw-r--r-- | Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/Platform/BroxtonPlatformPkg/BuildBios.bat b/Platform/BroxtonPlatformPkg/BuildBios.bat index b57188d349..80de2f47b5 100644 --- a/Platform/BroxtonPlatformPkg/BuildBios.bat +++ b/Platform/BroxtonPlatformPkg/BuildBios.bat @@ -410,9 +410,9 @@ copy /y/b %BUILD_PATH%\FV\FvOBBY.fv %Storage_Folder% >nul if /i "%FSP_WRAPPER%" == "TRUE" (
if %Stepping%==B (
-:: 0xFEF63000 = gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase = $(CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EMP_DATA_SIZE) + $(BLD_IBBM_SIZE)
+:: 0xFEF7A000 = gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase = $(CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EMP_DATA_SIZE) + $(BLD_IBBM_SIZE)
pushd %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin
- python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f ApolloLakeFsp.fd -c m -b 0xFEF63000 -o .\ -n FSP.fd
+ python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f ApolloLakeFsp.fd -c m -b 0xFEF7A000 -o .\ -n FSP.fd
python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py split -f FSP.fd -o .\ -n FSP.Fv
popd
copy /y/b %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_T.Fv %Storage_Folder%\FSP_T.Fv
diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc index ff751c164f..842acf3085 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc @@ -153,7 +153,7 @@ DEFINE FSP_IBBL_SIZE = 0x2000
DEFINE BLD_IBBL_SIZE = 0x6000
DEFINE FSP_IBBM_SIZE = 0x58000
- DEFINE BLD_IBBM_SIZE = 0x1E000
+ DEFINE BLD_IBBM_SIZE = 0x35000
DEFINE CAR_BASE_ADDRESS = 0xFEF00000 # @PcdTemporaryRamBase
DEFINE BLD_RAM_DATA_SIZE = 0x16000 # BOOTLOADER temp memory size
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf index 3b4d9e7801..7522153a3e 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf @@ -19,10 +19,10 @@ #==========================================================================================
# 3MB BIOS Layout Definition
#==========================================================================================
- DEFINE FLASH_BASE = 0xFFD00000 #The base address of the 3MB FLASH Device.
- DEFINE FLASH_SIZE = 0x00300000 #The flash size in bytes of the 3MB FLASH Device
+ DEFINE FLASH_BASE = 0xFFCE9000 #The base address of the 3MB FLASH Device.
+ DEFINE FLASH_SIZE = 0x00317000 #The flash size in bytes of the 3MB FLASH Device
DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 3MB FLASH Device.
- DEFINE FLASH_NUM_BLOCKS = 0x300 #The number of blocks in 3MB FLASH Device.
+ DEFINE FLASH_NUM_BLOCKS = 0x317 #The number of blocks in 3MB FLASH Device.
!else
#==========================================================================================
# 5MB BIOS Layout Definition
|