Platform,Silicon: Import Hisilicon D02,D03,D05 and HiKey

Imported from commit efd798c1eb of https://git.linaro.org/uefi/OpenPlatformPkg.git Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
author: Leif Lindholm <leif.lindholm@linaro.org> 2017-08-03 12:24:30 +0100
committer: Leif Lindholm <leif.lindholm@linaro.org> 2017-08-03 12:24:30 +0100
commit: 600081b52debde8d06585fdaf09fac16d323670f (patch)
tree: fef3287095bb56eba411c0b31c525283978b71fb /Platform/Hisilicon/D02
parent: f4d38e50c0f24eb78eb003a94f583025621c63db (diff)
download: edk2-platforms-600081b52debde8d06585fdaf09fac16d323670f.tar.xz
17 files changed, 2189 insertions, 0 deletions
diff --git a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c
new file mode 100644
index 0000000000..1d011fb686
--- /dev/null
+++ b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c
@@ -0,0 +1,94 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/ArmLib.h>
+
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+
+#include <Library/OemMiscLib.h>
+
+#define TIMER_SUBCTRL_BASE                              PcdGet64(PcdPeriSubctrlAddress)
+#define ALG_BASE                                        (0xA0000000)
+#define PERI_SUB_CTRL_BASE                              (0x80000000)
+#define SC_TM_CLKEN0_REG                                (0x2050)
+#define SYS_APB_IF_BASE                                 (0x10000)
+#define TSENSOR_REG                                     (0x5000)
+#define SC_ITS_M3_INT_MUX_SEL_REG                       (0x21F0)
+#define SC_HLLC_RESET_DREQ_REG                          (0xA8C)
+#define SC_ITS_M3_INT_MUX_SEL_VALUE                     (0xF)
+#define SC_HLLC_RESET_DREQ_VALUE                        (0x1f)
+#define TSENSOR_CONFIG_VALUE                            (0x1)
+
+VOID PlatformTimerStart (VOID)
+{
+    // Timer0 clock enable
+    MmioWrite32 (TIMER_SUBCTRL_BASE + SC_TM_CLKEN0_REG, 0x3);
+}
+
+EFI_STATUS
+EFIAPI
+EarlyConfigEntry (
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+    DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
+    SmmuConfigForOS();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"ITS CONFIG........."));
+    ITSCONFIG();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"AP CONFIG........."));
+    MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
+    (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
+    ArmDataSynchronizationBarrier ();
+    ArmInstructionSynchronizationBarrier ();
+
+    CoreSelectBoot();
+
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"MN CONFIG........."));
+    MN_CONFIG ();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"RTC CONFIG........."));
+
+    MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_VALUE);
+
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"Tsensor CONFIG........."));
+
+    MmioWrite32(PERI_SUB_CTRL_BASE + SYS_APB_IF_BASE + TSENSOR_REG, TSENSOR_CONFIG_VALUE);
+    MmioWrite32(ALG_BASE + SC_HLLC_RESET_DREQ_REG, SC_HLLC_RESET_DREQ_VALUE);
+
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"Timer CONFIG........."));
+    PlatformTimerStart ();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    return EFI_SUCCESS;
+}
diff --git a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
new file mode 100644
index 0000000000..5506a586ae
--- /dev/null
+++ b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
@@ -0,0 +1,53 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = EarlyConfigPeim
+  FILE_GUID                      = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = EarlyConfigEntry
+
+[Sources.common]
+  EarlyConfigPeim.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PeimEntryPoint
+  PcdLib
+  DebugLib
+  IoLib
+  CacheMaintenanceLib
+  ArmLib
+
+  PlatformSysCtrlLib
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdMailBoxAddress
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
+
+[Depex]
+## As we will clean mailbox in this module, need to wait memory init complete
+  gEfiPeiMemoryDiscoveredPpiGuid
+
+[BuildOptions]
+
diff --git a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c
new file mode 100644
index 0000000000..429306bb03
--- /dev/null
+++ b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c
@@ -0,0 +1,341 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <libfdt.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/FdtUpdateLib.h>
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <Library/MemoryAllocationLib.h>
+
+MAC_ADDRESS gMacAddress[1];
+
+CHAR8  *EthName[8]=
+{
+ "ethernet@0","ethernet@1",
+ "ethernet@2","ethernet@3",
+ "ethernet@4","ethernet@5",
+ "ethernet@6","ethernet@7"
+};
+
+CHAR8  *MacName[4]=
+{
+ "ethernet-mac@c7040000",
+ "ethernet-mac@c7044000",
+ "ethernet-mac@c7048000",
+ "ethernet-mac@c704c000"
+};
+
+STATIC
+BOOLEAN
+IsMemMapRegion (
+  IN EFI_MEMORY_TYPE MemoryType
+  )
+{
+  switch(MemoryType)
+    {
+        case EfiRuntimeServicesCode:
+        case EfiRuntimeServicesData:
+        case EfiConventionalMemory:
+        case EfiACPIReclaimMemory:
+        case EfiACPIMemoryNVS:
+        case EfiLoaderCode:
+        case EfiLoaderData:
+        case EfiBootServicesCode:
+        case EfiBootServicesData:
+        case EfiPalCode:
+                return TRUE;
+        default:
+                return FALSE;
+  }
+}
+
+EFI_STATUS
+GetMacAddress (UINT32 Port)
+{
+    EFI_MAC_ADDRESS Mac;
+    EFI_STATUS Status;
+    HISI_BOARD_NIC_PROTOCOL *OemNic = NULL;
+
+    Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    Status = OemNic->GetMac(&Mac, Port);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] GetMac failed %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    gMacAddress[0].data0=Mac.Addr[0];
+    gMacAddress[0].data1=Mac.Addr[1];
+    gMacAddress[0].data2=Mac.Addr[2];
+    gMacAddress[0].data3=Mac.Addr[3];
+    gMacAddress[0].data4=Mac.Addr[4];
+    gMacAddress[0].data5=Mac.Addr[5];
+    DEBUG((EFI_D_ERROR, "Port%d:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+        Port,gMacAddress[0].data0,gMacAddress[0].data1,gMacAddress[0].data2,
+        gMacAddress[0].data3,gMacAddress[0].data4,gMacAddress[0].data5));
+
+    return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+DelPhyhandleUpdateMacAddress(IN VOID* Fdt)
+{
+    UINT8               port;
+    INTN                ethernetnode;
+    INTN                node;
+    INTN                Error;
+    struct              fdt_property *m_prop;
+    int                 m_oldlen;
+    EFI_STATUS          Status = EFI_SUCCESS;
+
+    node = fdt_subnode_offset(Fdt, 0, "soc");
+    if (node < 0)
+    {
+        DEBUG ((EFI_D_ERROR, "can not find soc root node\n"));
+        return EFI_INVALID_PARAMETER;
+    }
+    else
+    {
+        for( port=0; port<8; port++ )
+        {
+            (VOID) GetMacAddress(port);
+            ethernetnode=fdt_subnode_offset(Fdt, node,EthName[port]);
+            if (ethernetnode < 0)
+            {
+                DEBUG ((EFI_D_ERROR, "can not find ethernet@ %d node\n",port));
+            }
+            m_prop = fdt_get_property_w(Fdt, ethernetnode, "local-mac-address", &m_oldlen);
+            if(m_prop)
+            {
+                Error = fdt_delprop(Fdt, ethernetnode, "local-mac-address");
+                if (Error)
+                {
+                    DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop() Local-mac-address: %a\n", fdt_strerror (Error)));
+                    Status = EFI_INVALID_PARAMETER;
+                }
+                Error = fdt_setprop(Fdt, ethernetnode, "local-mac-address",gMacAddress,sizeof(MAC_ADDRESS));
+                if (Error)
+                {
+                    DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop():local-mac-address %a\n", fdt_strerror (Error)));
+                    Status = EFI_INVALID_PARAMETER;
+                }
+            }
+        }
+    }
+    return Status;
+}
+
+EFI_STATUS UpdateMemoryNode(VOID* Fdt)
+{
+    INTN                Error = 0;
+    EFI_STATUS          Status = EFI_SUCCESS;
+    UINT32              Index = 0;
+    UINT32              MemIndex;
+    INTN                node;
+    struct              fdt_property *m_prop;
+    int                 m_oldlen;
+    EFI_MEMORY_DESCRIPTOR *MemoryMap;
+    EFI_MEMORY_DESCRIPTOR *MemoryMapPtr;
+    EFI_MEMORY_DESCRIPTOR *MemoryMapPtrCurrent;
+    UINTN                 MemoryMapSize;
+    UINTN                 Pages0 = 0;
+    UINTN                 Pages1 = 0;
+    UINTN                 MapKey;
+    UINTN                 DescriptorSize;
+    UINT32                DescriptorVersion;
+    PHY_MEM_REGION        *mRegion;
+    UINTN                 MemoryMapLastEndAddress ;
+    UINTN                 MemoryMapcontinuousStartAddress ;
+    UINTN                 MemoryMapCurrentStartAddress;
+    BOOLEAN               FindMemoryRegionFlag = FALSE;
+    node = fdt_subnode_offset(Fdt, 0, "memory");
+    if (node < 0)
+    {
+        // Create the memory node
+        node = fdt_add_subnode(Fdt, 0, "memory");
+        if(node < 0)
+        {
+          DEBUG((EFI_D_INFO, "[%a]:[%dL] fdt add subnode error\n", __FUNCTION__, __LINE__));
+        }
+    }
+    //find the memory node property
+    m_prop = fdt_get_property_w(Fdt, node, "memory", &m_oldlen);
+    if(m_prop)
+        Error=fdt_delprop(Fdt, node, "reg");
+    if (Error)
+    {
+        DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop(): %a\n", fdt_strerror (Error)));
+        Status = EFI_INVALID_PARAMETER;
+        return Status;
+    }
+
+    MemoryMap = NULL;
+    MemoryMapSize = 0;
+    MemIndex = 0;
+
+    Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+    if (Status == EFI_BUFFER_TOO_SMALL)
+    {
+        // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive
+        // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size.
+        //DEBUG ((EFI_D_ERROR, "MemoryMapsize: 0x%lx\n",MemoryMapSize));
+        Pages0 = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
+        MemoryMap = AllocatePages (Pages0);
+        if (MemoryMap == NULL)
+        {
+            Status = EFI_OUT_OF_RESOURCES;
+            return Status;
+        }
+        Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+    }
+
+    if(MemoryMap == NULL)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        //goto EXIT;
+        return Status;
+    }
+
+    mRegion = NULL;
+    Pages1 = EFI_SIZE_TO_PAGES (sizeof(PHY_MEM_REGION) *( MemoryMapSize / DescriptorSize));
+    mRegion = (PHY_MEM_REGION*)AllocatePages(Pages1);
+    if (mRegion == NULL)
+    {
+      Status = EFI_OUT_OF_RESOURCES;
+      return Status;
+    }
+
+    if (!EFI_ERROR(Status))
+    {
+        MemoryMapPtr = MemoryMap;
+        MemoryMapPtrCurrent = MemoryMapPtr;
+        MemoryMapLastEndAddress = 0;
+        MemoryMapcontinuousStartAddress = 0;
+        MemoryMapCurrentStartAddress = 0;
+        for ( Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++)
+        {
+            MemoryMapPtrCurrent = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + Index*DescriptorSize);
+            MemoryMapCurrentStartAddress = (UINTN)MemoryMapPtrCurrent->PhysicalStart;
+
+            if (!IsMemMapRegion ((EFI_MEMORY_TYPE)MemoryMapPtrCurrent->Type))
+            {
+                continue;
+            }
+            else
+            {
+                FindMemoryRegionFlag = TRUE;
+                if(MemoryMapCurrentStartAddress != MemoryMapLastEndAddress)
+                {
+                    mRegion[MemIndex].BaseHigh= cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32);
+                    mRegion[MemIndex].BaseLow=cpu_to_fdt32(MemoryMapcontinuousStartAddress);
+                    mRegion[MemIndex].LengthHigh= cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32);
+                    mRegion[MemIndex].LengthLow=cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress);
+                    MemIndex+=1;
+                    MemoryMapcontinuousStartAddress=MemoryMapCurrentStartAddress;
+                }
+            }
+            MemoryMapLastEndAddress = (UINTN)(MemoryMapPtrCurrent->PhysicalStart + MemoryMapPtrCurrent->NumberOfPages * EFI_PAGE_SIZE);
+        }
+        if (FindMemoryRegionFlag)
+        {
+            mRegion[MemIndex].BaseHigh = cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32);
+            mRegion[MemIndex].BaseLow = cpu_to_fdt32(MemoryMapcontinuousStartAddress);
+            mRegion[MemIndex].LengthHigh = cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32);
+            mRegion[MemIndex].LengthLow = cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress);
+        }
+    }
+    Error = fdt_setprop(Fdt, node, "reg",mRegion,sizeof(PHY_MEM_REGION) *(MemIndex+1));
+    FreePages (mRegion, Pages1);
+    FreePages (MemoryMap, Pages0);
+    if (Error)
+    {
+        DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop(): %a\n", fdt_strerror (Error)));
+        Status = EFI_INVALID_PARAMETER;
+        return Status;
+    }
+  return Status;
+}
+
+/*
+ * Entry point for fdtupdate lib.
+ */
+
+EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr)
+{
+    INTN                Error;
+    VOID*               Fdt;
+    UINT32              Size;
+    UINTN               NewFdtBlobSize;
+    UINTN               NewFdtBlobBase;
+    EFI_STATUS          Status = EFI_SUCCESS;
+
+    Error = fdt_check_header ((VOID*)(UINTN)(FdtFileAddr));
+    if (Error != 0)
+    {
+        DEBUG ((EFI_D_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error)));
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Size = (UINTN)fdt_totalsize ((VOID*)(UINTN)(FdtFileAddr));
+    NewFdtBlobSize = Size + ADD_FILE_LENGTH;
+    Fdt = (VOID*)(UINTN)FdtFileAddr;
+
+    Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase);
+    if (EFI_ERROR (Status))
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+
+    Error = fdt_open_into(Fdt,(VOID*)(UINTN)(NewFdtBlobBase), (NewFdtBlobSize));
+    if (Error) {
+        DEBUG ((EFI_D_ERROR, "ERROR:fdt_open_into(): %a\n", fdt_strerror (Error)));
+        Status = EFI_INVALID_PARAMETER;
+        goto EXIT;
+    }
+
+    Fdt = (VOID*)(UINTN)NewFdtBlobBase;
+
+    Status = DelPhyhandleUpdateMacAddress(Fdt);
+    if (EFI_ERROR (Status))
+    {
+        DEBUG ((EFI_D_ERROR, "DelPhyhandleUpdateMacAddress fail:\n"));
+        Status = EFI_SUCCESS;
+    }
+
+    Status = UpdateMemoryNode(Fdt);
+    if (EFI_ERROR (Status))
+    {
+        goto EXIT;
+    }
+
+    gBS->CopyMem(((VOID*)(UINTN)(FdtFileAddr)),((VOID*)(UINTN)(NewFdtBlobBase)),NewFdtBlobSize);
+
+EXIT:
+    gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize));
+
+    return Status;
+}
diff --git a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
new file mode 100644
index 0000000000..c952414350
--- /dev/null
+++ b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
@@ -0,0 +1,43 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = FdtUpdateLib
+  FILE_GUID                      = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = FdtUpdateLib
+
+
+[Sources.common]
+  FdtUpdateLib.c
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  FdtLib
+  OemAddressMapLib
+
+[Protocols]
+  gHisiBoardNicProtocolGuid
+
+[Pcd]
+
diff --git a/Platform/Hisilicon/D02/Include/Library/CpldD02.h b/Platform/Hisilicon/D02/Include/Library/CpldD02.h
new file mode 100644
index 0000000000..b899dbb377
--- /dev/null
+++ b/Platform/Hisilicon/D02/Include/Library/CpldD02.h
@@ -0,0 +1,34 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CPLDD02_H__
+#define __CPLDD02_H__
+#define CPLD_LOGIC_VERSION                (0x52)
+#define PRODUCT_VERSION                   (0x53)
+#define CPLD_LOGIC_COMPLIER_YEAR          (0x54)
+#define CPLD_LOGIC_COMPLIER_MONTH         (0x55)
+#define CPLD_LOGIC_COMPLIER_DAY           (0x56)
+#define CPLD_LOGIC_COMPLIER_HOUR          (0x57)
+#define CPLD_LOGIC_COMPLIER_MINUTE        (0x58)
+#define BOARD_ID                          (0x59)
+#define BOM_VERSION                       (0x5A)
+#define CPLD_BIOS_CURRENT_CHANNEL_REG_D02 (0x5B)
+
+#define CPU0_PCIE1_RESET_REG                (0x12)
+#define CPU0_PCIE2_RESET_REG                (0x13)
+#define CPU1_PCIE1_RESET_REG                (0x14)
+#define CPU1_PCIE2_RESET_REG                (0x15)
+
+#endif /* __CPLDD02_H__ */
diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
new file mode 100644
index 0000000000..49942e5151
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
@@ -0,0 +1,105 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <PlatformArch.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Library/CpldIoLib.h>
+#include <Library/CpldD02.h>
+#include <Library/TimerLib.h>
+#include <Library/I2CLib.h>
+#include <Library/HiiLib.h>
+
+I2C_DEVICE gDS3231RtcDevice = {
+    .Socket = 0,
+    .Port = 7,
+    .DeviceType = DEVICE_TYPE_SPD,
+    .SlaveDeviceAddress = 0x68
+};
+
+// Set Tx output polarity. Not inverting data is default. For Phosphor660 D02 Board
+//if((1 == ulMacroId) && ((7 == ulDsNum)||(0 == ulDsNum)))
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
+{
+    {1, 7},
+    {1, 0},
+    {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+// Set Rx data polarity. Not inverting data is default. For Phosphor660 D02 Board
+//if((1 == ulMacroId) && ((0 == ulDsNum) || (1 == ulDsNum)))
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
+{
+    {1, 0},
+    {1, 1},
+    {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_PARAM gSerdesParam = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = EmHilink3GeX4,
+  .Hilink4Mode = EmHilink4XgeX4,
+  .Hilink5Mode = EmHilink5Sas1X4,
+};
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId)
+{
+  if (ParamA == NULL) {
+    DEBUG((DEBUG_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA));
+  return EFI_SUCCESS;
+}
+
+
+VOID OemPcieResetAndOffReset(void)
+  {
+    WriteCpldReg(CPU0_PCIE1_RESET_REG,0x0);
+    WriteCpldReg(CPU0_PCIE2_RESET_REG,0x0);
+    WriteCpldReg(CPU1_PCIE1_RESET_REG,0x0);
+    WriteCpldReg(CPU1_PCIE2_RESET_REG,0x0);
+    MicroSecondDelay(100000);
+    WriteCpldReg(CPU0_PCIE1_RESET_REG,0x55);
+    WriteCpldReg(CPU0_PCIE2_RESET_REG,0x55);
+    WriteCpldReg(CPU1_PCIE1_RESET_REG,0x55);
+    WriteCpldReg(CPU1_PCIE2_RESET_REG,0x55);
+    return;
+  }
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+  {{STRING_TOKEN(STR_D02_DIMM_000), STRING_TOKEN(STR_D02_DIMM_001), 0xFFFF},
+   {STRING_TOKEN(STR_D02_DIMM_010), STRING_TOKEN(STR_D02_DIMM_011), 0xFFFF}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+  )
+{
+    return HiiAddPackages (
+                            &gEfiCallerIdGuid,
+                            NULL,
+                            OemMiscLibD02Strings,
+                            NULL,
+                            NULL
+                            );
+}
diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni
new file mode 100644
index 0000000000..dcd79eb3d5
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni
diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c
new file mode 100644
index 0000000000..df7d158c2d
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c
@@ -0,0 +1,77 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CpldIoLib.h>
+#include <Library/OemMiscLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/SerialPortLib.h>
+
+// Right now we only support 1P
+BOOLEAN OemIsSocketPresent (UINTN Socket)
+{
+  if (0 == Socket)
+  {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+UINTN OemGetSocketNumber (VOID)
+{
+    return 1;
+}
+
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel)
+{
+    return 2;
+}
+
+UINTN OemGetDdrChannel (VOID)
+{
+    return 2;
+}
+
+VOID CoreSelectBoot(VOID)
+{
+    if (!PcdGet64 (PcdTrustedFirmwareEnable))
+    {
+        StartupAp ();
+    }
+
+    return;
+}
+
+BOOLEAN OemIsMpBoot()
+{
+    return FALSE;
+}
+
+VOID OemBiosSwitch(UINT32 Master)
+{
+    return;
+}
+
+UINT32 OemIsWarmBoot(VOID)
+{
+    return 0;
+}
diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf
new file mode 100644
index 0000000000..3b50ddf9bc
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf
@@ -0,0 +1,45 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemMiscLibD02
+  FILE_GUID                      = 1DCE7EC8-3DB6-47cf-A2B5-717FD9AB2570
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemMiscLib
+
+[Sources.common]
+  BoardFeatureD02.c
+  OemMiscLibD02.c
+  BoardFeatureD02Strings.uni
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  Platform/Hisilicon/D02/Pv660D02.dec
+  Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  SerialPortLib
+  CpldIoLib
+
+[BuildOptions]
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c
new file mode 100644
index 0000000000..797163a5fc
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c
@@ -0,0 +1,147 @@
+/** @file
+
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ {// HostBridge 0
+  /* Port 0 */
+  {
+      PCI_HB0RB0_ECAM_BASE,
+      0,  //BusBase
+      63, //BusLimit
+      (PCI_HB0RB0_ECAM_BASE + SIZE_64MB),  //MemBase
+      (PCI_HB0RB0_ECAM_BASE + PCI_HB0RB0_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB0RB0_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+  /* Port 1 */
+  {
+      PCI_HB0RB1_ECAM_BASE,
+      64,  //BusBase
+      127, //BusLimit
+      PCI_HB0RB1_PCIREGION_BASE,
+      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1,
+      PCI_HB0RB1_IO_BASE, //IoBase
+      PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1,  //IoLimit
+      PCI_HB0RB1_CPUMEMREGIONBASE,
+      PCI_HB0RB2_CPUIOREGIONBASE,
+      (PCI_HB0RB1_PCI_BASE),  //RbPciBar
+      PCI_HB0RB1_PCIREGION_BASE,
+      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1
+  },
+  /* Port 2 */
+  {
+      PCI_HB0RB2_ECAM_BASE,
+      128,  //BusBase
+      191, //BusLimit
+      PCI_HB0RB2_PCIREGION_BASE ,
+      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1,
+      PCI_HB0RB2_IO_BASE, //IoBase
+      PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1,  //IoLimit
+      PCI_HB0RB2_CPUMEMREGIONBASE,
+      PCI_HB0RB2_CPUIOREGIONBASE,
+      (PCI_HB0RB2_PCI_BASE),  //RbPciBar
+      PCI_HB0RB2_PCIREGION_BASE ,
+      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB0RB3_ECAM_BASE,
+      192,  //BusBase
+      255, //BusLimit
+      (PCI_HB0RB3_ECAM_BASE),  //MemBase
+      (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB0RB3_PCI_BASE),  //RbPciBar
+      0,
+      0
+  }
+ },
+{// HostBridge 1
+  /* Port 0 */
+  {
+      PCI_HB1RB0_ECAM_BASE,
+      0,  //BusBase
+      0x1, //BusLimit
+      (PCI_HB1RB0_ECAM_BASE),  //MemBase
+      (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB0_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+  /* Port 1 */
+  {
+       PCI_HB1RB1_ECAM_BASE,
+      0x2,  //BusBase
+      0x3, //BusLimit
+      (PCI_HB1RB1_ECAM_BASE),  //MemBase
+      (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB1_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+  /* Port 2 */
+  {
+      PCI_HB1RB2_ECAM_BASE,
+      0x4,  //BusBase
+      0x5, //BusLimit
+      (PCI_HB1RB2_ECAM_BASE),  //MemBase
+      (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB2_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB1RB3_ECAM_BASE,
+      0x6,  //BusBase
+      0x7, //BusLimit
+      (PCI_HB1RB3_ECAM_BASE),  //MemBase
+      (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB3_PCI_BASE),  //RbPciBar
+      0,
+      0
+  }
+ }
+};
+
diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
new file mode 100644
index 0000000000..4d2dbbaf0d
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
@@ -0,0 +1,182 @@
+## @file
+#
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformPciLib
+  FILE_GUID                      = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  PlatformPciLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PciHb0Rb0Base
+  gHisiTokenSpaceGuid.PciHb0Rb1Base
+  gHisiTokenSpaceGuid.PciHb0Rb2Base
+  gHisiTokenSpaceGuid.PciHb0Rb3Base
+  gHisiTokenSpaceGuid.PciHb0Rb4Base
+  gHisiTokenSpaceGuid.PciHb0Rb5Base
+  gHisiTokenSpaceGuid.PciHb0Rb6Base
+  gHisiTokenSpaceGuid.PciHb0Rb7Base
+  gHisiTokenSpaceGuid.PciHb1Rb0Base
+  gHisiTokenSpaceGuid.PciHb1Rb1Base
+  gHisiTokenSpaceGuid.PciHb1Rb2Base
+  gHisiTokenSpaceGuid.PciHb1Rb3Base
+  gHisiTokenSpaceGuid.PciHb1Rb4Base
+  gHisiTokenSpaceGuid.PciHb1Rb5Base
+  gHisiTokenSpaceGuid.PciHb1Rb6Base
+  gHisiTokenSpaceGuid.PciHb1Rb7Base
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h
new file mode 100644
index 0000000000..5f07116426
--- /dev/null
+++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h
@@ -0,0 +1,31 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __OEM_NIC_CONFIG_H__
+#define __OEM_NIC_CONFIG_H__
+
+#define I2C_SLAVEADDR_EEPROM     (0x52)
+
+#define I2C_OFFSET_EEPROM_ETH0   (0xc00)
+#define I2C_OFFSET_EEPROM_ETH1   (I2C_OFFSET_EEPROM_ETH0 + 6)
+#define I2C_OFFSET_EEPROM_ETH2   (I2C_OFFSET_EEPROM_ETH1 + 6)
+#define I2C_OFFSET_EEPROM_ETH3   (I2C_OFFSET_EEPROM_ETH2 + 6)
+#define I2C_OFFSET_EEPROM_ETH4   (I2C_OFFSET_EEPROM_ETH3 + 6)
+#define I2C_OFFSET_EEPROM_ETH5   (I2C_OFFSET_EEPROM_ETH4 + 6)
+#define I2C_OFFSET_EEPROM_ETH6   (I2C_OFFSET_EEPROM_ETH5 + 6)
+#define I2C_OFFSET_EEPROM_ETH7   (I2C_OFFSET_EEPROM_ETH6 + 6)
+
+
+#endif
diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c
new file mode 100644
index 0000000000..d327fa4343
--- /dev/null
+++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c
@@ -0,0 +1,173 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <Library/I2CLib.h>
+#include <OemNicConfig.h>
+
+#define EEPROM_I2C_PORT 7
+
+EFI_STATUS
+EFIAPI OemGetMac (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+EFI_STATUS
+EFIAPI OemSetMac (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+HISI_BOARD_NIC_PROTOCOL mOemNicProtocol = {
+  .GetMac = OemGetMac,
+  .SetMac = OemSetMac,
+};
+
+
+EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr)
+{
+    I2C_DEVICE stI2cDev = {0};
+    EFI_STATUS Status;
+    UINT16     I2cOffset;
+
+    Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * 6);
+
+    stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+    stI2cDev.Port = EEPROM_I2C_PORT;
+    stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+    stI2cDev.Socket = 0;
+    Status = I2CRead(&stI2cDev, I2cOffset, 6, pucAddr);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr)
+{
+    I2C_DEVICE stI2cDev = {0};
+    EFI_STATUS Status;
+    UINT16     I2cOffset;
+
+    Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * 6);
+
+    stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+    stI2cDev.Port = EEPROM_I2C_PORT;
+    stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+    stI2cDev.Socket = 0;
+    Status = I2CWrite(&stI2cDev, I2cOffset, 6, pucAddr);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemGetMac (
+  IN OUT EFI_MAC_ADDRESS *Mac,
+  IN UINTN Port
+  )
+{
+  EFI_STATUS Status;
+
+  if (NULL == Mac)
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //TODO: discard port number, only support one port
+  // Only 6 bytes are used
+  Status = OemGetMacE2prom(Port, Mac->Addr);
+  if ((EFI_ERROR(Status)))
+  {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] Get mac failed!\n", __FUNCTION__, __LINE__));
+      return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemSetMac (
+  IN EFI_MAC_ADDRESS *Mac,
+  IN UINTN Port
+  )
+{
+  EFI_STATUS Status;
+
+  if (NULL == Mac)
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = OemSetMacE2prom(Port, Mac->Addr);
+  if ((EFI_ERROR(Status)))
+  {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] Set mac failed!\n", __FUNCTION__, __LINE__));
+      return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+OemNicConfigEntry (
+  IN EFI_HANDLE           ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+{
+  EFI_STATUS Status;
+
+  Status = gBS->InstallProtocolInterface(
+    &ImageHandle,
+    &gHisiBoardNicProtocolGuid,
+    EFI_NATIVE_INTERFACE,
+    &mOemNicProtocol
+    );
+
+  if(EFI_ERROR(Status))
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status));
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
new file mode 100644
index 0000000000..df5adf17ca
--- /dev/null
+++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemNicConfig
+  FILE_GUID                      = 3A23A929-1F38-4d04-8A01-38AD993EB2CE
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = OemNicConfigEntry
+
+[Sources.common]
+  OemNicConfigD02.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  Silicon/Hisilicon/HisiPkg.dec
+
+[Protocols]
+  gHisiBoardNicProtocolGuid       ##Produce
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  DebugLib
+  IoLib
+  TimerLib
+  I2CLib
+
+[FixedPcd]
+
+[Depex]
+  TRUE
+
+[BuildOptions]
+
diff --git a/Platform/Hisilicon/D02/Pv660D02.dec b/Platform/Hisilicon/D02/Pv660D02.dec
new file mode 100644
index 0000000000..5c34c2e537
--- /dev/null
+++ b/Platform/Hisilicon/D02/Pv660D02.dec
@@ -0,0 +1,44 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#
+# PV660 D02 Package
+#
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = Pv660D02Pkg
+  PACKAGE_GUID                   = 54392E0D-972B-459D-8CBE-DB381E7D1B98
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  Include
+
+[Ppis]
+
+[Protocols]
+
+[Guids]
+
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild]
+
+[PcdsFeatureFlag]
+
+
diff --git a/Platform/Hisilicon/D02/Pv660D02.dsc b/Platform/Hisilicon/D02/Pv660D02.dsc
new file mode 100644
index 0000000000..99d6972c75
--- /dev/null
+++ b/Platform/Hisilicon/D02/Pv660D02.dsc
@@ -0,0 +1,453 @@
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = Pv660D02
+  PLATFORM_GUID                  = E1AB8AC3-3EF1-4c6f-8D9F-ABE3EC67188E
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/Hisilicon/D02/$(PLATFORM_NAME).fdf
+  DEFINE INCLUDE_TFTP_COMMAND=1
+
+!include Silicon/Hisilicon/Hisilicon.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
+
+  ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+  NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+  LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+  I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+  IpmiCmdLib|Silicon/Hisilicon/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
+
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+!ifdef $(FDT_ENABLE)
+  #FDTUpdateLib
+  FdtUpdateLib|Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
+
+  CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+
+  SerdesLib|Silicon/Hisilicon/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf
+
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+  RealTimeClockLib|Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
+  OemMiscLib|Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf
+  OemAddressMapLib|Platform/Hisilicon/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.inf
+  PlatformSysCtrlLib|Silicon/Hisilicon/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when
+## input signal is de-asserted, except for virtual timer interrupt IRQ #27.
+## So we choose to use virtual timer instead of physical one as a workaround.
+## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc.
+[LibraryClasses.AARCH64]
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf
+
+[LibraryClasses.common.SEC]
+  ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
+
+[BuildOptions]
+  GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Pv660/Include
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D02"
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+
+  # Stacks for MPCores in Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
+
+  # Stacks for MPCores in Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
+
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
+
+  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
+
+  ## SP805 Watchdog - Motherboard Watchdog
+  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x801e0000
+
+  ## Serial Terminal
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x80300000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+
+  gHisiTokenSpaceGuid.PcdUartClkInHz|200000000
+
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|10000000
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D02 UEFI 16.08 RC1"
+
+  gHisiTokenSpaceGuid.PcdSystemProductName|L"D02"
+  gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
+  gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D02"
+  gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
+
+  gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
+
+  #
+  # ARM PL390 General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x8D000000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x8D100000
+
+  ## DTB address at spi flash
+  gHisiTokenSpaceGuid.FdtFileAddress|0xA4B00000
+
+  gHisiTokenSpaceGuid.PcdNORFlashBase|0x90000000
+  gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
+
+  #
+  # ARM OS Loader
+  #
+  # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SATA"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"EFI\GRUB2\grubaa64.efi"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
+
+  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+  #
+  # ARM Architectual Timer Frequency
+  #
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+
+  gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x80010000
+  gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
+  gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x98000000
+  gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
+  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
+
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x80000000
+
+  gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x80000000
+
+  ## 1 SCCL + 1 SICL
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x0
+  gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80020000
+  gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x80000000
+  gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  ## SP804 DualTimer
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|304
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x80060000
+  ## TODO: need to confirm the base for Performance and Metronome base for PV660
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x80060000
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x80060000
+
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x6 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x400000000000 # 4T
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0x30000000000
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0x22000000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0x24000000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0x26000000000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PciHb0Rb0Base|0xb0070000
+  gHisiTokenSpaceGuid.PciHb0Rb1Base|0xb0080000
+  gHisiTokenSpaceGuid.PciHb0Rb2Base|0xb0090000
+  gHisiTokenSpaceGuid.PciHb0Rb3Base|0xb00a0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xb0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0x7feffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xc0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x3feffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0x22008000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0x2400c000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0x2200fff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0x2400fff0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  Platform/Hisilicon/D02/MemoryInitPei/MemoryInitPeim.inf
+  ArmPkg/Drivers/CpuPei/CpuPei.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
+  Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+
+  Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
+
+  Platform/Hisilicon/D02/Drivers/SFC/SfcDxeDriver.inf
+
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  }
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+  #
+  #ACPI
+  #
+  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+  Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf
+  Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf
+
+  #Pci Express
+  Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf
+  Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+     <LibraryClasses>
+       NULL|Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
+  }
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
+  #network
+  #
+  Platform/Hisilicon/D02/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf
+
+  MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  Platform/Hisilicon/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # USB Support
+  #
+  Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+  Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+  Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf {
+    <LibraryClasses>
+      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  }
+!endif #$(FDT_ENABLE)
+
+  #
+  # Memory test
+  #
+  MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
+
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+!ifdef $(INCLUDE_DP)
+      NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+!endif #$(INCLUDE_DP)
+!ifdef $(INCLUDE_TFTP_COMMAND)
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platform/Hisilicon/D02/Pv660D02.fdf b/Platform/Hisilicon/D02/Pv660D02.fdf
new file mode 100644
index 0000000000..2d6cdcd9f6
--- /dev/null
+++ b/Platform/Hisilicon/D02/Pv660D02.fdf
@@ -0,0 +1,317 @@
+#
+#  Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[DEFINES]
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.PV660D02]
+BaseAddress   = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+
+Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00010000
+NumBlocks     = 0x30
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FILE = Platform/Hisilicon/D02/Sec/FVMAIN_SEC.Fv
+
+0x00040000|0x00240000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+## Place for Trusted Firmware
+0x00280000|0x00020000
+gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
+FILE = Platform/Hisilicon/D02/bl1.bin
+0x002a0000|0x00020000
+FILE = Platform/Hisilicon/D02/fip.bin
+
+0x002e0000|0x0000e000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x20000
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
+  0xB8, 0xdF, 0x00, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002ee000|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
+  0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002f0000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  INF Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf
+  INF Platform/Hisilicon/D02/Drivers/SFC/SfcDxeDriver.inf
+
+  INF Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
+
+  # PCI Express
+  INF Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf
+  INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  ## Sometimes we need to switch to emulated variable store for debug reason
+  #INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+  # This is simpler than generic serial console and may be used for debug
+  #INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatBinPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+
+  INF Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  INF Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf
+
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+  INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+  INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+  #
+  #ACPI
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  INF RuleOverride=ACPITABLE Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf
+  INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  #Network
+  #
+  INF Platform/Hisilicon/D02/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf
+
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  INF Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
+
+  INF Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf
+
+  #
+  #Sata
+  #
+  INF Platform/Hisilicon/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # USB Support
+  #
+  INF Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # Build Shell from latest source code instead of prebuilt binary
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+  INF Platform/Hisilicon/D02/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+
+  INF Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+!include Silicon/Hisilicon/Hisilicon.fdf.inc
+
author	Leif Lindholm <leif.lindholm@linaro.org>	2017-08-03 12:24:30 +0100
committer	Leif Lindholm <leif.lindholm@linaro.org>	2017-08-03 12:24:30 +0100
commit	600081b52debde8d06585fdaf09fac16d323670f (patch)
tree	fef3287095bb56eba411c0b31c525283978b71fb /Platform/Hisilicon/D02
parent	f4d38e50c0f24eb78eb003a94f583025621c63db (diff)
download	edk2-platforms-600081b52debde8d06585fdaf09fac16d323670f.tar.xz