diff options
| author | Jiewen Yao <jiewen.yao@intel.com> | 2017-06-19 10:54:34 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2017-06-23 11:54:46 +0800 |
| commit | 012d883a848bf7af8b4859394bb32f8b2a45313f (patch) | |
| tree | ea393e3c84e54cac930d1473b42c2bf8c0abe681 /Platform/Intel/KabylakeOpenBoardPkg/Acpi | |
| parent | 646b243c0e3ef49b98071ca2c3fec15299b4d72f (diff) | |
| download | edk2-platforms-012d883a848bf7af8b4859394bb32f8b2a45313f.tar.xz | |
Add KabylakeOpenBoardPkg
reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com>
reviewed-by: Amy Chan <amy.chan@intel.com>
reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Diffstat (limited to 'Platform/Intel/KabylakeOpenBoardPkg/Acpi')
17 files changed, 4524 insertions, 0 deletions
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c new file mode 100644 index 0000000000..3586cc6116 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c @@ -0,0 +1,101 @@ +/** @file
+ Acpi Gnvs Init Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <PchAccess.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/MpService.h>
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] GlobalNvs - Pointer of Global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **GlobalNvs
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GNVS;
+ EFI_MP_SERVICES_PROTOCOL *MpService;
+ UINTN NumberOfCPUs;
+ UINTN NumberOfEnabledCPUs;
+
+ Pages = EFI_SIZE_TO_PAGES (sizeof (EFI_GLOBAL_NVS_AREA));
+ Address = 0xffffffff; // allocate address below 4G.
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //
+ // Locate the MP services protocol
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **) &MpService
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Determine the number of processors
+ //
+ MpService->GetNumberOfProcessors (
+ MpService,
+ &NumberOfCPUs,
+ &NumberOfEnabledCPUs
+ );
+
+ *GlobalNvs = (VOID *) (UINTN) Address;
+ SetMem (*GlobalNvs, sizeof (EFI_GLOBAL_NVS_AREA), 0);
+
+ //
+ // GNVS default value init here...
+ //
+ GNVS = (EFI_GLOBAL_NVS_AREA_PROTOCOL *) &Address;
+
+ GNVS->Area->ThreadCount = (UINT8)NumberOfEnabledCPUs;
+
+ //
+ // Miscellaneous
+ //
+ GNVS->Area->PL1LimitCS = 0;
+ GNVS->Area->PL1LimitCSValue = 4500;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c new file mode 100644 index 0000000000..bb3154757d --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c @@ -0,0 +1,313 @@ +/** @file
+ ACPI Platform Driver
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/AslUpdateLib.h>
+
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/AcpiTable.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] GlobalNvs - Pointer of Global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **GlobalNvs
+ );
+
+VOID
+UpdateDsdt (
+ IN VOID *Table
+ );
+
+//
+// Function implementations
+//
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] Instance Return pointer to the first instance of the protocol.
+ @param[in] Type TRUE if the desired protocol is a FV protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID *gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (!Type) {
+
+ //
+ // Not looking for the FV protocol, so find the first instance of the
+ // protocol. There should not be any errors because our handle buffer
+ // should always contain at least one or LocateHandleBuffer would have
+ // returned not found.
+ //
+ break;
+ }
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ gEfiAcpiMultiTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID *gEfiAcpiMultiTableStorageGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ EFI_ACPI_TABLE_VERSION Version;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ //
+ // Find the AcpiSupport protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &AcpiTable,
+ FALSE
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &FwVol,
+ TRUE
+ );
+
+ //
+ // Read tables from the storage file.
+ //
+
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ gEfiAcpiMultiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Perform any table specific updates.
+ //
+ if (CurrentTable->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
+ UpdateDsdt (CurrentTable);
+ }
+ BoardUpdateAcpiTable (CurrentTable, &Version);
+
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+ }
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiBoard (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ AcpiGnvsInit((VOID **) &mGlobalNvsArea.Area);
+
+ //
+ // This PCD set must be done before PublishAcpiTablesFromFv.
+ // The PCD data will be used there.
+ //
+ PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mGlobalNvsArea.Area);
+
+ //
+ // Platform ACPI Tables
+ //
+ PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
+
+ //
+ // This protocol publish must be done after PublishAcpiTablesFromFv.
+ // The NVS data is be updated there.
+ //
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiGlobalNvsAreaProtocolGuid,
+ &mGlobalNvsArea,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf new file mode 100644 index 0000000000..e37afb0b90 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf @@ -0,0 +1,75 @@ +### @file
+# Component information file for AcpiPlatform module
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BoardAcpiDxe
+ FILE_GUID = E269E77D-6163-4F5D-8E59-21EAF114D307
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallAcpiBoard
+
+[Sources.common]
+ BoardAcpiDxe.c
+ AcpiGnvsInit.c
+ UpdateDsdt.c
+ Dsdt/DSDT.ASL
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ PcAtChipsetPkg/PcAtChipsetPkg.dec
+ KabylakeOpenBoardPkg/OpenBoardPkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ HobLib
+ AslUpdateLib
+ BoardAcpiTableLib
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gEfiMpServiceProtocolGuid ## CONSUMES
+ gEfiGlobalNvsAreaProtocolGuid
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
+
+ gBoardModuleTokenSpaceGuid.PcdAcpiSleepState
+ gBoardModuleTokenSpaceGuid.PcdAcpiHibernate
+ gPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle
+ gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints
+ gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints
+ gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid AND
+ gEfiPciRootBridgeIoProtocolGuid AND
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid
+
+
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL new file mode 100644 index 0000000000..9075769a49 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL @@ -0,0 +1,43 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(ALSD)
+{
+ Name(_HID,"ACPI0008")
+
+ Method(_STA,0)
+ {
+ If(LEqual(ALSE,2))
+ {
+ Return(0x000B) // ALS Enabled. Don't show it in UI.
+ }
+
+ Return(0x0000) // ALS Disabled. Hide it.
+ }
+
+ Method(_ALI)
+ {
+ Return (Or(ShiftLeft(LHIH,8),LLOW))
+ }
+
+ Name(_ALR, Package()
+ {
+ Package() {70, 0},
+ Package() {73, 10},
+ Package() {85, 80},
+ Package() {100, 300},
+ Package() {150, 1000}
+ })
+
+}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl new file mode 100644 index 0000000000..085b15cec2 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl @@ -0,0 +1,27 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+
+///////////////////////////////////////////////////////////////////////////////////
+//Values are set like this to have ASL compiler reserve enough space for objects
+///////////////////////////////////////////////////////////////////////////////////
+//
+// Available Sleep states
+//
+Name(SS1,0)
+Name(SS2,0)
+Name(SS3,1)
+Name(SS4,1)
+
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl new file mode 100644 index 0000000000..b62a305b7a --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl @@ -0,0 +1,252 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(\_PR)
+{
+ Processor(PR00, // Unique name for Processor 0.
+ 1, // Unique ID for Processor 0.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR01, // Unique name for Processor 1.
+ 2, // Unique ID for Processor 1.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR02, // Unique name for Processor 2.
+ 3, // Unique ID for Processor 2.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR03, // Unique name for Processor 3.
+ 4, // Unique ID for Processor 3.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR04, // Unique name for Processor 4.
+ 5, // Unique ID for Processor 4.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR05, // Unique name for Processor 5.
+ 6, // Unique ID for Processor 5.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR06, // Unique name for Processor 6.
+ 7, // Unique ID for Processor 6.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR07, // Unique name for Processor 7.
+ 8, // Unique ID for Processor 7.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR08, // Unique name for Processor 8.
+ 9, // Unique ID for Processor 8.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR09, // Unique name for Processor 9.
+ 10, // Unique ID for Processor 9.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR10, // Unique name for Processor 10.
+ 11, // Unique ID for Processor 10.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR11, // Unique name for Processor 11.
+ 12, // Unique ID for Processor 11.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR12, // Unique name for Processor 12.
+ 13, // Unique ID for Processor 12.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR13, // Unique name for Processor 13.
+ 14, // Unique ID for Processor 13.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR14, // Unique name for Processor 14.
+ 15, // Unique ID for Processor 14.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+
+ Processor(PR15, // Unique name for Processor 15.
+ 16, // Unique ID for Processor 15.
+ 0x1810, // P_BLK address = ACPIBASE + 10h.
+ 6) // P_BLK length = 6 bytes.
+ {}
+} // End Scope(\_PR)
+
+//
+// _CPC (Continuous Performance Control) Package declaration
+// Package
+// {
+// NumEntries, // Integer
+// Revision, // Integer
+// HighestPerformance, // Generic Register Descriptor
+// NominalPerformance, // Generic Register Descriptor
+// LowestNonlinearPerformance, // Generic Register Descriptor
+// LowestPerformance, // Generic Register Descriptor
+// GuaranteedPerformanceRegister, // Generic Register Descriptor
+// DesiredPerformanceRegister, // Generic Register Descriptor
+// MinimumPerformanceRegister, // Generic Register Descriptor
+// MaximumPerformanceRegister, // Generic Register Descriptor
+// PerformanceReductionToleranceRegister,// Generic Register Descriptor
+// TimeWindowRegister, // Generic Register Descriptor
+// CounterWraparoundTime, // Generic Register Descriptor
+// NominalCounterRegister, // Generic Register Descriptor
+// DeliveredCounterRegister, // Generic Register Descriptor
+// PerformanceLimitedRegister, // Generic Register Descriptor
+// EnableRegister // Generic Register Descriptor
+// }
+//
+Scope(\_PR.PR00)
+{
+ Name(CPC2, Package()
+ {
+ 21, // Number of entries
+ 02, // Revision
+ //
+ // Describe processor capabilities
+ //
+ ResourceTemplate() {Register(FFixedHW, 8, 0, 0x771, 4)}, // HighestPerformance
+ ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Performance - Maximum Non Turbo Ratio
+ ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
+ ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
+ ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
+ ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
+ ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
+ ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
+ ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
+ ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window register(Null)
+ ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
+ ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
+ ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
+ ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
+ ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
+ 1, // Autonomous selection enable register (Exclusively autonomous)
+ ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
+ ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
+ 0 // Reference performance (not supported)
+ })
+
+ Name(CPOC, Package()
+ {
+ 21, // Number of entries
+ 02, // Revision
+ //
+ // Describe processor capabilities
+ //
+ 255, // HighestPerformance
+ ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Performance - Maximum Non Turbo Ratio
+ ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
+ ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
+ ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
+ ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
+ ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
+ ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
+ ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
+ ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window register(Null)
+ ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
+ ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
+ ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
+ ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
+ ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
+ 1, // Autonomous selection enable register (Exclusively autonomous)
+ ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
+ ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
+ 0 // Reference performance (not supported)
+ })
+
+}// end Scope(\_PR.PR00)
+
+#ifndef SPS_SUPPORT // SPS is using Processor Aggregator Device different way
+Scope(\_SB)
+{
+ // The Processor Aggregator Device provides a control point that enables the platform to perform
+ // specific processor configuration and control that applies to all processors in the platform.
+ Device (PAGD)
+ {
+ Name (_HID, "ACPI000C") // Processor Aggregator Device
+
+ // _STA (Status)
+ //
+ // This object returns the current status of a device.
+ //
+ // Arguments: (0)
+ // None
+ // Return Value:
+ // An Integer containing a device status bitmap:
+ // Bit 0 - Set if the device is present.
+ // Bit 1 - Set if the device is enabled and decoding its resources.
+ // Bit 2 - Set if the device should be shown in the UI.
+ // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics).
+ // Bit 4 - Set if the battery is present.
+ // Bits 5-31 - Reserved (must be cleared).
+ //
+ Method(_STA)
+ {
+ If(\_OSI("Processor Aggregator Device")){
+ Return (0x0F) // Processor Aggregator Device is supported by this OS.
+ } Else {
+ Return (0) // No support in this OS.
+ }
+ }
+
+
+ // _PUR (Processor Utilization Request)
+ //
+ // The _PUR object is an optional object that may be declared under the Processor Aggregator Device
+ // and provides a means for the platform to indicate to OSPM the number of logical processors
+ // to be idled. OSPM evaluates the _PUR object as a result of the processing of a Notify event
+ // on the Processor Aggregator device object of type 0x80.
+ //
+ // Arguments: (0)
+ // None
+ // Return Value:
+ // Package
+ //
+ Name (_PUR, Package() // Requests a number of logical processors to be placed in an idle state.
+ {
+ 1, // RevisionID, Integer: Current value is 1
+ 0 // NumProcessors, Integer
+ })
+
+ } // end Device(PAGD)
+}// end Scope(\_SB)
+#endif // ndef SPS_SUPPORT
+
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL new file mode 100644 index 0000000000..eef1368a39 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL @@ -0,0 +1,130 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x02, // DSDT revision.
+ // A Revision field value greater than or equal to 2 signifies that integers
+ // declared within the Definition Block are to be evaluated as 64-bit values
+ "INTEL", // OEM ID (6 byte string)
+ "SKL ",// OEM table ID (8 byte string)
+ 0x0 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ External(LHIH)
+ External(LLOW)
+ External(IGDS)
+ External(LIDS)
+ External(BRTL)
+ External(ALSE)
+ External(GSMI)
+ External(\_SB.PCI0.GFX0, DeviceObj)
+ External(\_SB.PCI0.GFX0.ALSI)
+ External(\_SB.PCI0.GFX0.CDCK)
+ External(\_SB.PCI0.GFX0.CBLV)
+ External(\_SB.PCI0.GFX0.GSSE)
+ External(\_SB.PCI0.ISP0, DeviceObj)
+ External(\_SB.PCI0.PEG0, DeviceObj)
+ External(\_SB.PCI0.PEG0.PEGP, DeviceObj)
+ External(\_SB.PCI0.PEG1, DeviceObj)
+ External(\_SB.PCI0.PEG2, DeviceObj)
+ External(\_SB.PCI0.GFX0.DD1F, DeviceObj)
+ External(\_SB.PCI0.GFX0.GDCK, MethodObj)
+ External(\_SB.PCI0.GFX0.GHDS, MethodObj)
+ External(\_SB.PCI0.GFX0.AINT, MethodObj)
+ External(\_SB.PCI0.GFX0.GLID, MethodObj)
+ External(\_SB.PCI0.GFX0.GSCI, MethodObj)
+ External(\_PR.PR00, DeviceObj)
+ External(\_PR.PR00._PSS, MethodObj)
+ External(\_PR.PR00.LPSS, PkgObj)
+ External(\_PR.PR00.TPSS, PkgObj)
+ External(\_PR.PR00._PPC, MethodObj)
+ External(\_PR.CPPC, IntObj)
+ External(\_TZ.TZ00, DeviceObj)
+ External(\_TZ.TZ01, DeviceObj)
+ External(\_TZ.ETMD, IntObj)
+ External(\_TZ.FN00._OFF, MethodObj)
+ // Miscellaneous services enabled in Project
+ Include ("AMLUPD.asl")
+ Include ("Acpi/GlobalNvs.asl")
+ Include ("PciTree.asl")
+
+ if(LEqual(ECR1,1)){
+ Scope(\_SB.PCI0) {
+ //
+ // PCI-specific method's GUID
+ //
+ Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
+ //
+ // PCI's _DSM - an attempt at modular _DSM implementation
+ // When writing your own _DSM function that needs to include PCI-specific methods, do this:
+ //
+ // Method(_YOUR_DSM,4){
+ // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
+ // ...continue your _DSM by checking different GUIDs...
+ // else { return(0) }
+ // }
+ //
+ Method(PCID, 4, Serialized) {
+ If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID
+ If(LGreaterEqual(Arg1,3)) { // revision at least 3
+ If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function 0: list of supported functions
+ If(LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume
+ If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations
+ }
+ }
+ return (Buffer(1){0})
+ }
+ }//scope
+ }//if
+
+ Scope(\_SB.PCI0) {
+ //PciCheck, Arg0=UUID, returns true if support for 'PCI delays optimization ECR' is enabled and the UUID is correct
+ Method(PCIC,1,Serialized) {
+ If(LEqual(ECR1,1)) {
+ If(LEqual(Arg0, PCIG)) {
+ return (1)
+ }
+ }
+ return (0)
+ }
+ }
+
+ Include ("Pch.asl") // Not in this package. Refer to the PCH Reference Code accordingly
+ Include ("LpcB.asl")
+ Include ("Platform.asl")
+ Include ("CPU.asl")
+ Include ("PCI_DRC.ASL")
+ Include ("Video.asl")
+ Include ("PlatformGnvs.asl")
+ Include ("Gpe.asl")
+
+ Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state
+ if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})}
+ if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})}
+ if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})}
+ Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state
+
+ Method(PTS, 1) { // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE
+ If(Arg0) // entering any sleep state
+ {
+ }
+ }
+ Method(WAK, 1) { // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP
+ }
+}// End of ASL File
+
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl new file mode 100644 index 0000000000..a365882f6d --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl @@ -0,0 +1,845 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // General Purpose Events. This Scope handles the Run-time and
+ // Wake-time SCIs. The specific method called will be determined by
+ // the _Lxx value, where xx equals the bit location in the General
+ // Purpose Event register(s).
+
+
+ External(D1F0)
+ External(D1F1)
+ External(D1F2)
+ External(\_SB.PCI0.PEG0.HPME, MethodObj)
+ External(\_SB.PCI0.PEG1.HPME, MethodObj)
+ External(\_SB.PCI0.PEG2.HPME, MethodObj)
+ External(\_GPE.AL6F, MethodObj)
+ External(\_GPE.P0L6, MethodObj)
+ External(\_GPE.P1L6, MethodObj)
+ External(\_GPE.P2L6, MethodObj)
+ External(SGGP)
+ External(P1GP)
+ External(P2GP)
+ External(P0WK)
+ External(P1WK)
+ External(P2WK)
+ External(\_PR.HWPI, IntObj)
+ External(\_PR.DTSI, IntObj)
+
+ Scope(\_GPE)
+ {
+ // Note:
+ // Originally, the two GPE methods below are automatically generated, but, for ASL code restructuring,
+ // disabled the automatic generation and declare the ASL code here.
+ //
+
+ //
+ // This PME event (PCH's GPE 69h) is received on one or more of the PCI Express* ports or
+ // an assert PMEGPE message received via DMI
+ //
+ Method(_L69, 0, serialized) {
+ \_SB.PCI0.RP01.HPME()
+ \_SB.PCI0.RP02.HPME()
+ \_SB.PCI0.RP03.HPME()
+ \_SB.PCI0.RP04.HPME()
+ \_SB.PCI0.RP05.HPME()
+ \_SB.PCI0.RP06.HPME()
+ \_SB.PCI0.RP07.HPME()
+ \_SB.PCI0.RP08.HPME()
+ \_SB.PCI0.RP09.HPME()
+ \_SB.PCI0.RP10.HPME()
+ \_SB.PCI0.RP11.HPME()
+ \_SB.PCI0.RP12.HPME()
+ \_SB.PCI0.RP13.HPME()
+ \_SB.PCI0.RP14.HPME()
+ \_SB.PCI0.RP15.HPME()
+ \_SB.PCI0.RP16.HPME()
+ \_SB.PCI0.RP17.HPME()
+ \_SB.PCI0.RP18.HPME()
+ \_SB.PCI0.RP19.HPME()
+ \_SB.PCI0.RP20.HPME()
+ \_SB.PCI0.RP21.HPME()
+ \_SB.PCI0.RP22.HPME()
+ \_SB.PCI0.RP23.HPME()
+ \_SB.PCI0.RP24.HPME()
+
+ If(LEqual(D1F0,1))
+ {
+ \_SB.PCI0.PEG0.HPME()
+ Notify(\_SB.PCI0.PEG0, 0x02)
+ Notify(\_SB.PCI0.PEG0.PEGP, 0x02)
+ }
+
+ If(LEqual(D1F1,1))
+ {
+ \_SB.PCI0.PEG1.HPME()
+ Notify(\_SB.PCI0.PEG1, 0x02)
+ }
+
+ If(LEqual(D1F2,1))
+ {
+ \_SB.PCI0.PEG2.HPME()
+ Notify(\_SB.PCI0.PEG2, 0x02)
+ }
+ }
+
+ // PCI Express Hot-Plug caused the wake event.
+
+ Method(_L61)
+ {
+ Add(L01C,1,L01C) // Increment L01 Entry Count.
+
+ P8XH(0,0x01) // Output information to Port 80h.
+ P8XH(1,L01C)
+
+
+ // Check Root Port 1 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF),\_SB.PCI0.RP01.HPSX))
+ {
+ // Delay for 100ms to meet the timing requirements
+ // of the PCI Express Base Specification, Revision
+ // 1.0A, Section 6.6 ("...software must wait at
+ // least 100ms from the end of reset of one or more
+ // device before it is permitted to issue
+ // Configuration Requests to those devices").
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x1),LNotEqual(TBS1,0x1)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP01.PDCX)
+ {
+ // Clear all status bits first.
+
+ Store(1,\_SB.PCI0.RP01.PDCX)
+ Store(1,\_SB.PCI0.RP01.HPSX)
+
+ //
+ // PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
+ // In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
+ // hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
+ // disabled on empty slots prior booting to OS.
+ //
+ If(LNot(\_SB.PCI0.RP01.PDSX)) {
+ // The PCI Express slot is empty, so disable L0s on hot unplug
+ //
+ Store(0,\_SB.PCI0.RP01.L0SE)
+
+ }
+
+ // Perform proper notification
+ // to the OS.
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x1),LNotEqual(TBS1,0x1)))) {
+ Notify(\_SB.PCI0.RP01,0)
+ }
+ }
+ Else
+ {
+ // False event. Clear Hot-Plug Status
+ // then exit.
+
+ Store(1,\_SB.PCI0.RP01.HPSX)
+ }
+ }
+
+ // Check Root Port 2 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF),\_SB.PCI0.RP02.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x2),LNotEqual(TBS1,0x2)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP02.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP02.PDCX)
+ Store(1,\_SB.PCI0.RP02.HPSX)
+
+ If(LNot(\_SB.PCI0.RP02.PDSX)) {
+ Store(0,\_SB.PCI0.RP02.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x2),LNotEqual(TBS1,0x2)))) {
+ Notify(\_SB.PCI0.RP02,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP02.HPSX)
+ }
+ }
+
+ // Check Root Port 3 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF),\_SB.PCI0.RP03.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x3),LNotEqual(TBS1,0x3)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP03.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP03.PDCX)
+ Store(1,\_SB.PCI0.RP03.HPSX)
+
+ If(LNot(\_SB.PCI0.RP03.PDSX)) {
+ Store(0,\_SB.PCI0.RP03.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x3),LNotEqual(TBS1,0x3)))) {
+ Notify(\_SB.PCI0.RP03,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP03.HPSX)
+ }
+ }
+
+ // Check Root Port 4 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF),\_SB.PCI0.RP04.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x4),LNotEqual(TBS1,0x4)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP04.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP04.PDCX)
+ Store(1,\_SB.PCI0.RP04.HPSX)
+
+ If(LNot(\_SB.PCI0.RP04.PDSX)) {
+ Store(0,\_SB.PCI0.RP04.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x4),LNotEqual(TBS1,0x4)))) {
+ Notify(\_SB.PCI0.RP04,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP04.HPSX)
+ }
+ }
+
+ // Check Root Port 5 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF),\_SB.PCI0.RP05.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x5),LNotEqual(TBS1,0x5)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP05.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP05.PDCX)
+ Store(1,\_SB.PCI0.RP05.HPSX)
+
+ If(LNot(\_SB.PCI0.RP05.PDSX)) {
+ Store(0,\_SB.PCI0.RP05.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x5),LNotEqual(TBS1,0x5)))) {
+ Notify(\_SB.PCI0.RP05,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP05.HPSX)
+ }
+ }
+
+ // Check Root Port 6 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF),\_SB.PCI0.RP06.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x6),LNotEqual(TBS1,0x6)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP06.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP06.PDCX)
+ Store(1,\_SB.PCI0.RP06.HPSX)
+
+ If(LNot(\_SB.PCI0.RP06.PDSX)) {
+ Store(0,\_SB.PCI0.RP06.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x6),LNotEqual(TBS1,0x6)))) {
+ Notify(\_SB.PCI0.RP06,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP06.HPSX)
+ }
+ }
+
+ // Check Root Port 7 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF),\_SB.PCI0.RP07.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x7),LNotEqual(TBS1,0x7)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP07.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP07.PDCX)
+ Store(1,\_SB.PCI0.RP07.HPSX)
+
+ If(LNot(\_SB.PCI0.RP07.PDSX)) {
+ Store(0,\_SB.PCI0.RP07.L0SE)
+ }
+
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP07.HPSX)
+ }
+ }
+
+ // Check Root Port 8 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF),\_SB.PCI0.RP08.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x8),LNotEqual(TBS1,0x8)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP08.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP08.PDCX)
+ Store(1,\_SB.PCI0.RP08.HPSX)
+
+ If(LNot(\_SB.PCI0.RP08.PDSX)) {
+ Store(0,\_SB.PCI0.RP08.L0SE)
+ }
+
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP08.HPSX)
+ }
+ }
+
+ // Check Root Port 9 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF),\_SB.PCI0.RP09.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x9),LNotEqual(TBS1,0x9)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP09.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP09.PDCX)
+ Store(1,\_SB.PCI0.RP09.HPSX)
+
+ If(LNot(\_SB.PCI0.RP09.PDSX)) {
+ Store(0,\_SB.PCI0.RP09.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x9),LNotEqual(TBS1,0x9)))) {
+ Notify(\_SB.PCI0.RP09,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP09.HPSX)
+ }
+ }
+
+ // Check Root Port 10 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF),\_SB.PCI0.RP10.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xA),LNotEqual(TBS1,0xA)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP10.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP10.PDCX)
+ Store(1,\_SB.PCI0.RP10.HPSX)
+
+ If(LNot(\_SB.PCI0.RP10.PDSX)) {
+ Store(0,\_SB.PCI0.RP10.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xA),LNotEqual(TBS1,0xA)))) {
+ Notify(\_SB.PCI0.RP10,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP10.HPSX)
+ }
+ }
+
+ // Check Root Port 11 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF),\_SB.PCI0.RP11.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xB),LNotEqual(TBS1,0xB)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP11.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP11.PDCX)
+ Store(1,\_SB.PCI0.RP11.HPSX)
+
+ If(LNot(\_SB.PCI0.RP11.PDSX)) {
+ Store(0,\_SB.PCI0.RP11.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xB),LNotEqual(TBS1,0xB)))) {
+ Notify(\_SB.PCI0.RP11,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP11.HPSX)
+ }
+ }
+
+ // Check Root Port 12 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF),\_SB.PCI0.RP12.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xC),LNotEqual(TBS1,0xC)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP12.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP12.PDCX)
+ Store(1,\_SB.PCI0.RP12.HPSX)
+
+ If(LNot(\_SB.PCI0.RP12.PDSX)) {
+ Store(0,\_SB.PCI0.RP12.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xC),LNotEqual(TBS1,0xC)))) {
+ Notify(\_SB.PCI0.RP12,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP12.HPSX)
+ }
+ }
+
+ // Check Root Port 13 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF),\_SB.PCI0.RP13.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xD),LNotEqual(TBS1,0xD)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP13.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP13.PDCX)
+ Store(1,\_SB.PCI0.RP13.HPSX)
+
+ If(LNot(\_SB.PCI0.RP13.PDSX)) {
+ Store(0,\_SB.PCI0.RP13.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xD),LNotEqual(TBS1,0xD)))) {
+ Notify(\_SB.PCI0.RP13,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP13.HPSX)
+ }
+ }
+
+ // Check Root Port 14 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF),\_SB.PCI0.RP14.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xE),LNotEqual(TBS1,0xE)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP14.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP14.PDCX)
+ Store(1,\_SB.PCI0.RP14.HPSX)
+
+ If(LNot(\_SB.PCI0.RP14.PDSX)) {
+ Store(0,\_SB.PCI0.RP14.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xE),LNotEqual(TBS1,0xE)))) {
+ Notify(\_SB.PCI0.RP14,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP14.HPSX)
+ }
+ }
+
+ // Check Root Port 15 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF),\_SB.PCI0.RP15.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xF),LNotEqual(TBS1,0xF)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP15.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP15.PDCX)
+ Store(1,\_SB.PCI0.RP15.HPSX)
+
+ If(LNot(\_SB.PCI0.RP15.PDSX)) {
+ Store(0,\_SB.PCI0.RP15.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xF),LNotEqual(TBS1,0xF)))) {
+ Notify(\_SB.PCI0.RP15,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP15.HPSX)
+ }
+ }
+
+ // Check Root Port 16 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF),\_SB.PCI0.RP16.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x10),LNotEqual(TBS1,0x10)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP16.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP16.PDCX)
+ Store(1,\_SB.PCI0.RP16.HPSX)
+
+ If(LNot(\_SB.PCI0.RP16.PDSX)) {
+ Store(0,\_SB.PCI0.RP16.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x10),LNotEqual(TBS1,0x10)))) {
+ Notify(\_SB.PCI0.RP16,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP16.HPSX)
+ }
+ }
+
+ // Check Root Port 17 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF),\_SB.PCI0.RP17.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x11),LNotEqual(TBS1,0x11)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP17.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP17.PDCX)
+ Store(1,\_SB.PCI0.RP17.HPSX)
+
+ If(LNot(\_SB.PCI0.RP17.PDSX)) {
+ Store(0,\_SB.PCI0.RP17.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x11),LNotEqual(TBS1,0x11)))) {
+ Notify(\_SB.PCI0.RP17,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP17.HPSX)
+ }
+ }
+
+ // Check Root Port 18 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF),\_SB.PCI0.RP18.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x12),LNotEqual(TBS1,0x12)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP18.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP18.PDCX)
+ Store(1,\_SB.PCI0.RP18.HPSX)
+
+ If(LNot(\_SB.PCI0.RP18.PDSX)) {
+ Store(0,\_SB.PCI0.RP18.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x12),LNotEqual(TBS1,0x12)))) {
+ Notify(\_SB.PCI0.RP18,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP18.HPSX)
+ }
+ }
+
+ // Check Root Port 19 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF),\_SB.PCI0.RP19.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x13),LNotEqual(TBS1,0x13)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP19.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP19.PDCX)
+ Store(1,\_SB.PCI0.RP19.HPSX)
+
+ If(LNot(\_SB.PCI0.RP19.PDSX)) {
+ Store(0,\_SB.PCI0.RP19.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x13),LNotEqual(TBS1,0x13)))) {
+ Notify(\_SB.PCI0.RP19,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP19.HPSX)
+ }
+ }
+
+ // Check Root Port 20 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF),\_SB.PCI0.RP20.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x14),LNotEqual(TBS1,0x14)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP20.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP20.PDCX)
+ Store(1,\_SB.PCI0.RP20.HPSX)
+
+ If(LNot(\_SB.PCI0.RP20.PDSX)) {
+ Store(0,\_SB.PCI0.RP20.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x14),LNotEqual(TBS1,0x14)))) {
+ Notify(\_SB.PCI0.RP20,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP20.HPSX)
+ }
+ }
+
+ // Check Root Port 21 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP21.VDID,0xFFFFFFFF),\_SB.PCI0.RP21.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x21),LNotEqual(TBS1,0x21)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP21.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP21.PDCX)
+ Store(1,\_SB.PCI0.RP21.HPSX)
+
+ If(LNot(\_SB.PCI0.RP21.PDSX)) {
+ Store(0,\_SB.PCI0.RP21.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x21),LNotEqual(TBS1,0x21)))) {
+ Notify(\_SB.PCI0.RP21,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP21.HPSX)
+ }
+ }
+
+ // Check Root Port 22 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP22.VDID,0xFFFFFFFF),\_SB.PCI0.RP22.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x22),LNotEqual(TBS1,0x22)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP22.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP22.PDCX)
+ Store(1,\_SB.PCI0.RP22.HPSX)
+
+ If(LNot(\_SB.PCI0.RP22.PDSX)) {
+ Store(0,\_SB.PCI0.RP22.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x22),LNotEqual(TBS1,0x22)))) {
+ Notify(\_SB.PCI0.RP22,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP22.HPSX)
+ }
+ }
+
+ // Check Root Port 23 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP23.VDID,0xFFFFFFFF),\_SB.PCI0.RP23.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x23),LNotEqual(TBS1,0x23)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP23.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP23.PDCX)
+ Store(1,\_SB.PCI0.RP23.HPSX)
+
+ If(LNot(\_SB.PCI0.RP23.PDSX)) {
+ Store(0,\_SB.PCI0.RP23.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x23),LNotEqual(TBS1,0x23)))) {
+ Notify(\_SB.PCI0.RP23,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP23.HPSX)
+ }
+ }
+
+ // Check Root Port 24 for a Hot Plug Event if the Port is
+ // enabled.
+
+ If(LAnd(LNotEqual(\_SB.PCI0.RP24.VDID,0xFFFFFFFF),\_SB.PCI0.RP24.HPSX))
+ {
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x24),LNotEqual(TBS1,0x24)))) {
+ Sleep(100)
+ }
+
+ If(\_SB.PCI0.RP24.PDCX)
+ {
+ Store(1,\_SB.PCI0.RP24.PDCX)
+ Store(1,\_SB.PCI0.RP24.HPSX)
+
+ If(LNot(\_SB.PCI0.RP24.PDSX)) {
+ Store(0,\_SB.PCI0.RP24.L0SE)
+ }
+
+ If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x24),LNotEqual(TBS1,0x24)))) {
+ Notify(\_SB.PCI0.RP24,0)
+ }
+ }
+ Else
+ {
+ Store(1,\_SB.PCI0.RP24.HPSX)
+ }
+ }
+ }
+
+ //
+ // Software GPE caused the event.
+ //
+ Method(_L62)
+ {
+ // Clear GPE status bit.
+ Store(0,GPEC)
+
+ //
+ // Handle DTS Thermal SCI Event.
+ //
+ If(CondRefOf(\_PR.DTSE)){
+ If(LGreaterEqual(\_PR.DTSE, 0x01)){
+ If(LEqual(\_PR.DTSI, 1)){
+ Notify(\_TZ.TZ00,0x80)
+ Notify(\_TZ.TZ01,0x80)
+ ///
+ /// Clear HWP interrupt status
+ ///
+ Store(0,\_PR.DTSI)
+ }
+ }
+ }
+ ///
+ /// Handle HWP SCI event
+ ///
+ External(\_GPE.HLVT, MethodObj)
+ If(LEqual(\_PR.HWPI, 1)){
+ If(CondRefOf(\_GPE.HLVT)){
+ \_GPE.HLVT()
+ }
+ ///
+ /// Clear HWP interrupt status
+ ///
+ Store(0,\_PR.HWPI)
+ }
+ }
+
+ // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).
+
+ Method(_L66)
+ {
+ If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event?
+ {
+ \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI
+ }
+ }
+
+}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl new file mode 100644 index 0000000000..8210926859 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl @@ -0,0 +1,39 @@ +/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+// ITSS
+// Define the needed ITSS registers used by ASL on Interrupt
+// mapping.
+
+scope(\_SB){
+ OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208)
+ Field(ITSS, ByteAcc, NoLock, Preserve)
+ {
+ PARC, 8,
+ PBRC, 8,
+ PCRC, 8,
+ PDRC, 8,
+ PERC, 8,
+ PFRC, 8,
+ PGRC, 8,
+ PHRC, 8,
+ Offset(0x200), // Offset 3300h ITSSPRC - ITSS Power Reduction Control
+ , 1,
+ , 1,
+ SCGE, 1, // ITSSPRC[2]: 8254 Static Clock Gating Enable (8254CGE)
+
+ }
+}
+
+
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL new file mode 100644 index 0000000000..64b4722011 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL @@ -0,0 +1,205 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(FWHD) // Firmware Hub Device
+{
+ Name(_HID,EISAID("INT0800"))
+
+ Name(_CRS,ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly,0xFF000000,0x1000000)
+ })
+}
+
+
+Device(HPET) // High Performance Event Timer
+{
+ Name(_HID,EISAID("PNP0103"))
+ Name(_UID, 0)
+
+ Name(BUF0,ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite,0xFED00000,0x400,FED0)
+ })
+
+ Method(_STA,0)
+ {
+ // Show this Device only if the OS is WINXP or beyond.
+ If(HPTE)
+ {
+ Return(0x000F) // Enabled, do Display.
+ }
+
+ Return(0x0000) // Return Nothing.
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ If(HPTE)
+ {
+ // Check if HPETimer Base should be modified.
+ CreateDwordField(BUF0,^FED0._BAS,HPT0)
+ Store(HPTB,HPT0)
+ }
+
+ Return(BUF0)
+ }
+}
+
+Device(IPIC) // 8259 PIC
+{
+ Name(_HID,EISAID("PNP0000"))
+
+ Name(_CRS,ResourceTemplate()
+ {
+ IO(Decode16,0x20,0x20,0x01,0x02)
+ IO(Decode16,0x24,0x24,0x01,0x02)
+ IO(Decode16,0x28,0x28,0x01,0x02)
+ IO(Decode16,0x2C,0x2C,0x01,0x02)
+ IO(Decode16,0x30,0x30,0x01,0x02)
+ IO(Decode16,0x34,0x34,0x01,0x02)
+ IO(Decode16,0x38,0x38,0x01,0x02)
+ IO(Decode16,0x3C,0x3C,0x01,0x02)
+ IO(Decode16,0xA0,0xA0,0x01,0x02)
+ IO(Decode16,0xA4,0xA4,0x01,0x02)
+ IO(Decode16,0xA8,0xA8,0x01,0x02)
+ IO(Decode16,0xAC,0xAC,0x01,0x02)
+ IO(Decode16,0xB0,0xB0,0x01,0x02)
+ IO(Decode16,0xB4,0xB4,0x01,0x02)
+ IO(Decode16,0xB8,0xB8,0x01,0x02)
+ IO(Decode16,0xBC,0xBC,0x01,0x02)
+ IO(Decode16,0x4D0,0x4D0,0x01,0x02)
+ IRQNoFlags() {2}
+ })
+}
+
+
+Device(MATH) // Math Co-Processor
+{
+ Name(_HID,EISAID("PNP0C04"))
+
+ Name(_CRS,ResourceTemplate()
+ {
+ IO(Decode16,0xF0,0xF0,0x01,0x01)
+ IRQNoFlags() {13}
+ })
+
+ //
+ // Report device present for LPT-H.
+ //
+ Method (_STA, 0x0, NotSerialized)
+ {
+ If(LEqual(PCHV(), SPTH)) {
+ Return(0x1F)
+ } else {
+ Return(0x0)
+ }
+ }
+}
+
+
+Device(LDRC) // LPC Device Resource Consumption
+{
+ Name(_HID,EISAID("PNP0C02"))
+
+ Name(_UID,2)
+
+ Name(_CRS,ResourceTemplate() // This is for Cougar Point
+ {
+ IO(Decode16,0x2E,0x2E,0x1,0x02) // SIO Access.
+ IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access.
+ IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status.
+ IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F.
+ IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F.
+ IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F.
+ IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable.
+ IO(Decode16,0x80,0x80,0x1,0x1) // Port 80h.
+ IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F.
+ IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI.
+ IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O.
+ IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // ACPI IO Trap.
+ IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // DTS IO Trap.
+ IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // HotKey IO Trap.
+
+ IO(Decode16, 0x1800,0x1800,0x1,0xFF) // PCH ACPI Base
+
+ IO(Decode16,0x164e,0x164e,0x1,0x02) // 16 Byte I/O.
+ })
+}
+
+Device(LDR2) // LPC Device Resource Consumption for PCH GPIO
+{
+ Name(_HID,EISAID("PNP0C02"))
+
+ Name(_UID, "LPC_DEV")
+
+ // LPT-H GPIO resource map
+ Name(_CRS,ResourceTemplate()
+ {
+ IO(Decode16, 0x800,0x800,0x1,0x80) // PCH GPIO Base.
+ })
+
+ Method(_STA, 0, NotSerialized)
+ {
+ If(LEqual(PCHV(), SPTH)) {
+ Return(0xF)
+ } else {
+ Return(0)
+ }
+ }
+}
+
+Device(RTC) // RTC
+{
+ Name(_HID,EISAID("PNP0B00"))
+
+ Name(_CRS,ResourceTemplate()
+ {
+ IO(Decode16,0x70,0x70,0x01,0x08)
+ IRQNoFlags() {8}
+ })
+}
+
+Device(TIMR) // 8254 Timer
+{
+ Name(_HID,EISAID("PNP0100"))
+
+ Name(_CRS,ResourceTemplate()
+ {
+ IO(Decode16,0x40,0x40,0x01,0x04)
+ IO(Decode16,0x50,0x50,0x10,0x04)
+ IRQNoFlags() {0}
+ })
+}
+
+Device(CWDT)
+{
+ Name(_HID,EISAID("INT3F0D"))
+ Name(_CID,EISAID("PNP0C02"))
+ Name(BUF0,ResourceTemplate()
+ {
+ IO(Decode16, 0x1854, 0x1854, 0x4, 0x4) // PMBS 0x1800 + Offset 0x54
+ }
+ )
+
+ Method(_STA,0,Serialized)
+ {
+ Return(0x0F)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Return(BUF0)
+ }
+}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl new file mode 100644 index 0000000000..cf0eb2092a --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl @@ -0,0 +1,94 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+// LPC Bridge - Device 31, Function 0
+scope (\_SB.PCI0.LPCB) {
+ Include ("LPC_DEV.ASL")
+
+ // Define the KBC_COMMAND_REG-64, KBC_DATA_REG-60 Registers as an ACPI Operating
+ // Region. These registers will be used to skip kbd mouse
+ // resource settings if not present.
+ OperationRegion(PKBS, SystemIO, 0x60, 0x05)
+ Field(PKBS, ByteAcc, Lock, Preserve)
+ {
+ PKBD, 8,
+ , 8,
+ , 8,
+ , 8,
+ PKBC, 8
+ }
+ Device(PS2K) // PS2 Keyboard
+ {
+ Name(_HID,"MSFT0001")
+ Name(_CID,EISAID("PNP0303"))
+
+ Method(_STA)
+ {
+ If (P2MK) //Ps2 Keyboard and Mouse Enable
+ {
+ Return(0x000F)
+ }
+ Return(0x0000)
+ }
+
+ Name(_CRS,ResourceTemplate()
+ {
+ IO(Decode16,0x60,0x60,0x01,0x01)
+ IO(Decode16,0x64,0x64,0x01,0x01)
+ IRQ(Edge,ActiveHigh,Exclusive){0x01}
+ })
+
+ Name(_PRS, ResourceTemplate(){
+ StartDependentFn(0, 0) {
+ FixedIO(0x60,0x01)
+ FixedIO(0x64,0x01)
+ IRQNoFlags(){1}
+ }
+ EndDependentFn()
+ })
+
+ }
+
+ Device(PS2M) // PS/2 Mouse
+ {
+ Name(_HID,"MSFT0003")
+ Name(_CID,EISAID("PNP0F03"))
+
+ Method(_STA)
+ {
+ If (P2ME) //Ps2 Mouse Enable
+ {
+ If (P2MK) //Ps2 Keyboard and Mouse Enable
+ {
+ Return(0x000F)
+ }
+ }
+ Return(0x0000)
+ }
+
+ Name(_CRS,ResourceTemplate()
+ {
+ IRQ(Edge,ActiveHigh,Exclusive){0x0C}
+ })
+
+ Name(_PRS, ResourceTemplate(){
+ StartDependentFn(0, 0) {
+ IRQNoFlags(){12}
+ }
+ EndDependentFn()
+ })
+ }
+
+}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL new file mode 100644 index 0000000000..8b1593f1cf --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL @@ -0,0 +1,122 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+Scope (\_SB.PCI0){
+
+ Device(PDRC)
+ {
+ //
+ // PCI Device Resource Consumption
+ //
+
+ Name(_HID,EISAID("PNP0C02"))
+
+ Name(_UID,1)
+
+ Name(BUF0,ResourceTemplate()
+ {
+ //
+ // MCH BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.48h
+ //
+ Memory32Fixed(ReadWrite,0,0x08000,MCHB)
+ //
+ // DMI BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.68h
+ //
+ Memory32Fixed(ReadWrite,0,0x01000,DMIB)
+ //
+ // EP BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.40h
+ //
+ Memory32Fixed(ReadWrite,0,0x01000,EGPB)
+ //
+ // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
+ //
+ Memory32Fixed(ReadWrite,0,0,PCIX)
+
+ //
+ // MISC ICH TTT base address reserved for the TxT module use. Check if the hard code meets the real configuration.
+ // If not, dynamically update it like the _CRS method below.
+ //
+ Memory32Fixed(ReadWrite,0xFED20000,0x20000)
+
+ //
+ // VTD engine memory range. Check if the hard code meets the real configuration.
+ // If not, dynamically update it like the _CRS method below.
+ //
+ Memory32Fixed(ReadOnly, 0xFED90000, 0x00004000)
+
+ //
+ // MISC ICH. Check if the hard code meets the real configuration.
+ // If not, dynamically update it like the _CRS method below.
+ //
+ Memory32Fixed(ReadWrite,0xFED45000,0x4B000,TPMM)
+
+ //
+ // FLASH range
+ //
+ Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) //16MB as per IOH spec
+
+ //
+ // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
+ //
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
+
+ //
+ // Sx handler reserved MMIO
+ //
+ Memory32Fixed (ReadWrite, 0, 0, SXRE)
+
+ //
+ // Reserve HPET address decode range
+ //
+ Memory32Fixed (ReadWrite, 0, 0, HPET)
+
+ })
+
+
+ Method(_CRS,0,Serialized)
+ {
+
+ CreateDwordField(BUF0,^MCHB._BAS,MBR0)
+ Store(\_SB.PCI0.GMHB(), MBR0)
+
+ CreateDwordField(BUF0,^DMIB._BAS,DBR0)
+ Store(\_SB.PCI0.GDMB(), DBR0)
+
+ CreateDwordField(BUF0,^EGPB._BAS,EBR0)
+ Store(\_SB.PCI0.GEPB(), EBR0)
+
+ CreateDwordField(BUF0,^PCIX._BAS,XBR0)
+ Store(\_SB.PCI0.GPCB(), XBR0)
+
+ CreateDwordField(BUF0,^PCIX._LEN,XSZ0)
+ Store(\_SB.PCI0.GPCL(), XSZ0)
+
+ CreateDwordField(BUF0,^SXRE._BAS,SXRA)
+ Store(SXRB, SXRA)
+ CreateDwordField(BUF0,^SXRE._LEN,SXRL)
+ Store(SXRS, SXRL)
+
+ // HPET device claims the resource in LPC_DEV.ASL.
+ If(LNOT(HPTE)){
+ CreateDwordField(BUF0,^HPET._BAS,HBAS)
+ CreateDwordField(BUF0,^HPET._LEN,HLEN)
+ Store(HPTB, HBAS)
+ Store(0x400, HLEN)
+ }
+
+ Return(BUF0)
+ }
+ } //end of PDRC
+} // end of SB
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl new file mode 100644 index 0000000000..a32bb30f14 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl @@ -0,0 +1,312 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(\_SB) {
+ Name(PR00, Package(){
+// PCI Bridge
+// D31: cAVS, SMBus, GbE, Nothpeak
+ Package(){0x001FFFFF, 0, LNKA, 0 },
+ Package(){0x001FFFFF, 1, LNKB, 0 },
+ Package(){0x001FFFFF, 2, LNKC, 0 },
+ Package(){0x001FFFFF, 3, LNKD, 0 },
+// D30: SerialIo and SCS - can't use PIC
+// D29: PCI Express Port 9-16
+ Package(){0x001DFFFF, 0, LNKA, 0 },
+ Package(){0x001DFFFF, 1, LNKB, 0 },
+ Package(){0x001DFFFF, 2, LNKC, 0 },
+ Package(){0x001DFFFF, 3, LNKD, 0 },
+// D28: PCI Express Port 1-8
+ Package(){0x001CFFFF, 0, LNKA, 0 },
+ Package(){0x001CFFFF, 1, LNKB, 0 },
+ Package(){0x001CFFFF, 2, LNKC, 0 },
+ Package(){0x001CFFFF, 3, LNKD, 0 },
+// D27: PCI Express Port 17-20
+ Package(){0x001BFFFF, 0, LNKA, 0 },
+ Package(){0x001BFFFF, 1, LNKB, 0 },
+ Package(){0x001BFFFF, 2, LNKC, 0 },
+ Package(){0x001BFFFF, 3, LNKD, 0 },
+// D25: SerialIo - can't use PIC
+// D23: SATA controller
+ Package(){0x0017FFFF, 0, LNKA, 0 },
+// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
+ Package(){0x0016FFFF, 0, LNKA, 0 },
+ Package(){0x0016FFFF, 1, LNKB, 0 },
+ Package(){0x0016FFFF, 2, LNKC, 0 },
+ Package(){0x0016FFFF, 3, LNKD, 0 },
+// D21: SerialIo - can't use PIC
+// D20: xHCI, Thermal Subsystem, Camera IO Host Controller
+ Package(){0x0014FFFF, 0, LNKA, 0 },
+ Package(){0x0014FFFF, 1, LNKB, 0 },
+ Package(){0x0014FFFF, 2, LNKC, 0 },
+ Package(){0x0014FFFF, 3, LNKD, 0 },
+// D19: Integrated Sensor Hub - can't use PIC
+
+// Host Bridge
+// P.E.G. Root Port D1F0
+ Package(){0x0001FFFF, 0, LNKA, 0 },
+ Package(){0x0001FFFF, 1, LNKB, 0 },
+ Package(){0x0001FFFF, 2, LNKC, 0 },
+ Package(){0x0001FFFF, 3, LNKD, 0 },
+// P.E.G. Root Port D1F1
+// P.E.G. Root Port D1F2
+// SA IGFX Device
+ Package(){0x0002FFFF, 0, LNKA, 0 },
+// SA Thermal Device
+ Package(){0x0004FFFF, 0, LNKA, 0 },
+// SA SkyCam Device
+ Package(){0x0005FFFF, 0, LNKA, 0 },
+// SA GMM Device
+ Package(){0x0008FFFF, 0, LNKA, 0 },
+ })
+ Name(AR00, Package(){
+// PCI Bridge
+// D31: cAVS, SMBus, GbE, Nothpeak
+ Package(){0x001FFFFF, 0, 0, 16 },
+ Package(){0x001FFFFF, 1, 0, 17 },
+ Package(){0x001FFFFF, 2, 0, 18 },
+ Package(){0x001FFFFF, 3, 0, 19 },
+// D30: SerialIo and SCS
+ Package(){0x001EFFFF, 0, 0, 20 },
+ Package(){0x001EFFFF, 1, 0, 21 },
+ Package(){0x001EFFFF, 2, 0, 22 },
+ Package(){0x001EFFFF, 3, 0, 23 },
+// D29: PCI Express Port 9-16
+ Package(){0x001DFFFF, 0, 0, 16 },
+ Package(){0x001DFFFF, 1, 0, 17 },
+ Package(){0x001DFFFF, 2, 0, 18 },
+ Package(){0x001DFFFF, 3, 0, 19 },
+// D28: PCI Express Port 1-8
+ Package(){0x001CFFFF, 0, 0, 16 },
+ Package(){0x001CFFFF, 1, 0, 17 },
+ Package(){0x001CFFFF, 2, 0, 18 },
+ Package(){0x001CFFFF, 3, 0, 19 },
+// D27: PCI Express Port 17-20
+ Package(){0x001BFFFF, 0, 0, 16 },
+ Package(){0x001BFFFF, 1, 0, 17 },
+ Package(){0x001BFFFF, 2, 0, 18 },
+ Package(){0x001BFFFF, 3, 0, 19 },
+// D25: SerialIo
+ Package(){0x0019FFFF, 0, 0, 32 },
+ Package(){0x0019FFFF, 1, 0, 33 },
+ Package(){0x0019FFFF, 2, 0, 34 },
+// D23: SATA controller
+ Package(){0x0017FFFF, 0, 0, 16 },
+// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
+ Package(){0x0016FFFF, 0, 0, 16 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+ Package(){0x0016FFFF, 2, 0, 18 },
+ Package(){0x0016FFFF, 3, 0, 19 },
+// D21: SerialIo
+ Package(){0x0015FFFF, 0, 0, 16 },
+ Package(){0x0015FFFF, 1, 0, 17 },
+ Package(){0x0015FFFF, 2, 0, 18 },
+ Package(){0x0015FFFF, 3, 0, 19 },
+// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+// D19: Integrated Sensor Hub
+ Package(){0x0013FFFF, 0, 0, 20 },
+
+// Host Bridge
+// P.E.G. Root Port D1F0
+ Package(){0x0001FFFF, 0, 0, 16 },
+ Package(){0x0001FFFF, 1, 0, 17 },
+ Package(){0x0001FFFF, 2, 0, 18 },
+ Package(){0x0001FFFF, 3, 0, 19 },
+// P.E.G. Root Port D1F1
+// P.E.G. Root Port D1F2
+// SA IGFX Device
+ Package(){0x0002FFFF, 0, 0, 16 },
+// SA Thermal Device
+ Package(){0x0004FFFF, 0, 0, 16 },
+// SA SkyCam Device
+ Package(){0x0005FFFF, 0, 0, 16 },
+// SA GMM Device
+ Package(){0x0008FFFF, 0, 0, 16 },
+ })
+ Name(PR04, Package(){
+ Package(){0x0000FFFF, 0, LNKA, 0 },
+ Package(){0x0000FFFF, 1, LNKB, 0 },
+ Package(){0x0000FFFF, 2, LNKC, 0 },
+ Package(){0x0000FFFF, 3, LNKD, 0 },
+ })
+ Name(AR04, Package(){
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PR05, Package(){
+ Package(){0x0000FFFF, 0, LNKB, 0 },
+ Package(){0x0000FFFF, 1, LNKC, 0 },
+ Package(){0x0000FFFF, 2, LNKD, 0 },
+ Package(){0x0000FFFF, 3, LNKA, 0 },
+ })
+ Name(AR05, Package(){
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PR06, Package(){
+ Package(){0x0000FFFF, 0, LNKC, 0 },
+ Package(){0x0000FFFF, 1, LNKD, 0 },
+ Package(){0x0000FFFF, 2, LNKA, 0 },
+ Package(){0x0000FFFF, 3, LNKB, 0 },
+ })
+ Name(AR06, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+ Name(PR07, Package(){
+ Package(){0x0000FFFF, 0, LNKD, 0 },
+ Package(){0x0000FFFF, 1, LNKA, 0 },
+ Package(){0x0000FFFF, 2, LNKB, 0 },
+ Package(){0x0000FFFF, 3, LNKC, 0 },
+ })
+ Name(AR07, Package(){
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+ Name(PR08, Package(){
+ Package(){0x0000FFFF, 0, LNKA, 0 },
+ Package(){0x0000FFFF, 1, LNKB, 0 },
+ Package(){0x0000FFFF, 2, LNKC, 0 },
+ Package(){0x0000FFFF, 3, LNKD, 0 },
+ })
+ Name(AR08, Package(){
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PR09, Package(){
+ Package(){0x0000FFFF, 0, LNKB, 0 },
+ Package(){0x0000FFFF, 1, LNKC, 0 },
+ Package(){0x0000FFFF, 2, LNKD, 0 },
+ Package(){0x0000FFFF, 3, LNKA, 0 },
+ })
+ Name(AR09, Package(){
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PR0E, Package(){
+ Package(){0x0000FFFF, 0, LNKC, 0 },
+ Package(){0x0000FFFF, 1, LNKD, 0 },
+ Package(){0x0000FFFF, 2, LNKA, 0 },
+ Package(){0x0000FFFF, 3, LNKB, 0 },
+ })
+ Name(AR0E, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+ Name(PR0F, Package(){
+ Package(){0x0000FFFF, 0, LNKD, 0 },
+ Package(){0x0000FFFF, 1, LNKA, 0 },
+ Package(){0x0000FFFF, 2, LNKB, 0 },
+ Package(){0x0000FFFF, 3, LNKC, 0 },
+ })
+ Name(AR0F, Package(){
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+ Name(PR02, Package(){
+ Package(){0x0000FFFF, 0, LNKA, 0 },
+ Package(){0x0000FFFF, 1, LNKB, 0 },
+ Package(){0x0000FFFF, 2, LNKC, 0 },
+ Package(){0x0000FFFF, 3, LNKD, 0 },
+ })
+ Name(AR02, Package(){
+// P.E.G. Port Slot x16
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PR0A, Package(){
+// P.E.G. Port Slot x8
+ Package(){0x0000FFFF, 0, LNKB, 0 },
+ Package(){0x0000FFFF, 1, LNKC, 0 },
+ Package(){0x0000FFFF, 2, LNKD, 0 },
+ Package(){0x0000FFFF, 3, LNKA, 0 },
+ })
+ Name(AR0A, Package(){
+// P.E.G. Port Slot x8
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PR0B, Package(){
+// P.E.G. Port Slot x4
+ Package(){0x0000FFFF, 0, LNKC, 0 },
+ Package(){0x0000FFFF, 1, LNKD, 0 },
+ Package(){0x0000FFFF, 2, LNKA, 0 },
+ Package(){0x0000FFFF, 3, LNKB, 0 },
+ })
+ Name(AR0B, Package(){
+// P.E.G. Port Slot x4
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+//---------------------------------------------------------------------------
+// List of IRQ resource buffers compatible with _PRS return format.
+//---------------------------------------------------------------------------
+// Naming legend:
+// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
+// Note. PRSy name is generated if IRQ Link name starts from "LNK".
+// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
+//---------------------------------------------------------------------------
+ Name(PRSA, ResourceTemplate(){ // Link name: LNKA
+ IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
+ })
+ Alias(PRSA,PRSB) // Link name: LNKB
+ Alias(PRSA,PRSC) // Link name: LNKC
+ Alias(PRSA,PRSD) // Link name: LNKD
+ Alias(PRSA,PRSE) // Link name: LNKE
+ Alias(PRSA,PRSF) // Link name: LNKF
+ Alias(PRSA,PRSG) // Link name: LNKG
+ Alias(PRSA,PRSH) // Link name: LNKH
+//---------------------------------------------------------------------------
+// Begin PCI tree object scope
+//---------------------------------------------------------------------------
+ Device(PCI0) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
+ Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
+ Name(_ADR, 0x00000000)
+ Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
+ Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
+ Name(_UID, 0x0000) // Unique Bus ID, optional
+ Method(_PRT,0) {
+ If(PICM) {Return(AR00)} // APIC mode
+ Return (PR00) // PIC Mode
+ } // end _PRT
+
+ Include("HostBus.asl")
+ } // end PCI0 Bridge "Host Bridge"
+} // end _SB scope
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl new file mode 100644 index 0000000000..c784d516db --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl @@ -0,0 +1,1135 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#define TRAP_TYPE_DTS 0x02
+#define TRAP_TYPE_IGD 0x03
+#define TRAP_TYPE_BGD 0x04 // BIOS Guard
+
+// Define the following External variables to prevent a WARNING when
+// using ASL.EXE and an ERROR when using IASL.EXE.
+
+External(\PC00, IntObj) // PR00 _PDC Flags
+External(\PC01)
+External(\PC02)
+External(\PC03)
+External(\PC04)
+External(\PC05)
+External(\PC06)
+External(\PC07)
+External(\PC08)
+External(\PC09)
+External(\PC10)
+External(\PC11)
+External(\PC12)
+External(\PC13)
+External(\PC14)
+External(\PC15)
+External(\_PR.CFGD)
+External(\SGMD)
+
+//
+// DTS externals
+//
+External(\_PR.DTSF)
+External(\_PR.DTSE)
+External(\_PR.TRPD)
+External(\_PR.TRPF)
+External(\_PR.DSAE)
+//
+// SGX
+//
+External(\_PR.EPCS)
+External(\_PR.EMNA)
+External(\_PR.ELNG)
+
+External(\_SB.PCI0.GFX0.TCHE) // Technology enabled indicator
+External(\_SB.PCI0.GFX0.STAT) // State Indicator
+
+External(\_SB.TPM.PTS, MethodObj)
+External(\_SB.PCI0.PAUD.PUAM, MethodObj) //PUAM - PowerResource User Absent Mode
+External(\_SB.PCI0.XHC.DUAM, MethodObj) //DUAM - Device User Absent Mode for XHCI controller
+External(\_SB.PCI0.I2C4.GEXP.INVC, MethodObj)
+
+External(\_SB.PCI0.GFX0.IUEH, MethodObj)
+
+#define CONVERTIBLE_BUTTON 6
+#define DOCK_INDICATOR 7
+
+Name(ECUP, 1) // EC State indicator: 1- Normal Mode 0- Low Power Mode
+Mutex(EHLD, 0) // EC Hold indicator: 0- No one accessing the EC Power State 1- Someone else is accessing the EC Power State
+
+
+
+External(TBTD, MethodObj)
+External(TBTF, MethodObj)
+External(MMRP, MethodObj)
+External(MMTB, MethodObj)
+External(TBFF, MethodObj)
+External(FFTB, MethodObj)
+External(SXTB, MethodObj)
+
+
+// Interrupt specific registers
+include("Itss.asl")
+
+// Create a Global MUTEX.
+
+Mutex(MUTX,0)
+
+// OS Up mutex
+Mutex(OSUM, 0)
+// _WAK Finished Event
+Event(WFEV)
+
+// Define Port 80 as an ACPI Operating Region to use for debugging. Please
+// note that the Intel CRBs have the ability to ouput an entire DWord to
+// Port 80h for debugging purposes, so the model implemented here may not be
+// able to be used on OEM Designs.
+
+OperationRegion(PRT0,SystemIO,0x80,4)
+Field(PRT0,DwordAcc,Lock,Preserve)
+{
+ P80H, 32
+}
+
+// Port 80h Update:
+// Update 8 bits of the 32-bit Port 80h.
+//
+// Arguments:
+// Arg0: 0 = Write Port 80h, Bits 7:0 Only.
+// 1 = Write Port 80h, Bits 15:8 Only.
+// 2 = Write Port 80h, Bits 23:16 Only.
+// 3 = Write Port 80h, Bits 31:24 Only.
+// Arg1: 8-bit Value to write
+//
+// Return Value:
+// None
+
+Method(D8XH,2,Serialized)
+{
+ If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0.
+ {
+ Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)
+ }
+
+ If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8.
+ {
+ Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)
+ }
+
+ If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16.
+ {
+ Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)
+ }
+
+ If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24.
+ {
+ Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)
+ }
+
+ Store(P80D,P80H)
+}
+
+// Debug Port 80h Update:
+// If Acpidebug is enabled only then call D8XH to update 8 bits of the 32-bit Port 80h.
+//
+// Arguments:
+// Arg0: 0 = Write Port 80h, Bits 7:0 Only.
+// 1 = Write Port 80h, Bits 15:8 Only.
+// 2 = Write Port 80h, Bits 23:16 Only.
+// 3 = Write Port 80h, Bits 31:24 Only.
+// Arg1: 8-bit Value to write
+//
+// Return Value:
+// None
+Method(P8XH,2,Serialized)
+{
+ // If ACPI debug is enabled, then display post codes on Port 80h
+ If(CondRefOf(MDBG)) {// Check if ACPI Debug SSDT is loaded
+ D8XH(Arg0,Arg1)
+ }
+}
+
+Method(ADBG,1,Serialized)
+{
+ Return(0)
+}
+
+//
+// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.
+//
+OperationRegion(SPRT,SystemIO, 0xB2,2)
+Field (SPRT, ByteAcc, Lock, Preserve) {
+ SSMP, 8
+}
+
+// The _PIC Control Method is optional for ACPI design. It allows the
+// OS to inform the ASL code which interrupt controller is being used,
+// the 8259 or APIC. The reference code in this document will address
+// PCI IRQ Routing and resource allocation for both cases.
+//
+// The values passed into _PIC are:
+// 0 = 8259
+// 1 = IOAPIC
+
+Method(\_PIC,1)
+{
+ Store(Arg0,GPIC)
+ Store(Arg0,PICM)
+}
+
+// Prepare to Sleep. The hook is called when the OS is about to
+// enter a sleep state. The argument passed is the numeric value of
+// the Sx state.
+
+Method(_PTS,1)
+{
+ Store(0,P80D) // Zero out the entire Port 80h DWord.
+ D8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0.
+
+ ADBG(Concatenate("_PTS=",ToHexString(Arg0)))
+
+
+ // If code is executed, Wake from RI# via Serial Modem will be
+ // enabled. If code is not executed, COM Port Debugging throughout
+ // all Sx states will be enabled.
+
+ If(LEqual(Arg0,3))
+ {
+ //
+ // Disable update DTS temperature and threshold value in every SMI
+ //
+ If(CondRefOf(\_PR.DTSE)){
+ If(LAnd(\_PR.DTSE, LGreater(TCNT, 1)))
+ {
+ TRAP(TRAP_TYPE_DTS,30)
+ }
+ }
+ }
+
+
+ // Generate a SW SMI trap to save some NVRAM data back to CMOS.
+
+ // Don't enable IGD OpRegion support yet.
+ // TRAP(1, 81)
+ //
+ // Call TPM.PTS
+ //
+ If(CondRefOf(\_SB.TPM.PTS))
+ {
+ //
+ // Call TPM PTS method
+ //
+ \_SB.TPM.PTS (Arg0)
+ }
+
+}
+
+// Wake. This hook is called when the OS is about to wake from a
+// sleep state. The argument passed is the numeric value of the
+// sleep state the system is waking from.
+
+Method(_WAK,1,Serialized)
+{
+ D8XH(1,0xAB) // Beginning of _WAK.
+
+ ADBG("_WAK")
+
+ //
+ // Only set 8254 CG if Low Power S0 Idle Capability is enabled
+ //
+ If (LEqual(S0ID, One)) {
+ //
+ // Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2]
+ //
+ Store(0x01, \_SB.SCGE)
+ }
+
+ If(NEXP)
+ {
+ // Reinitialize the Native PCI Express after resume
+
+ If(And(OSCC,0x02))
+ {
+ \_SB.PCI0.NHPG()
+ }
+ If(And(OSCC,0x04)) // PME control granted?
+ {
+ \_SB.PCI0.NPME()
+ }
+ }
+
+
+ If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume
+ {
+
+ // Check to send Convertible/Dock state changes upon resume from Sx.
+ If(And(GBSX,0x40))
+ {
+ \_SB.PCI0.GFX0.IUEH(6)
+
+ //
+ // Do the same thing for Virtul Button device.
+ // Toggle Bit3 of PB1E(Slate/Notebook status)
+ //
+ Xor(PB1E, 0x08, PB1E)
+
+ }
+
+ If(And(GBSX,0x80))
+ {
+ \_SB.PCI0.GFX0.IUEH(7)
+
+ //
+ // Do the same thing for Virtul Button device.
+ // Toggle Bit4 of PB1E (Dock/Undock status)
+ //
+ Xor(PB1E, 0x10, PB1E)
+
+ }
+
+
+ If(CondRefOf(\_PR.DTSE)){
+ If(LAnd(\_PR.DTSE, LGreater(TCNT, 1)))
+ {
+ TRAP(TRAP_TYPE_DTS, 20)
+ }
+ }
+
+
+ // For PCI Express Express Cards, it is possible a device was
+ // either inserted or removed during an Sx State. The problem
+ // is that no wake event will occur for a given warm insertion
+ // or removal, so the OS will not become aware of any change.
+ // To get around this, re-enumerate all Express Card slots.
+ //
+ // If the Root Port is enabled, it may be assumed to be hot-pluggable.
+
+ If(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP01,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP02,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP03,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP04,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP05,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP06,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP07,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP08,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP09,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP10,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP11,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP12,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP13,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP14,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP15,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP16,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP17,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP18,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP19,0)
+ }
+
+ If(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF))
+ {
+ Notify (\_SB.PCI0.RP20,0)
+ }
+ }
+
+
+ Return(Package(){0,0})
+}
+
+// Get Buffer:
+// This method will take a buffer passed into the method and
+// create then return a smaller buffer based on the pointer
+// and size parameters passed in.
+//
+// Arguments:
+// Arg0: Pointer to start of new Buffer in passed in Buffer.
+// Arg1: Size of Buffer to create.
+// Arg2: Original Buffer
+//
+// Return Value:
+// Newly created buffer.
+
+Method(GETB,3,Serialized)
+{
+ Multiply(Arg0,8,Local0) // Convert Index.
+ Multiply(Arg1,8,Local1) // Convert Size.
+ CreateField(Arg2,Local0,Local1,TBF3) // Create Buffer.
+
+ Return(TBF3) // Return Buffer.
+}
+
+// Power Notification:
+// Perform all needed OS notifications during a
+// Power Switch.
+//
+// Arguments:
+// None
+//
+// Return Value:
+// None
+
+Method(PNOT,0,Serialized)
+{
+ //
+ // If MP enabled and driver support is present, notify all
+ // processors.
+ //
+ If(LGreater(TCNT, 1))
+ {
+ If(And(\PC00,0x0008)){
+ Notify(\_PR.PR00,0x80) // Eval PR00 _PPC.
+ }
+ If(And(\PC01,0x0008)){
+ Notify(\_PR.PR01,0x80) // Eval PR01 _PPC.
+ }
+ If(And(\PC02,0x0008)){
+ Notify(\_PR.PR02,0x80) // Eval PR02 _PPC.
+ }
+ If(And(\PC03,0x0008)){
+ Notify(\_PR.PR03,0x80) // Eval PR03 _PPC.
+ }
+ If(And(\PC04,0x0008)){
+ Notify(\_PR.PR04,0x80) // Eval PR04 _PPC.
+ }
+ If(And(\PC05,0x0008)){
+ Notify(\_PR.PR05,0x80) // Eval PR05 _PPC.
+ }
+ If(And(\PC06,0x0008)){
+ Notify(\_PR.PR06,0x80) // Eval PR06 _PPC.
+ }
+ If(And(\PC07,0x0008)){
+ Notify(\_PR.PR07,0x80) // Eval PR07 _PPC.
+ }
+ If(And(\PC08,0x0008)){
+ Notify(\_PR.PR08,0x80) // Eval PR08 _PPC.
+ }
+ If(And(\PC09,0x0008)){
+ Notify(\_PR.PR09,0x80) // Eval PR09 _PPC.
+ }
+ If(And(\PC10,0x0008)){
+ Notify(\_PR.PR10,0x80) // Eval PR10 _PPC.
+ }
+ If(And(\PC11,0x0008)){
+ Notify(\_PR.PR11,0x80) // Eval PR11 _PPC.
+ }
+ If(And(\PC12,0x0008)){
+ Notify(\_PR.PR12,0x80) // Eval PR12 _PPC.
+ }
+ If(And(\PC13,0x0008)){
+ Notify(\_PR.PR13,0x80) // Eval PR13 _PPC.
+ }
+ If(And(\PC14,0x0008)){
+ Notify(\_PR.PR14,0x80) // Eval PR14 _PPC.
+ }
+ If(And(\PC15,0x0008)){
+ Notify(\_PR.PR15,0x80) // Eval PR15 _PPC.
+ }
+ }Else{
+ Notify(\_PR.PR00,0x80) // Eval _PPC.
+ }
+
+ If(LGreater(TCNT, 1)){
+ If(LAnd(And(\PC00,0x0008),And(\PC00,0x0010))){
+ Notify(\_PR.PR00,0x81) // Eval PR00 _CST.
+ }
+ If(LAnd(And(\PC01,0x0008),And(\PC01,0x0010))){
+ Notify(\_PR.PR01,0x81) // Eval PR01 _CST.
+ }
+ If(LAnd(And(\PC02,0x0008),And(\PC02,0x0010))){
+ Notify(\_PR.PR02,0x81) // Eval PR02 _CST.
+ }
+ If(LAnd(And(\PC03,0x0008),And(\PC03,0x0010))){
+ Notify(\_PR.PR03,0x81) // Eval PR03 _CST.
+ }
+ If(LAnd(And(\PC04,0x0008),And(\PC04,0x0010))){
+ Notify(\_PR.PR04,0x81) // Eval PR04 _CST.
+ }
+ If(LAnd(And(\PC05,0x0008),And(\PC05,0x0010))){
+ Notify(\_PR.PR05,0x81) // Eval PR05 _CST.
+ }
+ If(LAnd(And(\PC06,0x0008),And(\PC06,0x0010))){
+ Notify(\_PR.PR06,0x81) // Eval PR06 _CST.
+ }
+ If(LAnd(And(\PC07,0x0008),And(\PC07,0x0010))){
+ Notify(\_PR.PR07,0x81) // Eval PR07 _CST.
+ }
+ If(LAnd(And(\PC08,0x0008),And(\PC08,0x0010))){
+ Notify(\_PR.PR08,0x81) // Eval PR08 _CST.
+ }
+ If(LAnd(And(\PC09,0x0008),And(\PC09,0x0010))){
+ Notify(\_PR.PR09,0x81) // Eval PR09 _CST.
+ }
+ If(LAnd(And(\PC10,0x0008),And(\PC10,0x0010))){
+ Notify(\_PR.PR10,0x81) // Eval PR10 _CST.
+ }
+ If(LAnd(And(\PC11,0x0008),And(\PC11,0x0010))){
+ Notify(\_PR.PR11,0x81) // Eval PR11 _CST.
+ }
+ If(LAnd(And(\PC12,0x0008),And(\PC12,0x0010))){
+ Notify(\_PR.PR12,0x81) // Eval PR12 _CST.
+ }
+ If(LAnd(And(\PC13,0x0008),And(\PC13,0x0010))){
+ Notify(\_PR.PR13,0x81) // Eval PR13 _CST.
+ }
+ If(LAnd(And(\PC14,0x0008),And(\PC14,0x0010))){
+ Notify(\_PR.PR14,0x81) // Eval PR14 _CST.
+ }
+ If(LAnd(And(\PC15,0x0008),And(\PC15,0x0010))){
+ Notify(\_PR.PR15,0x81) // Eval PR15 _CST.
+ }
+ } Else {
+ Notify(\_PR.PR00,0x81) // Eval _CST.
+ }
+
+
+} // end of Method(PNOT)
+
+//
+// Memory window to the CTDP registers starting at MCHBAR+5000h.
+//
+ OperationRegion (MBAR, SystemMemory, Add(\_SB.PCI0.GMHB(),0x5000), 0x1000)
+ Field (MBAR, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938)
+ PWRU, 4, // Power Units [3:0] unit value is calculated by 1 W / Power(2,PWR_UNIT). The default value of 0011b corresponds to 1/8 W.
+ Offset (0x9A0), // TURBO_POWER_LIMIT1 (MCHBAR+0x59A0)
+ PPL1, 15, // PKG_PWR_LIM_1 [14:0]
+ PL1E,1, // PKG_PWR_LIM1_EN [15]
+ CLP1,1, // Package Clamping Limitation 1
+ }
+Name(CLMP, 0) // save the clamp bit
+Name(PLEN,0) // save the power limit enable bit
+Name(PLSV,0x8000) // save value of PL1 upon entering CS
+Name(CSEM, 0) //semaphore to avoid multiple calls to SPL1. SPL1/RPL1 must always be called in pairs, like push/pop off a stack
+//
+// SPL1 (Set PL1 to 4.5 watts with clamp bit set)
+// Per Legacy Thermal management CS requirements, we would like to set the PL1 limit when entering CS to 4.5W with clamp bit set via MMIO.
+// This can be done in the ACPI object which gets called by graphics driver during CS Entry.
+// Likewise, during CS exit, the BIOS must reset the PL1 value to the previous value prior to CS entry and reset the clamp bit.
+//
+// Arguments:
+// None
+//
+// Return Value:
+// None
+Method(SPL1,0,Serialized)
+{
+ Name(PPUU,0) // units
+ If (LEqual(CSEM, 1))
+ {
+ Return() // we have already been called, must have CS exit before calling again
+ }
+ Store(1, CSEM) // record first call
+
+ Store (PPL1, PLSV) // save PL1 value upon entering CS
+ Store (PL1E, PLEN) // save PL1 Enable bit upon entering CS
+ Store (CLP1, CLMP) // save PL1 Clamp bit upon entering CS
+
+ If (LEqual(PWRU,0)) { // use PACKAGE_POWER_SKU_UNIT - Power Units[3:0]
+ Store(1,PPUU)
+ } Else {
+ ShiftLeft(Decrement(PWRU),2,PPUU) // get units
+ }
+
+ Multiply(PLVL,PPUU,Local0) // convert SETUP value to power units in milli-watts
+ Divide(Local0,1000,,Local1) // convert SETUP value to power units in watts
+ Store(Local1, PPL1) // copy value to PL1
+ Store(1, PL1E) // set Enable bit
+ Store(1, CLP1) // set Clamp bit
+}
+//
+// RPL1 (Restore the PL1 register to the values prior to CS entry)
+//
+// Arguments:
+// None
+//
+// Return Value:
+// None
+Method(RPL1,0,Serialized)
+{
+ Store (PLSV, PPL1) // restore value of PL1 upon exiting CS
+ Store(PLEN, PL1E) // restore the PL1 enable bit
+ Store(CLMP, CLP1) // restore the PL1 Clamp bit
+ Store(0, CSEM) // restore semaphore
+}
+
+Name(UAMS, 0) // User Absent Mode state, Zero - User Present; non-Zero - User not present
+Name(GLCK, 0) // a spin lock to avoid multi execution of GUAM
+// GUAM - Global User Absent Mode
+// Run when a change to User Absent mode is made, e.g. screen/display on/off events.
+// Any device that needs notifications of these events includes its own UAMN Control Method.
+//
+// Arguments:
+// Power State:
+// 00h = On
+// 01h = Standby
+// other value = do nothing & return
+//
+// Return Value:
+// None
+//
+Method(GUAM,1,Serialized)
+{
+ Switch(ToInteger(Arg0))
+ {
+ Case(0) // exit CS
+ {
+ If(LEqual(GLCK, 1)){
+ store(0, GLCK)
+
+ P8XH(0, 0xE1)
+ P8XH(1, 0xAB)
+ ADBG("Exit Resiliency")
+
+ // @Todo: Exit EC Low Power Mode here
+
+
+ If(PSCP){
+ // if P-state Capping s enabled
+ If (CondRefOf(\_PR.PR00._PPC))
+ {
+ Store(Zero, \_PR.CPPC)
+ PNOT()
+ }
+ }
+ If(PLCS){
+ RPL1() // restore PL1 to pre-CS value upon exiting CS
+ }
+ } // end GLCK=1
+ } // end case(0)
+
+ Case(1) // enter CS
+ {
+ If(LEqual(GLCK, 0)){
+ store(1, GLCK)
+
+ P8XH(0, 0xE0)
+ P8XH(1, 00)
+ ADBG("Enter Resiliency")
+
+ //@Todo: Enter EC Low Power Mode here
+
+
+ If(PSCP){
+ // if P-state Capping is enabled
+ If (LAnd(CondRefOf(\_PR.PR00._PSS), CondRefOf(\_PR.PR00._PPC)))
+ {
+ If(And(\PC00,0x0400))
+ {
+ Subtract(SizeOf(\_PR.PR00.TPSS), One, \_PR.CPPC)
+ } Else {
+ Subtract(SizeOf(\_PR.PR00.LPSS), One, \_PR.CPPC)
+ }
+ PNOT()
+ }
+ }
+ If(PLCS){
+ SPL1() // set PL1 to low value upon CS entry
+ }
+ } // end GLCK=0
+ } // end case(1)
+ Default{
+ Return() // do nothing
+ }
+ } // end switch(arg0)
+
+ Store(LAnd(Arg0, LNot(PWRS)), UAMS) // UAMS: User Absent Mode state, Zero - User Present; non-Zero - User not present
+ P_CS() // Powergating during CS
+
+} // end method GUAM()
+
+// Power CS Powergated Devices:
+// Method to enable/disable power during CS
+Method(P_CS,0,Serialized)
+{
+ // NOTE: Do not turn ON Touch devices from here. Touch does not have PUAM
+ If(CondRefOf(\_SB.PCI0.PAUD.PUAM)){ // Notify Codec(HD-A/ADSP)
+ \_SB.PCI0.PAUD.PUAM()
+ }
+ // Adding back USB powergating (ONLY for Win8) until RTD3 walkup port setup implementation is complete */
+ If(LEqual(OSYS,2012)){ // ONLY for Win8 OS
+ If(CondRefOf(\_SB.PCI0.XHC.DUAM)){ // Notify USB port- RVP
+ \_SB.PCI0.XHC.DUAM()
+ }
+ }
+ // TODO: Add calls to UAMN methods for
+ // * USB controller(s)
+ // * Embedded Controller
+ // * Sensor devices
+ // * Audio DSP?
+ // * Any other devices dependent on User Absent mode for power controls
+}
+
+// SMI I/O Trap:
+// Generate a Mutex protected SMI I/O Trap.
+//
+// Arguments:
+// Arg0: I/O Trap type.
+// 2 - For DTS
+// 3 - For IGD
+// 4 - For BIOS Guard Tools
+// Arg1: SMI I/O Trap Function to call.
+//
+// Return Value:
+// SMI I/O Trap Return value.
+// 0 = Success. Non-zero = Failure.
+
+Scope(\)
+{
+ //
+ // The IO address in this ACPI Operating Region will be updated during POST.
+ // This address range is used as a HotKey I/O Trap SMI so that ASL and SMI can
+ // communicate when needed.
+ //
+ OperationRegion(IO_H,SystemIO,0x1000,0x4)
+ Field(IO_H,ByteAcc,NoLock,Preserve) {
+ TRPH, 8
+ }
+}
+
+Method(TRAP,2,Serialized)
+{
+ Store(Arg1,SMIF) // Store SMI Function.
+
+ If(LEqual(Arg0,TRAP_TYPE_DTS)) // Is DTS IO Trap?
+ {
+ Store(Arg1,\_PR.DTSF) // Store the function number global NVS
+ Store(0,\_PR.TRPD) // Generate IO Trap.
+ Return(\_PR.DTSF) // Return status from SMI handler
+ }
+
+ If(LEqual(Arg0,TRAP_TYPE_IGD)) // Is IGD IO Trap?
+ {
+ Store(0,TRPH) // Generate IO Trap.
+ }
+
+ If(LEqual(Arg0,TRAP_TYPE_BGD)) // Is BIOS Guard TOOLS IO Trap?
+ {
+ Store(0,\_PR.TRPF) // Generate IO Trap
+ }
+
+ Return(SMIF) // Return SMIF. 0 = Success.
+}
+
+// Note: Only add the indicator device needed by the platform.
+
+//
+// System Bus
+//
+Scope(\_SB.PCI0)
+{
+
+ Method(_INI,0, Serialized)
+ {
+
+ // Determine the OS and store the value, where:
+ //
+ // OSYS = 1000 = Linux.
+ // OSYS = 2000 = WIN2000.
+ // OSYS = 2001 = WINXP, RTM or SP1.
+ // OSYS = 2002 = WINXP SP2.
+ // OSYS = 2006 = Vista.
+ // OSYS = 2009 = Windows 7 and Windows Server 2008 R2.
+ // OSYS = 2012 = Windows 8 and Windows Server 2012.
+ // OSYS = 2013 = Windows Blue.
+ //
+ // Assume Windows 2000 at a minimum.
+
+ Store(2000,OSYS)
+
+ // Check for a specific OS which supports _OSI.
+
+ If(CondRefOf(\_OSI))
+ {
+ If(\_OSI("Linux"))
+ {
+ Store(1000,OSYS)
+ }
+
+ If(\_OSI("Windows 2001")) // Windows XP
+ {
+ Store(2001,OSYS)
+ }
+
+ If(\_OSI("Windows 2001 SP1")) //Windows XP SP1
+ {
+ Store(2001,OSYS)
+ }
+
+ If(\_OSI("Windows 2001 SP2")) //Windows XP SP2
+ {
+ Store(2002,OSYS)
+ }
+
+ If (\_OSI( "Windows 2001.1")) //Windows Server 2003
+ {
+ Store(2003,OSYS)
+ }
+
+ If(\_OSI("Windows 2006")) //Windows Vista
+ {
+ Store(2006,OSYS)
+ }
+
+ If(\_OSI("Windows 2009")) //Windows 7 and Windows Server 2008 R2
+ {
+ Store(2009,OSYS)
+ }
+
+ If(\_OSI("Windows 2012")) //Windows 8 and Windows Server 2012
+ {
+ Store(2012,OSYS)
+ }
+
+ If(\_OSI("Windows 2013")) //Windows 8.1 and Windows Server 2012 R2
+ {
+ Store(2013,OSYS)
+ }
+
+ If(\_OSI("Windows 2015")) //Windows 10
+ {
+ Store(2015,OSYS)
+ }
+ }
+
+ //
+ // Set DTS NVS data means in OS ACPI mode enabled insteads of GlobalNvs OperatingSystem (OSYS)
+ //
+ If(CondRefOf(\_PR.DTSE)){
+ If(LGreaterEqual(\_PR.DTSE, 0x01)){
+ Store(0x01, \_PR.DSAE)
+ }
+ }
+
+ }
+
+ Method(NHPG,0,Serialized)
+ {
+ Store(0,^RP01.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP02.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP03.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP04.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP05.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP06.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP07.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP08.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP09.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP10.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP11.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP12.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP13.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP14.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP15.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP16.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP17.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP18.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP19.HPEX) // clear the hot plug SCI enable bit
+ Store(0,^RP20.HPEX) // clear the hot plug SCI enable bit
+
+ Store(1,^RP01.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP02.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP03.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP04.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP05.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP06.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP07.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP08.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP09.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP10.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP11.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP12.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP13.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP14.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP15.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP16.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP17.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP18.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP19.HPSX) // clear the hot plug SCI status bit
+ Store(1,^RP20.HPSX) // clear the hot plug SCI status bit
+ }
+
+ Method(NPME,0,Serialized)
+ {
+ Store(0,^RP01.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP02.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP03.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP04.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP05.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP06.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP07.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP08.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP09.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP10.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP11.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP12.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP13.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP14.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP15.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP16.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP17.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP18.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP19.PMEX) // clear the PME SCI enable bit
+ Store(0,^RP20.PMEX) // clear the PME SCI enable bit
+
+ Store(1,^RP01.PMSX) // clear the PME SCI status bit
+ Store(1,^RP02.PMSX) // clear the PME SCI status bit
+ Store(1,^RP03.PMSX) // clear the PME SCI status bit
+ Store(1,^RP04.PMSX) // clear the PME SCI status bit
+ Store(1,^RP05.PMSX) // clear the PME SCI status bit
+ Store(1,^RP06.PMSX) // clear the PME SCI enable bit
+ Store(1,^RP07.PMSX) // clear the PME SCI status bit
+ Store(1,^RP08.PMSX) // clear the PME SCI status bit
+ Store(1,^RP09.PMSX) // clear the PME SCI status bit
+ Store(1,^RP10.PMSX) // clear the PME SCI status bit
+ Store(1,^RP11.PMSX) // clear the PME SCI status bit
+ Store(1,^RP12.PMSX) // clear the PME SCI status bit
+ Store(1,^RP13.PMSX) // clear the PME SCI status bit
+ Store(1,^RP14.PMSX) // clear the PME SCI status bit
+ Store(1,^RP15.PMSX) // clear the PME SCI status bit
+ Store(1,^RP16.PMSX) // clear the PME SCI status bit
+ Store(1,^RP17.PMSX) // clear the PME SCI status bit
+ Store(1,^RP18.PMSX) // clear the PME SCI status bit
+ Store(1,^RP19.PMSX) // clear the PME SCI status bit
+ Store(1,^RP20.PMSX) // clear the PME SCI status bit
+ }
+}
+
+Scope (\)
+{
+ //
+ // Global Name, returns current Interrupt controller mode;
+ // updated from _PIC control method
+ //
+ Name(PICM, 0)
+
+ //
+ // Procedure: GPRW
+ //
+ // Description: Generic Wake up Control Method ("Big brother")
+ // to detect the Max Sleep State available in ASL Name scope
+ // and Return the Package compatible with _PRW format.
+ // Input: Arg0 = bit offset within GPE register space device event will be triggered to.
+ // Arg1 = Max Sleep state, device can resume the System from.
+ // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System.
+ // Output: _PRW package
+ //
+ Name(PRWP, Package(){Zero, Zero}) // _PRW Package
+
+ Method(GPRW, 2)
+ {
+ Store(Arg0, Index(PRWP, 0)) // copy GPE#
+ //
+ // SS1-SS4 - enabled in BIOS Setup Sleep states
+ //
+ Store(ShiftLeft(SS1,1),Local0) // S1 ?
+ Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ?
+ Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ?
+ Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ?
+ //
+ // Local0 has a bit mask of enabled Sx(1 based)
+ // bit mask of enabled in BIOS Setup Sleep states(1 based)
+ //
+ If(And(ShiftLeft(1, Arg1), Local0))
+ {
+ //
+ // Requested wake up value (Arg1) is present in Sx list of available Sleep states
+ //
+ Store(Arg1, Index(PRWP, 1)) // copy Sx#
+ }
+ Else
+ {
+ //
+ // Not available -> match Wake up value to the higher Sx state
+ //
+ ShiftRight(Local0, 1, Local0)
+ // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x
+ // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx
+ // } Else { // ??? Win2k / XP
+ FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx
+ // }
+ }
+
+ Return(PRWP)
+ }
+}
+
+
+Scope (\_SB)
+{
+ Name(OSCI, 0) // \_SB._OSC DWORD2 input
+ Name(OSCO, 0) // \_SB._OSC DWORD2 output
+ Name(OSCP, 0) // \_SB._OSC CAPABILITIES
+ // _OSC (Operating System Capabilities)
+ // _OSC under \_SB scope is used to convey platform wide OSPM capabilities.
+ // For a complete description of _OSC ACPI Control Method, refer to ACPI 5.0
+ // specification, section 6.2.10.
+ // Arguments: (4)
+ // Arg0 - A Buffer containing the UUID "0811B06E-4A27-44F9-8D60-3CBBC22E7B48"
+ // Arg1 - An Integer containing the Revision ID of the buffer format
+ // Arg2 - An Integer containing a count of entries in Arg3
+ // Arg3 - A Buffer containing a list of DWORD capabilities
+ // Return Value:
+ // A Buffer containing the list of capabilities
+ //
+ Method(_OSC,4,Serialized)
+ {
+ //
+ // Point to Status DWORD in the Arg3 buffer (STATUS)
+ //
+ CreateDWordField(Arg3, 0, STS0)
+ //
+ // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
+ //
+ CreateDwordField(Arg3, 4, CAP0)
+
+
+ //
+ // Only set 8254 CG if Low Power S0 Idle Capability is enabled
+ //
+ If (LEqual(S0ID, One)) {
+ //
+ // Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2]
+ //
+ Store(0x01, \_SB.SCGE)
+ }
+
+ //
+ // Check UUID
+ //
+ If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
+ {
+ //
+ // Check Revision
+ //
+ If(LEqual(Arg1,One))
+ {
+ Store(CAP0, OSCP)
+ If(And(CAP0,0x04)) // Check _PR3 Support(BIT2)
+ {
+ Store(0x04, OSCO)
+ If(LNotEqual(And(SGMD,0x0F),2)) // Check Switchable/Hybrid graphics is not enabled in bios setup [SgModeMuxless]?
+ {
+ If(LEqual(RTD3,0)) // Is RTD3 support disabled in Bios Setup?
+ {
+ // RTD3 is disabled via BIOS Setup.
+ And(CAP0, 0x3B, CAP0) // Clear _PR3 capability
+ Or(STS0, 0x10, STS0) // Indicate capability bit is cleared
+ }
+ }
+ }
+ } Else{
+ And(STS0,0xFFFFFF00,STS0)
+ Or(STS0,0xA, STS0) // Unrecognised Revision and report OSC failure
+ }
+ } Else {
+ And(STS0,0xFFFFFF00,STS0)
+ Or (STS0,0x6, STS0) // Unrecognised UUID and report OSC failure
+ }
+
+ Return(Arg3)
+ } // End _OSC
+
+} // End of Scope(\_SB)
+
+//
+// CS Wake up event support
+//
+Scope (\_SB)
+{
+ // Define Sleep button to put the system in sleep
+ Device (SLPB)
+ {
+ Name (_HID, EISAID ("PNP0C0E"))
+ Name (_STA, 0x0B)
+ // Bit0 - the device is present: Yes.
+ // Bit1 - the device is enabled and decoding its resources: Yes.
+ // Bit2 - the device should be shown in the UI: No.
+ // Bit3 - the device is functioning properly: Yes.
+ // Bit4 - the battery is present: N/A
+ }
+} // End of Scope(\_SB)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.asl new file mode 100644 index 0000000000..60223054ab --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.asl @@ -0,0 +1,14 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl new file mode 100644 index 0000000000..a77a1f5805 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl @@ -0,0 +1,35 @@ +/** @file
+ ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+
+External(DIDX)
+
+// Brightness Notification:
+// Generate a brightness related notification
+// to the LFP if its populated.
+//
+// Arguments:
+// Arg0: Notification value.
+//
+// Return Value:
+// None
+
+Method(BRTN,1,Serialized)
+{
+ If(LEqual(And(DIDX,0x0F00),0x400))
+ {
+ Notify(\_SB.PCI0.GFX0.DD1F,Arg0)
+ }
+}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c new file mode 100644 index 0000000000..c4651f117a --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c @@ -0,0 +1,782 @@ +/** @file
+ Acpi Gnvs Init Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/GlobalNvsArea.h>
+extern GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
+
+VOID
+UpdateDsdt (
+ IN VOID *Table
+ )
+{
+ UINT8 *CurrPtr;
+ UINT8 *TmpDsdtPointer;
+ UINT8 *DsdtPointer;
+ UINT32 *Signature;
+ UINT8 *Operation;
+ UINT32 *Address;
+ UINT8 *Value;
+ UINT16 *Size;
+ BOOLEAN EnterDock = FALSE;
+
+ UINT8 MaximumDsdtPointLength;
+
+ MaximumDsdtPointLength = 20;
+
+ //
+ // Fix up the AML code in the DSDT affected by end user options.
+ // Fix up the following ASL Code:
+ // (1) ACPI Global NVS Memory Base and Size.
+ // (2) ACPI Graphics NVS Memory Base and Size.
+ // (3) SMBus I/O Base.
+ // (4) Thermal Management Methods.
+ //
+ //
+ // Loop through the ASL looking for values that we must fix up.
+ //
+ CurrPtr = (UINT8 *) Table;
+ for (DsdtPointer = CurrPtr;
+ DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
+ DsdtPointer++
+ ) {
+ Signature = (UINT32 *) DsdtPointer;
+ switch (*Signature) {
+ //
+ // GNVS operation region
+ //
+ case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
+ //
+ // Conditional match. For Region Objects, the Operator will always be the
+ // byte immediately before the specific name. Therefore, subtract 1 to check
+ // the Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_EXT_REGION_OP) {
+ Address = (UINT32 *) (DsdtPointer + 6);
+ *Address = (UINT32) (UINTN) mGlobalNvsArea.Area;
+ Size = (UINT16 *) (DsdtPointer + 11);
+ *Size = sizeof (EFI_GLOBAL_NVS_AREA);
+ }
+ break;
+
+ //
+ // _AC0 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '0')):
+ //
+ // Conditional match. _AC0 is >63 and <4095 bytes, so the package length is 2 bytes.
+ // Therefore, subtract 3 to check the Operator.
+ //
+ Operation = DsdtPointer - 3;
+ if (*Operation == AML_METHOD_OP) {
+ //
+ // Check if we want _AC0 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '0');
+ }
+ }
+ break;
+
+ //
+ // _AL0 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '0')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL0 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '0');
+ }
+ }
+ break;
+
+ //
+ // _AC1 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '1')):
+ //
+ // Conditional match. _AC1 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC1 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '1');
+ }
+ }
+ break;
+
+ //
+ // _AL1 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '1')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL1 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '1');
+ }
+ }
+ break;
+
+ //
+ // _AC2 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '2')):
+ //
+ // Conditional match. _AC2 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC2 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '2');
+ }
+ }
+ break;
+
+ //
+ // _AL2 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '2')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL2 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '2');
+ }
+ }
+ break;
+
+ //
+ // _AC3 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '3')):
+ //
+ // Conditional match. _AC3 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC3 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '3');
+ }
+ }
+ break;
+
+ //
+ // _AL3 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '3')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL3 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '3');
+ }
+ }
+ break;
+
+ //
+ // _AC4 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '4')):
+ //
+ // Conditional match. _AC4 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC4 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '4');
+ }
+ }
+ break;
+
+ //
+ // _AL4 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '4')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL4 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '4');
+ }
+ }
+ break;
+
+ //
+ // _AC5 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '5')):
+ //
+ // Conditional match. _AC5 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC5 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '5');
+ }
+ }
+ break;
+
+ //
+ // _AL5 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '5')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL5 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '5');
+ }
+ }
+ break;
+
+ //
+ // _AC6 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '6')):
+ //
+ // Conditional match. _AC6 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC6 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '6');
+ }
+ }
+ break;
+
+ //
+ // _AL6 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '6')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL6 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '6');
+ }
+ }
+ break;
+
+ //
+ // _AC7 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '7')):
+ //
+ // Conditional match. _AC7 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC7 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '7');
+ }
+ }
+ break;
+
+ //
+ // _AL7 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '7')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL7 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '7');
+ }
+ }
+ break;
+
+ //
+ // _AC8 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '8')):
+ //
+ // Conditional match. _AC8 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC8 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '8');
+ }
+ }
+ break;
+
+ //
+ // _AL8 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '8')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL8 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '8');
+ }
+ }
+ break;
+
+ //
+ // _AC9 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'C', '9')):
+ //
+ // Conditional match. _AC9 is < 63 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _AC9 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'C', '9');
+ }
+ }
+ break;
+
+ //
+ // _AL9 method
+ //
+ case (SIGNATURE_32 ('_', 'A', 'L', '9')):
+ //
+ // Conditional match. For Name Objects, the Operator will always be the byte
+ // immediately before the specific name. Therefore, subtract 1 to check the
+ // Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+
+ //
+ // Check if we want _AL9 enabled
+ //
+ if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'A', 'L', '9');
+ }
+ }
+ break;
+
+ //
+ // _PSL method
+ //
+ case (SIGNATURE_32 ('_', 'P', 'S', 'L')):
+ //
+ // Conditional match. _PSL is < 256 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 3;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _PSL enabled
+ //
+ if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'P', 'S', 'L');
+ }
+ }
+ break;
+
+ //
+ // _PSV method
+ //
+ case (SIGNATURE_32 ('_', 'P', 'S', 'V')):
+ //
+ // Conditional match. _PSV is < 256 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 3;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _PSV enabled
+ //
+ if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'P', 'S', 'V');
+ }
+ }
+ break;
+
+ //
+ // _CRT method
+ //
+ case (SIGNATURE_32 ('_', 'C', 'R', 'T')):
+ //
+ // Conditional match. _CRT is < 256 bytes, so the package length is 1 byte.
+ // Subtract 3 to check the Operator for CRB, subract 2 for Harris Beach.
+ //
+ Operation = DsdtPointer - 3;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _CRT enabled
+ //
+ if (PcdGet8 (PcdDisableCriticalTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'C', 'R', 'T');
+ }
+ }
+ break;
+
+ //
+ // _TC1 method
+ //
+ case (SIGNATURE_32 ('_', 'T', 'C', '1')):
+ //
+ // Conditional match. _TC1 is < 256 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _TC1 enabled
+ //
+ if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'T', 'C', '1');
+ }
+ }
+ break;
+
+ //
+ // _TC2 method
+ //
+ case (SIGNATURE_32 ('_', 'T', 'C', '2')):
+ //
+ // Conditional match. _TC2 is < 256 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _TC2 enabled
+ //
+ if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'T', 'C', '2');
+ }
+ }
+ break;
+
+ //
+ // _TSP method
+ //
+ case (SIGNATURE_32 ('_', 'T', 'S', 'P')):
+ //
+ // Conditional match. _TSP is < 256 bytes, so the package length is 1 byte.
+ // Therefore, subtract 2 to check the Operator.
+ //
+ Operation = DsdtPointer - 2;
+ if (*Operation == AML_METHOD_OP) {
+
+ //
+ // Check if we want _TSP enabled
+ //
+ if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'T', 'S', 'P');
+ }
+ }
+ break;
+
+ //
+ // Update SS3 Name with Setup value
+ //
+ case (SIGNATURE_32 ('S', 'S', '3', '_')):
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+ Value = (UINT8 *) DsdtPointer + 4;
+ *Value = PcdGet8 (PcdAcpiSleepState);
+ }
+ break;
+ //
+ // Update SS4 Name with Setup value
+ //
+ case (SIGNATURE_32 ('S', 'S', '4', '_')):
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_NAME_OP) {
+ Value = (UINT8 *) DsdtPointer + 4;
+ *Value = PcdGet8 (PcdAcpiHibernate);
+ }
+ break;
+ //
+ // _EJ0 method
+ //
+ case (SIGNATURE_32 ('_', 'E', 'J', '0')):
+ if (PcdGet8 (PcdLowPowerS0Idle)) {
+ //
+ // Remove _EJ0 for SOC
+ //
+ if (*(DsdtPointer-3) == AML_METHOD_OP) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'E', 'J', '0');
+ EnterDock = TRUE;
+ }
+ }
+ break;
+ //
+ // _STA method for Device (\_SB.PCI0.DOCK)
+ //
+ case (SIGNATURE_32 ('_', 'S', 'T', 'A')):
+ if (PcdGet8 (PcdLowPowerS0Idle)) {
+ //
+ // Remove _STA in (\_SB.PCI0.DOCK) for SOC
+ //
+ if ((*(DsdtPointer-3) == AML_METHOD_OP) && (EnterDock)) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'S', 'T', 'A');
+ EnterDock = FALSE;
+ }
+ }
+ break;
+ //
+ // _UPC method for Device (\_SB.PCI0.XHC.RHUB)
+ //
+ case (SIGNATURE_32('H', 'S', '1', '3')):
+ for (TmpDsdtPointer = DsdtPointer;
+ TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength;
+ TmpDsdtPointer++){
+ Signature = (UINT32 *) TmpDsdtPointer;
+ switch (*Signature) {
+ case(SIGNATURE_32('U', 'P', 'C', 'P')):
+ Value = (UINT8 *)((UINT32 *)TmpDsdtPointer + 2);
+ break;
+ default:
+ //
+ // Do nothing.
+ //
+ break;
+ }
+ }
+ break;
+
+
+ //
+ // _DCK method
+ //
+ case (SIGNATURE_32 ('_', 'D', 'C', 'K')):
+ if (PcdGet8 (PcdLowPowerS0Idle)) {
+ //
+ // Remove _DCK for SOC
+ //
+ if (*(DsdtPointer-3) == AML_METHOD_OP) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'D', 'C', 'K');
+ }
+ }
+ break;
+
+ //
+ // mask _DEP from CPU's scope if CS disabled.
+ //
+ case (SIGNATURE_32 ('P', 'R', '0', '0')):
+ case (SIGNATURE_32 ('P', 'R', '0', '1')):
+ case (SIGNATURE_32 ('P', 'R', '0', '2')):
+ case (SIGNATURE_32 ('P', 'R', '0', '3')):
+ case (SIGNATURE_32 ('P', 'R', '0', '4')):
+ case (SIGNATURE_32 ('P', 'R', '0', '5')):
+ case (SIGNATURE_32 ('P', 'R', '0', '6')):
+ case (SIGNATURE_32 ('P', 'R', '0', '7')):
+ case (SIGNATURE_32 ('P', 'R', '0', '8')):
+ case (SIGNATURE_32 ('P', 'R', '0', '9')):
+ case (SIGNATURE_32 ('P', 'R', '1', '0')):
+ case (SIGNATURE_32 ('P', 'R', '1', '1')):
+ case (SIGNATURE_32 ('P', 'R', '1', '2')):
+ case (SIGNATURE_32 ('P', 'R', '1', '3')):
+ case (SIGNATURE_32 ('P', 'R', '1', '4')):
+ case (SIGNATURE_32 ('P', 'R', '1', '5')):
+
+ if (PcdGet8 (PcdLowPowerS0Idle) == 0) {
+ for (TmpDsdtPointer = DsdtPointer; TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength; TmpDsdtPointer++){
+ Signature = (UINT32 *) TmpDsdtPointer;
+ switch (*Signature) {
+ case(SIGNATURE_32('_', 'D', 'E', 'P')):
+ *(UINT8 *) TmpDsdtPointer = 'X';
+ break;
+ default:
+ //
+ // Do nothing.
+ //
+ break;
+ }
+ }
+ }
+ break;
+
+ //
+ // _EDL name
+ //
+ case (SIGNATURE_32 ('_', 'E', 'D', 'L')):
+ if (PcdGet8 (PcdLowPowerS0Idle)) {
+ //
+ // Remove _EDL for SOC
+ //
+ if (*(DsdtPointer-1) == AML_NAME_OP) {
+ Signature = (UINT32 *) DsdtPointer;
+ *Signature = SIGNATURE_32 ('X', 'E', 'D', 'L');
+ }
+ }
+ break;
+
+ default:
+ //
+ // Do nothing.
+ //
+ break;
+ }
+ }
+}
+
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