Enable MinPlatformPkg to boot with EDK2 platform. Validated on an open server platform.

1)	MinPlatform.dec
a)	Add PcdFspWrapperBootMode to control different behavior in FSP wrapper mode and EDKII mode (by PlatformInitPei)
b)	Add gPeiBaseMemoryTestPpiGuid and gPeiPlatformMemorySizePpiGuid – they are used for EDKII boot mode.
c)	Rename MADT related PCD for server (PcdLocalApicAddress/PcdLocalApicMmioSize/PcdIoApicAddress/PcdIoApicMmioSize/PcdIoApicId)
d)	Add MADT related PCD for multi IO APIC for server (PcdPcIoApicCount/PcdPcIoApicIdBase/PcdPcIoApicAddressBase/PcdPcIoApicInterruptBase)
e)	Add HPET related PCD (PcdHpetTimerBlockId)
f)	Add FADT related PCD (PcdFadtPreferredPmProfile/PcdFadtIaPcBootArch/PcdFadtFlags)
g)	Add PCD for DXE Silicon module flash address (PcdFlashFvFspUBase/PcdFlashFvFspUSize/PcdFlashFvFspUOffset)
h)	Make Flash Address PCD to be patchable, so that it can be updated in binary FV.
2)	Include
a)	DSC/FDF: Do not always include the module, which might be from silicon code, such as SEC/CpuDxe/SmmCpu/PciHostBridge.
b)	DSC/FDF: UiApp.inf – fix a bug that UIAPP does not have boot manager.
c)	DSC/FDF: DP.inf – sync to latest performance dump tool in ShellPkg.
3)	Update AcpiPlatform for server platform
a)	Construct MADT from scratch.
b)	Construct MCFG from scratch.
4)	CompressLib
a)	Add CompressLib class and instance so that MRC data can be compressed.
5)	PlatformInitPei
a)	Produce BaseMemoryTestPpi and PlatformMemorySizePpi in EDKII boot mode.
b)	Install FV in FSPM/FSPS/FSPU in EDKII boot mode.
c)	Move SecurityFv/AdvancedFv installation from SEC to PlatformInitPei.
d)	Remove BuildFvHob for flash region – it is a bug.
e)	Mark above 4GiB MMIO to be uncatchable.
6)	PciSegmentInfoLib
a)	Handle the case that the lib is linked by a DXE module only.
7)	PlatformSecLib
a)	Move SecurityFv/AdvancedFv installation from SEC to PlatformInitPei.
8)	SpiFvbService
a)	Do not use fixed PCD, so that the address can be patchable.
9)	TestPoint
a)	Enhance the logic to check if a memory is in save state area or not. (Support PcdCpuHotPlugSupport)
10)	Add python tool
a)	AmlGenOffset.py – generate ACPI patch table.
b)	ParseVar.py – parse the VarBin generated by FCE tool and output PCD value.
c)	PatchFv/PatchBfv.py – patch the BFV address in ResetVector.bin
d)	PatchFv/PatchBinFv.py – patch patchable PCD in a given FV according to build report.
e)	PatchFv/RebaseBinFv.py – rebase a given FV to a new address.
f)	PatchFv/SyncBinFvInf.py – generate INF for a binary FV.

Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Brett Wang <brett.wang@intel.com>
Cc: Daocheng Bu <daocheng.bu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>

1 files changed, 147 insertions, 4 deletions

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
index 0eb1328332..0def9f6c2b 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
@@ -17,8 +17,151 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //

 // Statements that include other files

 //

+#include <IndustryStandard/Acpi.h>

 

-#include "Fadt.h"

+//

+// FADT Definitions

+//

+#define EFI_ACPI_OEM_FADT_REVISION  0x00000000

+

+#define EFI_ACPI_PREFERRED_PM_PROFILE 0x00 // To be fixed

+

+#define EFI_ACPI_SCI_INT              0x0009

+#define EFI_ACPI_SMI_CMD              0x000000B2

+

+#define EFI_ACPI_ACPI_ENABLE          0 // To be fixed

+#define EFI_ACPI_ACPI_DISABLE         0 // To be fixed

+#define EFI_ACPI_S4_BIOS_REQ          0x00

+#define EFI_ACPI_CST_CNT              0x00

+

+#define EFI_ACPI_PSTATE_CNT           0x00

+#define EFI_ACPI_GPE1_BASE            (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 2)

+#define EFI_ACPI_P_LVL2_LAT           0x0065 // 101

+#define EFI_ACPI_P_LVL3_LAT           0x03E9 // 1001

+#define EFI_ACPI_FLUSH_SIZE 0x0000

+#define EFI_ACPI_FLUSH_STRIDE 0x0000

+#define EFI_ACPI_DUTY_OFFSET  0x01

+#define EFI_ACPI_DUTY_WIDTH 0x00

+

+#define EFI_ACPI_DAY_ALRM   0x0D

+#define EFI_ACPI_MON_ALRM   0x00

+#define EFI_ACPI_CENTURY    0x32

+

+//

+// IA-PC Boot Architecture Flags

+//

+

+#define EFI_ACPI_IAPC_BOOT_ARCH         0 // To be fixed

+

+//

+// Fixed Feature Flags

+//

+#define EFI_ACPI_FIXED_FEATURE_FLAGS    0 // To be fixed

+

+//

+// PM1A Event Register Block Generic Address Information

+//

+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH         0x20

+#define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET        0x00

+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS           0 // To be fixed

+

+//

+// PM1B Event Register Block Generic Address Information

+//

+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH         0x00

+#define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET        0x00

+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS           0 // To be fixed

+

+//

+// PM1A Control Register Block Generic Address Information

+//

+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH         0x10

+#define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET        0x00

+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS           0 // To be fixed

+

+//

+// PM1B Control Register Block Generic Address Information

+//

+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH         0x00

+#define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET        0x00

+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS           0 // To be fixed

+

+//

+// PM2 Control Register Block Generic Address Information

+//

+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH        0x08

+#define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET       0x00

+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS          0 // To be fixed

+

+//

+// Power Management Timer Control Register Block Generic Address

+// Information

+//

+#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH         0x20

+#define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET        0x00

+#define EFI_ACPI_PM_TMR_BLK_ADDRESS           0 // To be fixed

+

+//

+// General Purpose Event 0 Register Block Generic Address

+// Information

+//

+#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_GPE0_BLK_BIT_WIDTH         0  // size of R_PCH_ACPI_GPE0_STS_127_96 + R_PCH_ACPI_GPE0_EN_127_96

+#define EFI_ACPI_GPE0_BLK_BIT_OFFSET        0x00

+#define EFI_ACPI_GPE0_BLK_ADDRESS           0 // To be fixed

+

+//

+// General Purpose Event 1 Register Block Generic Address

+// Information

+//

+#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_GPE1_BLK_BIT_WIDTH         0x0

+#define EFI_ACPI_GPE1_BLK_BIT_OFFSET        0x0

+#define EFI_ACPI_GPE1_BLK_ADDRESS           0 // To be fixed

+//

+// Reset Register Generic Address Information

+//

+#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO

+#define EFI_ACPI_RESET_REG_BIT_WIDTH        0x08

+#define EFI_ACPI_RESET_REG_BIT_OFFSET       0x00

+#define EFI_ACPI_RESET_REG_ADDRESS          0x00000CF9

+#define EFI_ACPI_RESET_VALUE                0x06

+

+//

+// Number of bytes decoded by PM1 event blocks (a and b)

+//

+#define EFI_ACPI_PM1_EVT_LEN  ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)

+

+//

+// Number of bytes decoded by PM1 control blocks (a and b)

+//

+#define EFI_ACPI_PM1_CNT_LEN  ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)

+

+//

+// Number of bytes decoded by PM2 control block

+//

+#define EFI_ACPI_PM2_CNT_LEN  (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH / 8)

+

+//

+// Number of bytes decoded by PM timer block

+//

+#define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8)

+

+//

+// Number of bytes decoded by GPE0 block

+//

+#define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8)

+

+//

+// Number of bytes decoded by GPE1 block

+//

+#define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8)

 

 //

 // Fixed ACPI Description Table

@@ -57,8 +200,8 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
   EFI_ACPI_PREFERRED_PM_PROFILE,

   EFI_ACPI_SCI_INT,

   EFI_ACPI_SMI_CMD,

-  FixedPcdGet8 (PcdAcpiEnableSwSmi),

-  FixedPcdGet8 (PcdAcpiDisableSwSmi),

+  EFI_ACPI_ACPI_ENABLE,

+  EFI_ACPI_ACPI_DISABLE,

   EFI_ACPI_S4_BIOS_REQ,

   EFI_ACPI_PSTATE_CNT,

   

@@ -184,7 +327,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
     // X_General Purpose Event 0 Register Block

     //

     EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID,

-    0x0,

+    EFI_ACPI_GPE0_BLK_BIT_WIDTH,

     EFI_ACPI_GPE0_BLK_BIT_OFFSET,

     EFI_ACPI_5_0_BYTE,

     EFI_ACPI_GPE0_BLK_ADDRESS