Enable MinPlatformPkg to boot with EDK2 platform. Validated on an open server platform.

1)	MinPlatform.dec
a)	Add PcdFspWrapperBootMode to control different behavior in FSP wrapper mode and EDKII mode (by PlatformInitPei)
b)	Add gPeiBaseMemoryTestPpiGuid and gPeiPlatformMemorySizePpiGuid – they are used for EDKII boot mode.
c)	Rename MADT related PCD for server (PcdLocalApicAddress/PcdLocalApicMmioSize/PcdIoApicAddress/PcdIoApicMmioSize/PcdIoApicId)
d)	Add MADT related PCD for multi IO APIC for server (PcdPcIoApicCount/PcdPcIoApicIdBase/PcdPcIoApicAddressBase/PcdPcIoApicInterruptBase)
e)	Add HPET related PCD (PcdHpetTimerBlockId)
f)	Add FADT related PCD (PcdFadtPreferredPmProfile/PcdFadtIaPcBootArch/PcdFadtFlags)
g)	Add PCD for DXE Silicon module flash address (PcdFlashFvFspUBase/PcdFlashFvFspUSize/PcdFlashFvFspUOffset)
h)	Make Flash Address PCD to be patchable, so that it can be updated in binary FV.
2)	Include
a)	DSC/FDF: Do not always include the module, which might be from silicon code, such as SEC/CpuDxe/SmmCpu/PciHostBridge.
b)	DSC/FDF: UiApp.inf – fix a bug that UIAPP does not have boot manager.
c)	DSC/FDF: DP.inf – sync to latest performance dump tool in ShellPkg.
3)	Update AcpiPlatform for server platform
a)	Construct MADT from scratch.
b)	Construct MCFG from scratch.
4)	CompressLib
a)	Add CompressLib class and instance so that MRC data can be compressed.
5)	PlatformInitPei
a)	Produce BaseMemoryTestPpi and PlatformMemorySizePpi in EDKII boot mode.
b)	Install FV in FSPM/FSPS/FSPU in EDKII boot mode.
c)	Move SecurityFv/AdvancedFv installation from SEC to PlatformInitPei.
d)	Remove BuildFvHob for flash region – it is a bug.
e)	Mark above 4GiB MMIO to be uncatchable.
6)	PciSegmentInfoLib
a)	Handle the case that the lib is linked by a DXE module only.
7)	PlatformSecLib
a)	Move SecurityFv/AdvancedFv installation from SEC to PlatformInitPei.
8)	SpiFvbService
a)	Do not use fixed PCD, so that the address can be patchable.
9)	TestPoint
a)	Enhance the logic to check if a memory is in save state area or not. (Support PcdCpuHotPlugSupport)
10)	Add python tool
a)	AmlGenOffset.py – generate ACPI patch table.
b)	ParseVar.py – parse the VarBin generated by FCE tool and output PCD value.
c)	PatchFv/PatchBfv.py – patch the BFV address in ResetVector.bin
d)	PatchFv/PatchBinFv.py – patch patchable PCD in a given FV according to build report.
e)	PatchFv/RebaseBinFv.py – rebase a given FV to a new address.
f)	PatchFv/SyncBinFvInf.py – generate INF for a binary FV.

Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Brett Wang <brett.wang@intel.com>
Cc: Daocheng Bu <daocheng.bu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>

1 files changed, 51 insertions, 0 deletions

diff --git a/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformMemorySize.h b/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformMemorySize.h
new file mode 100644
index 0000000000..f90c4672f8
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformMemorySize.h
@@ -0,0 +1,51 @@
+//

+// This file contains 'Framework Code' and is licensed as such 

+// under the terms of your license agreement with Intel or your

+// vendor.  This file may not be modified, except as allowed by

+// additional terms of your license agreement.                 

+//

+/**

+

+Copyright (c)  1999 - 2003 Intel Corporation. All rights reserved

+This software and associated documentation (if any) is furnished

+under a license and may only be used or copied in accordance

+with the terms of the license. Except as permitted by such

+license, no part of this software or documentation may be

+reproduced, stored in a retrieval system, or transmitted in any

+form or by any means without the express written consent of

+Intel Corporation.

+

+  @file PlatformMemorySize.h

+

+  Platform Memory Size PPI as defined in Tiano

+

+  PPI for describing the minimum platform memory size in order to successfully

+  pass control into DXE

+

+**/

+

+#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_

+#define _PEI_PLATFORM_MEMORY_SIZE_H_

+

+#define PEI_PLATFORM_MEMORY_SIZE_PPI_GUID \

+  { \

+    0x9a7ef41e, 0xc140, 0x4bd1, {0xb8, 0x84, 0x1e, 0x11, 0x24, 0xb, 0x4c, 0xe6 } \

+  }

+

+typedef struct _PEI_PLATFORM_MEMORY_SIZE_PPI PEI_PLATFORM_MEMORY_SIZE_PPI;

+

+typedef

+EFI_STATUS

+(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) (

+  IN      EFI_PEI_SERVICES                       **PeiServices,

+  IN PEI_PLATFORM_MEMORY_SIZE_PPI                * This,

+  IN OUT  UINT64                                 *MemorySize

+  );

+

+typedef struct _PEI_PLATFORM_MEMORY_SIZE_PPI {

+  PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE  GetPlatformMemorySize;

+} PEI_PLATFORM_MEMORY_SIZE_PPI;

+

+extern EFI_GUID gPeiPlatformMemorySizePpiGuid;

+

+#endif