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authorJiewen Yao <jiewen.yao@intel.com>2018-03-17 07:41:44 +0800
committerJiewen Yao <jiewen.yao@intel.com>2018-03-17 07:41:44 +0800
commit8b2982cd59533486c31f6effae45cdf7899209b8 (patch)
treef75a13afd7c10e6fd86fc15771519e8785db8123 /Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c
parent5c164e151c4047efc32f2bd0d6cad730e635c23c (diff)
downloadedk2-platforms-8b2982cd59533486c31f6effae45cdf7899209b8.tar.xz
PurleyOpenBoardPkg: Initial version.
Cc: Isaac W Oram <isaac.w.oram@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Isaac W Oram <isaac.w.oram@intel.com>
Diffstat (limited to 'Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c')
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diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c
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+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/PcdLib.h>
+#include <PchLimits.h>
+#include <PchPolicyCommon.h>
+
+PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ PchUsbOverCurrentPinSkip, //1 BMC,skip
+ PchUsbOverCurrentPinSkip, //2 BMC,skip
+ PchUsbOverCurrentPin0, //3 USB REAR PANEL, OC0
+ PchUsbOverCurrentPin1, //4 USB REAR PANEL, OC1
+ PchUsbOverCurrentPin1, //5 USB REAR PANEL, OC1
+ PchUsbOverCurrentPinSkip, //6 Internal USB3.0, NC, skip(org OC2 in schematic)
+ PchUsbOverCurrentPinSkip, //7 NC, skip
+ PchUsbOverCurrentPin4, //8 Internal USB2.0, OC4
+ PchUsbOverCurrentPinSkip, //9 NC, skip
+ PchUsbOverCurrentPinSkip, //10 NC, skip
+ PchUsbOverCurrentPin6, //11 USB FRONT PANEL, OC6
+ PchUsbOverCurrentPin5, //12 USB STORAGE FRONT PANNEL, OC5
+ PchUsbOverCurrentPin6, //13 USB FRONT PANEL, OC6
+ PchUsbOverCurrentPin5, //14 USB STORAGE FRONT PANNEL, OC5
+ PchUsbOverCurrentPinSkip,
+ PchUsbOverCurrentPinSkip
+ };
+
+PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ PchUsbOverCurrentPin6, //1 USB FRONT PANEL, OC6
+ PchUsbOverCurrentPin6, //2 USB FRONT PANEL, OC6
+ PchUsbOverCurrentPin0, //3 USB REAR PANEL, OC0
+ PchUsbOverCurrentPin1, //4 USB REAR PANEL, OC1
+ PchUsbOverCurrentPin1, //5 USB REAR PANEL, OC1
+ PchUsbOverCurrentPinSkip, //6 Internal USB3.0, NC, skip(org OC2 in schematic)
+ PchUsbOverCurrentPinSkip,
+ PchUsbOverCurrentPinSkip,
+ PchUsbOverCurrentPinSkip,
+ PchUsbOverCurrentPinSkip
+ };
+