Marvell: Reorganize file structure

In edk2-platforms it is expected to provide a separation between
SoC and boards files in 'Silicon' and 'Platform' directories
accordingly.

This patch aligns Marvell code to this requirement with no functional
changes in the actual source files, unless required due to modified
paths. Change the supported board's files names to proper Armada70x0Db.

Also rename 'Armada' directory to 'Armada7k8k' in order to properly
refer to the SoC family and prevent confusion in future, when
adding new Armada machines. On the occasion add ARM copyright,
which was wrongly missing in the dsc.inc file.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

2 files changed, 450 insertions, 0 deletions

diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
new file mode 100644
index 0000000000..46a1ea94f7
--- /dev/null
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -0,0 +1,137 @@
+#Copyright (C) 2016 Marvell International Ltd.

+#

+#Marvell BSD License Option

+#

+#If you received this File from Marvell, you may opt to use, redistribute and/or

+#modify this File under the following licensing terms.

+#Redistribution and use in source and binary forms, with or without modification,

+#are permitted provided that the following conditions are met:

+#

+# * Redistributions of source code must retain the above copyright notice,

+# this list of conditions and the following disclaimer.

+#

+# * Redistributions in binary form must reproduce the above copyright

+# notice, this list of conditions and the following disclaimer in the

+# documentation and/or other materials provided with the distribution.

+#

+# * Neither the name of Marvell nor the names of its contributors may be

+# used to endorse or promote products derived from this software without

+# specific prior written permission.

+#

+#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND

+#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

+#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR

+#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

+#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON

+#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

+#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

+#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+#

+################################################################################

+#

+# Defines Section - statements that will be processed to create a Makefile.

+#

+################################################################################

+[Defines]

+  PLATFORM_NAME                  = Armada70x0Db

+  PLATFORM_GUID                  = f837e231-cfc7-4f56-9a0f-5b218d746ae3

+  PLATFORM_VERSION               = 0.1

+  DSC_SPECIFICATION              = 0x00010005

+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)-$(ARCH)

+  SUPPORTED_ARCHITECTURES        = AARCH64|ARM

+  BUILD_TARGETS                  = DEBUG|RELEASE

+  SKUID_IDENTIFIER               = DEFAULT

+  FLASH_DEFINITION               = Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf

+

+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc

+

+################################################################################

+#

+# Pcd Section - list of all EDK II PCD Entries defined by this Platform

+#

+################################################################################

+[PcdsFixedAtBuild.common]

+  #MPP

+  gMarvellTokenSpaceGuid.PcdMppChipCount|2

+

+  # APN806-A0 MPP SET

+  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE

+  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000

+  gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20

+  gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }

+  gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }

+

+  # CP110 MPP SET - Router configuration

+  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE

+  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000

+  gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64

+  gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 }

+  gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA }

+  gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 }

+  gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }

+  gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }

+  gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }

+

+  # I2C

+  gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60 }

+  gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 }

+  gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 }

+  gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000

+  gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000

+  gMarvellTokenSpaceGuid.PcdI2cBusCount|2

+

+  #SPI

+  gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680

+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000

+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000

+

+  gMarvellTokenSpaceGuid.PcdSpiFlashMode|3

+  gMarvellTokenSpaceGuid.PcdSpiFlashCs|0

+

+  #ComPhy

+  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }

+  # ComPhy0

+  # 0: SGMII1        1.25 Gbps

+  # 1: USB3_HOST0    5 Gbps

+  # 2: SFI           10.31 Gbps

+  # 3: SATA1         5 Gbps

+  # 4: USB3_HOST1    5 Gbps

+  # 5: PCIE2         5 Gbps

+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }

+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }

+

+  #UtmiPhy

+  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }

+  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }

+

+  #MDIO

+  gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }

+

+  #PHY

+  gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }

+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE

+

+  #NET

+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }

+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }

+  gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMII), $(PHY_RGMII) }

+  gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }

+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }

+  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }

+

+  #PciEmulation

+  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 }

+  gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }

+

+  #RTC

+  gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 }

diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
new file mode 100644
index 0000000000..f63f42d89f
--- /dev/null
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
@@ -0,0 +1,313 @@
+#

+#  Copyright (C) Marvell International Ltd. and its affiliates

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution.  The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+

+################################################################################

+#

+# FD Section

+# The [FD] Section is made up of the definition statements and a

+# description of what goes into  the Flash Device Image.  Each FD section

+# defines one flash "device" image.  A flash device image may be one of

+# the following: Removable media bootable image (like a boot floppy

+# image,) an Option ROM image (that would be "flashed" into an add-in

+# card,) a System "Flash"  image (that would be burned into a system's

+# flash) or an Update ("Capsule") image that will be used to update and

+# existing system flash.

+#

+################################################################################

+

+[FD.Armada70x0_EFI]

+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.

+Size          = 0x00400000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device

+ErasePolarity = 1

+

+# This one is tricky, it must be: BlockSize * NumBlocks = Size

+BlockSize     = 0x00001000

+NumBlocks     = 0x400

+

+################################################################################

+#

+# Following are lists of FD Region layout which correspond to the locations of different

+# images within the flash device.

+#

+# Regions must be defined in ascending order and may not overlap.

+#

+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by

+# the pipe "|" character, followed by the size of the region, also in hex with the leading

+# "0x" characters. Like:

+# Offset|Size

+# PcdOffsetCName|PcdSizeCName

+# RegionType <FV, DATA, or FILE>

+#

+################################################################################

+

+0x00000000|0x00100000

+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize

+FV = FVMAIN_COMPACT

+

+

+################################################################################

+#

+# FV Section

+#

+# [FV] section is used to define what components or modules are placed within a flash

+# device file.  This section also defines order the components and modules are positioned

+# within the image.  The [FV] section consists of define statements, set statements and

+# module statements.

+#

+################################################################################

+

+# DXE phase firmware volume

+[FV.FvMain]

+BlockSize          = 0x40

+NumBlocks          = 0         # This FV gets compressed so make it just big enough

+FvAlignment        = 8         # FV alignment and FV attributes setting.

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c

+

+  INF MdeModulePkg/Core/Dxe/DxeMain.inf

+

+  #

+  # Platform Initialization

+  #

+  INF Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf

+

+  # PI DXE Drivers producing Architectural Protocols (EFI Services)

+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf

+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf

+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf

+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf

+  INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf

+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf

+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf

+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf

+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf

+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf

+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf

+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf

+  INF Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf

+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf

+  INF Silicon/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf

+  INF Silicon/Marvell/Drivers/Spi/MvSpiDxe.inf

+  INF Silicon/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf

+  INF Silicon/Marvell/Armada7k8k/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf

+

+  # Variable services

+  INF Silicon/Marvell/Drivers/Spi/Variables/MvFvbDxe.inf

+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf

+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf

+

+  # Network support

+  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf

+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf

+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf

+  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf

+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf

+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf

+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf

+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf

+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf

+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf

+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf

+  INF Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf

+  INF Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf

+  INF Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf

+

+  # PciEmulation

+  INF Silicon/Marvell/PciEmulation/PciEmulation.inf

+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf

+

+  # SCSI

+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf

+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf

+

+  # SATA

+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf

+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf

+  INF OvmfPkg/SataControllerDxe/SataControllerDxe.inf

+

+  # USB

+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf

+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf

+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf

+

+  # SD/MMC

+  INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf

+  INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf

+  INF Silicon/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf

+

+  # Multiple Console IO support

+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf

+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf

+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf

+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf

+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

+

+  # Human interface

+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

+

+  # FAT filesystem + GPT/MBR partitioning

+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf

+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf

+  INF FatBinPkg/EnhancedFatDxe/Fat.inf

+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf

+

+  # UEFI application (Shell Embedded Boot Loader)

+  INF ShellPkg/Application/Shell/Shell.inf

+!ifdef $(INCLUDE_TFTP_COMMAND)

+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf

+!endif #$(INCLUDE_TFTP_COMMAND)

+

+  # Bds

+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf

+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf

+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf

+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

+  INF MdeModulePkg/Application/UiApp/UiApp.inf

+

+

+# PEI phase firmware volume

+[FV.FVMAIN_COMPACT]

+FvAlignment        = 8

+FvForceRebase      = TRUE

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+

+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf

+

+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {

+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

+      SECTION FV_IMAGE = FVMAIN

+    }

+  }

+

+################################################################################

+#

+# Rules are use with the [FV] section's module INF type to define

+# how an FFS file is created for a given INF file. The following Rule are the default

+# rules for the different module type. User can add the customized rules to define the

+# content of the FFS file.

+#

+################################################################################

+

+

+############################################################################

+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #

+############################################################################

+#

+#[Rule.Common.DXE_DRIVER]

+#  FILE DRIVER = $(NAMED_GUID) {

+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex

+#    COMPRESS PI_STD {

+#      GUIDED {

+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi

+#        UI       STRING="$(MODULE_NAME)" Optional

+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+#      }

+#    }

+#  }

+#

+############################################################################

+

+[Rule.Common.SEC]

+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {

+    TE  TE    Align = Auto              $(INF_OUTPUT)/$(MODULE_NAME).efi

+  }

+

+[Rule.Common.PEI_CORE]

+  FILE PEI_CORE = $(NAMED_GUID) {

+    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI     STRING ="$(MODULE_NAME)" Optional

+  }

+

+[Rule.Common.PEIM]

+  FILE PEIM = $(NAMED_GUID) {

+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex

+     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi

+     UI       STRING="$(MODULE_NAME)" Optional

+  }

+

+[Rule.Common.PEIM.TIANOCOMPRESSED]

+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {

+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex

+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {

+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi

+      UI        STRING="$(MODULE_NAME)" Optional

+    }

+  }

+

+[Rule.Common.DXE_CORE]

+  FILE DXE_CORE = $(NAMED_GUID) {

+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI       STRING="$(MODULE_NAME)" Optional

+  }

+

+[Rule.Common.UEFI_DRIVER]

+  FILE DRIVER = $(NAMED_GUID) {

+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex

+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI           STRING="$(MODULE_NAME)" Optional

+  }

+

+[Rule.Common.UEFI_DRIVER.BINARY]

+  FILE DRIVER = $(NAMED_GUID) {

+    DXE_DEPEX DXE_DEPEX Optional      |.depex

+    PE32      PE32                    |.efi

+    UI        STRING="$(MODULE_NAME)" Optional

+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.DXE_DRIVER]

+  FILE DRIVER = $(NAMED_GUID) {

+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex

+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI           STRING="$(MODULE_NAME)" Optional

+  }

+

+[Rule.Common.DXE_RUNTIME_DRIVER]

+  FILE DRIVER = $(NAMED_GUID) {

+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex

+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI           STRING="$(MODULE_NAME)" Optional

+  }

+

+[Rule.Common.UEFI_APPLICATION]

+  FILE APPLICATION = $(NAMED_GUID) {

+    UI     STRING ="$(MODULE_NAME)" Optional

+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi

+  }