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| author | Leif Lindholm <leif.lindholm@linaro.org> | 2017-05-03 17:47:23 +0100 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-07-14 22:36:51 +0100 |
| commit | 0189ff331b9bdd9353624bc7b509e53148976806 (patch) | |
| tree | 481788a26d43fdad9f762256111ece2926b7835a /Platform/Marvell/Documentation/PortingGuide/ComPhy.txt | |
| parent | 8322634459ac602d9fbcca30e96b24ff098acb3c (diff) | |
| download | edk2-platforms-0189ff331b9bdd9353624bc7b509e53148976806.tar.xz | |
Platform: import Marvell Armada supportdevel-OpenPlatformPkg
Import Armada 70x0 suppport from OpenPlatformPkg,
together with its documentation and utilities.
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/Marvell/Documentation/PortingGuide/ComPhy.txt')
| -rw-r--r-- | Platform/Marvell/Documentation/PortingGuide/ComPhy.txt | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt b/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt new file mode 100644 index 0000000000..a96015e152 --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt @@ -0,0 +1,45 @@ +COMPHY configuration
+---------------------------
+In order to configure ComPhy library, following PCDs are available:
+
+ gMarvellTokenSpaceGuid.PcdComPhyDevices
+
+This array indicates, which ones of the ComPhy chips defined in
+MVHW_COMPHY_DESC template will be configured.
+
+Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
+important, but configuration will be set for first PcdComPhyChipCount chips).
+
+Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes
+settings for this chip. Their format is unicode string, containing settings
+for up to 10 lanes. Setting for each one is separated with semicolon.
+These PCDs together describe outputs of PHY integrated in simple cihp.
+Below is example for the first chip (Chip0).
+
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
+
+Unicode string indicating PHY types. Currently supported are:
+
+{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3",
+L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0",
+L"SGMII1", L"SGMII2", L"SGMII3",
+L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE",
+L"RXAUI0", L"RXAUI1", L"SFI" }
+
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
+
+Indicates PHY speeds in MHz. Currently supported are:
+
+{ 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 10310 }
+
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
+
+Indicates lane polarity invert.
+
+Example
+-------
+ #ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1;USB3_HOST1;PCIE2"
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;5000"
+
|