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| author | Leif Lindholm <leif.lindholm@linaro.org> | 2017-05-03 17:47:23 +0100 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-07-14 22:36:51 +0100 |
| commit | 0189ff331b9bdd9353624bc7b509e53148976806 (patch) | |
| tree | 481788a26d43fdad9f762256111ece2926b7835a /Platform/Marvell/Documentation/PortingGuide/Pp2.txt | |
| parent | 8322634459ac602d9fbcca30e96b24ff098acb3c (diff) | |
| download | edk2-platforms-0189ff331b9bdd9353624bc7b509e53148976806.tar.xz | |
Platform: import Marvell Armada supportdevel-OpenPlatformPkg
Import Armada 70x0 suppport from OpenPlatformPkg,
together with its documentation and utilities.
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/Marvell/Documentation/PortingGuide/Pp2.txt')
| -rw-r--r-- | Platform/Marvell/Documentation/PortingGuide/Pp2.txt | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt new file mode 100644 index 0000000000..c1554a694e --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt @@ -0,0 +1,59 @@ +Pp2Dxe porting guide
+--------------------
+Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
+are required to operate:
+
+Number of ports/network interfaces:
+ gMarvellTokenSpaceGuid.PcdPp2NumPorts
+
+Addresses of PHY devices:
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses
+
+Identificators of PP2 ports:
+ gMarvellTokenSpaceGuid.PcdPp2PortIds
+
+Indexes used in GOP operation:
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes
+
+Set to 0x1 for always-up interface, 0x0 otherwise:
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
+
+Values corresponding to PHY_SPEED enum:
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
+
+PHY_SPEED (in Mbps) is defined as follows:
+ typedef enum {
+ 0 NO_SPEED,
+ 1 SPEED_10,
+ 2 SPEED_100,
+ 3 SPEED_1000,
+ 4 SPEED_2500,
+ 5 SPEED_10000
+ } PHY_SPEED;
+
+Base address of shared register space of PP2:
+ gMarvellTokenSpaceGuid.PcdPp2SharedAddress
+
+Spacing between consecutive GMAC register spaces:
+ gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
+
+Base address of GMAC:
+ gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
+
+Spacing between consecutive XLG register spaces:
+ gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
+
+Base address of XLG:
+ gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
+
+Base address of RFU1:
+ gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
+
+Base address of SMI:
+ gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
+
+TCLK frequency in Hz:
+ gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
+
+GMAC and XLG addresses are computed as follows:
+ address = base_address + dev_size * gop_index
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