diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-08-24 20:43:57 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-08-31 14:41:24 +0100 |
| commit | bff9700855e43e4948fb4f7249b9a4fb5451072e (patch) | |
| tree | c5e4b2b328b3319df2e500c5b83c5a040ca8c928 /Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | |
| parent | 8b89ae57eec0d544827c6047860825603b78e3b8 (diff) | |
| download | edk2-platforms-bff9700855e43e4948fb4f7249b9a4fb5451072e.tar.xz | |
Platform/Armada/Pp2Dxe: switch to NonCoherentDmaLib
Instead of hardcoding the non-cache coherent nature of this device
by invoking UncachedMemoryAllocationLib directly for allocating
shared buffers, switch to DmaLib, which encapsulates this at a
more abstract level. This allows the driver to be shared with
platforms that are cache coherent (by simply switching to another
DmaLib implementation), and removes the hardcoded dependency on
UncachedMemoryAllocationLib, which will be removed from upstream
EDK2.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Marcin Wojtas <mw@semihalf.com>
Diffstat (limited to 'Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c')
| -rw-r--r-- | Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 35 |
1 files changed, 25 insertions, 10 deletions
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 8de2473d09..1e2ccd0dbe 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -175,9 +175,10 @@ Pp2DxeBmPoolInit ( VOID
)
{
- INTN Index;
- UINT8 *PoolAddr;
- UINT32 PoolSize = (sizeof(VOID *) * MVPP2_BM_SIZE) * 2 + MVPP2_BM_POOL_PTR_ALIGN;
+ INTN Index;
+ UINT8 *PoolAddr;
+ UINT32 PoolSize;
+ EFI_STATUS Status;
ASSERT(MVPP2_BM_POOL_PTR_ALIGN >= sizeof(UINTN));
@@ -194,11 +195,16 @@ Pp2DxeBmPoolInit ( return EFI_OUT_OF_RESOURCES;
}
- PoolAddr = UncachedAllocateAlignedZeroPool (PoolSize, MVPP2_BM_POOL_PTR_ALIGN);
- if (PoolAddr == NULL) {
- return EFI_OUT_OF_RESOURCES;
+ Status = DmaAllocateAlignedBuffer (EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (PoolSize),
+ MVPP2_BM_POOL_PTR_ALIGN,
+ (VOID **)&PoolAddr);
+ if (EFI_ERROR (Status)) {
+ goto FreePools;
}
+ ZeroMem (PoolAddr, PoolSize);
+
Mvpp2Shared->BmPools->Id = MVPP2_BM_POOL;
Mvpp2Shared->BmPools->VirtAddr = (UINT32 *)PoolAddr;
Mvpp2Shared->BmPools->PhysAddr = (UINTN)PoolAddr;
@@ -206,6 +212,10 @@ Pp2DxeBmPoolInit ( Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools, MVPP2_BM_SIZE);
return EFI_SUCCESS;
+
+FreePools:
+ FreePool (Mvpp2Shared->BmPools);
+ return Status;
}
/* Enable and fill BM pool */
@@ -1169,12 +1179,17 @@ Pp2DxeInitialise ( Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
/* Prepare buffers */
- BufferSpace = UncachedAllocateAlignedZeroPool (BD_SPACE, MVPP2_BUFFER_ALIGN_SIZE);
- if (BufferSpace == NULL) {
- DEBUG((DEBUG_ERROR, "Failed to allocate buffer space\n"));
- return EFI_OUT_OF_RESOURCES;
+ Status = DmaAllocateAlignedBuffer (EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (BD_SPACE),
+ MVPP2_BUFFER_ALIGN_SIZE,
+ &BufferSpace);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate buffer space\n"));
+ return Status;
}
+ ZeroMem (BufferSpace, BD_SPACE);
+
BufferLocation.TxDescs = BufferSpace;
BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)((UINTN)BufferSpace + MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC));
BufferLocation.RxDescs = (MVPP2_RX_DESC *)((UINTN)BufferSpace +
|