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authorMarcin Wojtas <mw@semihalf.com>2017-05-18 08:26:48 +0200
committerMarcin Wojtas <mw@semihalf.com>2017-10-05 16:58:06 +0200
commit5d3bc1fdd28bcc300adb1290aae9f5e0f71546e9 (patch)
tree083ae7d8b4188588c4e7bf975c4a9c92f731523b /Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h
parenta46a211fe350c74b095f3d83781d778912ac1491 (diff)
downloadedk2-platforms-5d3bc1fdd28bcc300adb1290aae9f5e0f71546e9.tar.xz
Marvell/Drivers: MvSpiFlash: Fix usage of erase size parameter
Although, hitherto support allowed for using configurable EraseSize, the erase command was fixed to CMD_ERASE_64K. Also it was assumed that EraseSize equals SectorSize, which is not true for some flash devices. Fix both issues by adding new PCD (gMarvellTokenSpaceGuid.PcdSpiFlashPageSize) and using this parameter properly in MvSpiFlashUpdate routine instead of the EraseSize. Also erase command is adjusted to the settings. Update PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h')
-rwxr-xr-xPlatform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h
index 3889643aeb..f90abb771e 100755
--- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h
+++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h
@@ -57,6 +57,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define CMD_READ_ARRAY_FAST 0x0b
#define CMD_PAGE_PROGRAM 0x02
#define CMD_BANK_WRITE 0xc5
+#define CMD_ERASE_4K 0x20
+#define CMD_ERASE_32K 0x52
#define CMD_ERASE_64K 0xd8
#define CMD_4B_ADDR_ENABLE 0xb7