Adjust FVs size and base.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>

4 files changed, 14 insertions, 10 deletions

diff --git a/Platform/BroxtonPlatformPkg/BuildBios.bat b/Platform/BroxtonPlatformPkg/BuildBios.bat
index 99a58cafd6..a326d3c640 100644
--- a/Platform/BroxtonPlatformPkg/BuildBios.bat
+++ b/Platform/BroxtonPlatformPkg/BuildBios.bat
@@ -404,8 +404,9 @@ copy /y/b %BUILD_PATH%\FV\FvOBBY.fv  %Storage_Folder% >nul
 

 if /i "%FSP_WRAPPER%" == "TRUE" (

   if %Stepping%==B (

+::  0xFEF63000 = gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase = $(CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EMP_DATA_SIZE) + $(BLD_IBBM_SIZE)

     pushd  %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin

-    python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f ApolloLakeFsp.fd -c m -b 0xFEF65000 -o .\ -n FSP.fd

+    python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f ApolloLakeFsp.fd -c m -b 0xFEF63000 -o .\ -n FSP.fd

     python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py split -f FSP.fd -o .\ -n FSP.Fv

     popd

     copy /y/b %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_T.Fv %Storage_Folder%\FSP_T.Fv

diff --git a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
index 1012a77421..326fade90d 100644
--- a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
+++ b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat
@@ -103,8 +103,9 @@ if /i "!Platform_Type!"=="MINN" (
 :: rd /s /q %BIOS_Names%  >>Stitching.log

 

 pushd %BIOS_Names%

-copy /y /b FVIBBM.fv+FSP_M.fv IBBM.Fv

-copy /y /b FSP_S.fv+FVIBBR.fv+FVOBB.Fv+FVOBBX.Fv+FVOBBY.Fv+NvStorage.Fv OBB2.Fv

+copy /y /b FVIBBL.Fv IBBL.Fv

+copy /y /b FVIBBM.fv+FSP_M.fv IBB.Fv

+copy /y /b FSP_S.fv+FVIBBR.fv+FVOBB.Fv+FVOBBX.Fv+FVOBBY.Fv OBB.Fv

 popd

 

 set IFWI_Name=!IFWI_Prefix!_%IFWI_Suffix%

@@ -113,19 +114,21 @@ echo.
 echo ------------------------------------------

 echo.

 echo   Generating SPI Image...

-

-copy /y /b %BIOS_Names%\IBBM.Fv .

-copy /y /b %BIOS_Names%\OBB2.Fv .

+mkdir BIOS_COMPONENTS

+copy /y /b %BIOS_Names%\IBBL.Fv .\BIOS_COMPONENTS

+copy /y /b %BIOS_Names%\IBB.Fv .\BIOS_COMPONENTS

+copy /y /b %BIOS_Names%\OBB.Fv .\BIOS_COMPONENTS

+copy /y /b %BIOS_Names%\NvStorage.Fv .\BIOS_COMPONENTS

 if %Stepping%==B (

   copy /y /b ..\..\Binaries\IFWI\B_Stepping\SpiChunk1.bin .

   copy /y /b ..\..\Binaries\IFWI\B_Stepping\SpiChunk2.bin .

   copy /y /b ..\..\Binaries\IFWI\B_Stepping\SpiChunk3.bin .

-  copy /y /b SpiChunk1.bin+IBBM.Fv+SpiChunk2.bin+OBB2.Fv+SpiChunk3.bin spi_out.bin

+  copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COMPONENTS\IBB.Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvStorage.Fv+SpiChunk3.bin spi_out.bin

   ) else (

   copy /y /b ..\..\Binaries\IFWI\A_Stepping\SpiChunk1.bin .

   copy /y /b ..\..\Binaries\IFWI\A_Stepping\SpiChunk2.bin .

   copy /y /b ..\..\Binaries\IFWI\A_Stepping\SpiChunk3.bin .

-  copy /y /b SpiChunk1.bin+IBBM.Fv+SpiChunk2.bin+OBB2.Fv+SpiChunk3.bin spi_out.bin

+  copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBB.Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvStorage.Fv+SpiChunk3.bin spi_out.bin

   )

 

 move /y spi_out.bin %BIOS_ID%.bin  >> Stitching.log

diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
index 173484db78..ad38d4424b 100644
--- a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
+++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc
@@ -152,7 +152,7 @@
     DEFINE FSP_IBBL_SIZE                   = 0x2000

     DEFINE BLD_IBBL_SIZE                   = 0x6000

     DEFINE FSP_IBBM_SIZE                   = 0x56000

-    DEFINE BLD_IBBM_SIZE                   = 0x20000

+    DEFINE BLD_IBBM_SIZE                   = 0x1E000

 

     DEFINE CAR_BASE_ADDRESS                = 0xFEF00000  # @PcdTemporaryRamBase

     DEFINE BLD_RAM_DATA_SIZE               = 0x16000     # BOOTLOADER temp memory size

diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
index c117245b23..81ca4cb054 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
@@ -75,7 +75,7 @@
   DEFINE FLASH_REGION_FV_IBBM_OFFSET                              = $(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET) + $(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE)

   DEFINE FLASH_REGION_FV_IBBL_SIZE                                = 0x00001000

 

-  DEFINE FLASH_REGION_FV_IBBM_SIZE                                = 0x00020000

+  DEFINE FLASH_REGION_FV_IBBM_SIZE                                = $(BLD_IBBM_SIZE)

   DEFINE FLASH_REGION_FV_IBBL_OFFSET                              = $(FLASH_SIZE) - $(FLASH_REGION_FV_IBBL_SIZE)

 

   DEFINE FLASH_FV_RECOVERY_BASE                                   = 0xFFF80000