diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-23 14:29:06 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:15:23 +0800 |
| commit | 8ab3a9adc8f2b56e865e6ad4f9900066a159ec00 (patch) | |
| tree | 311ff90dfcd021480498ea81b6beaf6824f190a0 /Platform | |
| parent | 275a7851a246bf0a86a66768b3fc0f4497d0425d (diff) | |
| download | edk2-platforms-8ab3a9adc8f2b56e865e6ad4f9900066a159ec00.tar.xz | |
BroxtonPlatformPkg: Add PlatformDxe
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Platform')
15 files changed, 3742 insertions, 0 deletions
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/AzaliaVerbTable.h b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/AzaliaVerbTable.h new file mode 100644 index 0000000000..21c0f85c80 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/AzaliaVerbTable.h @@ -0,0 +1,141 @@ +/** @file
+ Header file for Azalia Verb Table.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+UINT32 mHdaVerbTableData[] = {
+ //
+ // Rear Audio Verb Table - 10EC0880/0000/03
+ //
+ //
+ // Pin Complex 1 (NID 1Eh)
+ //
+ 0x01E71F01,
+ 0x01E71E44,
+ 0x01E71D21,
+ 0x01E71C00,
+
+ //
+ // Pin Complex 2 (NID 1Fh)
+ //
+ 0x01F71F01,
+ 0x01F71EC4,
+ 0x01F71D21,
+ 0x01F71C10,
+
+ //
+ // Pin Complex 3 (NID 14h)
+ //
+ 0x01471F01,
+ 0x01471E01,
+ 0x01471D40,
+ 0x01471C20,
+
+ //
+ // Pin Complex 4 (NID 15h)
+ //
+ 0x01571F01,
+ 0x01571E01,
+ 0x01571D40,
+ 0x01571C21,
+
+ //
+ // Pin Complex 5 (NID 16h)
+ //
+ 0x01671F01,
+ 0x01671E01,
+ 0x01671D90,
+ 0x01671C22,
+
+ //
+ // Pin Complex 6 (NID 17h)
+ //
+ 0x01771F01,
+ 0x01771E01,
+ 0x01771D30,
+ 0x01771C23,
+
+ //
+ // Pin Complex 7 (NID 1Ah)
+ //
+ 0x01A71F01,
+ 0x01A71E81,
+ 0x01A71D30,
+ 0x01A71C30,
+
+ //
+ // Pin Complex 8 (NID 18h)
+ //
+ 0x01871F01,
+ 0x01871EA1,
+ 0x01871D90,
+ 0x01871C31,
+
+ //
+ // Pin Complex 11 (NID 1Ch)
+ //
+ 0x01C71F99,
+ 0x01C71E33,
+ 0x01C71DF1,
+ 0x01C71C70,
+
+ //
+ // Pin Complex 12 (NID 1Dh)
+ //
+ 0x01D71F99,
+ 0x01D71EF3,
+ 0x01D71DF1,
+ 0x01D71C80,
+
+ //
+ // front panel
+ //
+
+ //
+ // Pin Complex 9 (NID 1Bh)
+ //
+ 0x01B71F02,
+ 0x01B71E21,
+ 0x01B71D40,
+ 0x01B71C50,
+
+ //
+ // Pin Complex 10 (NID 19h)
+ //
+ 0x01971F02,
+ 0x01971EA1,
+ 0x01971D90,
+ 0x01971C60
+ };
+
+SC_HDAUDIO_VERB_TABLE mHdaVerbTable[] = {
+ {
+ //
+ // VerbTable:
+ // Revision ID = 0xFF, support all steps
+ // Codec Verb Table For AZALIA
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0880
+ //
+ {
+ 0x10EC0880, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0xFF, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000A, // Number of Rear Jacks = 10
+ 0x0002 // Number of Front Jacks = 2
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ }
+};
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/ClockControl.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/ClockControl.c new file mode 100644 index 0000000000..c5117c083b --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/ClockControl.c @@ -0,0 +1,123 @@ +/** @file
+ Sets platform/SKU specific clock routing information.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include <Protocol/CK505ClockPlatformInfo.h>
+
+//
+// Default clock routing informtion (All On)
+//
+EFI_CLOCK_PLATFORM_INFO mDefClockPolicy = {NULL, 0, NULL, 0, NULL, 0};
+
+//
+// Clock Settings
+//
+// Static clock table.
+// This should be used to define any clock settings that are static
+// (Always On or Always Off). Dynamic clocks should be set to enabled
+// in this table.
+//
+EFI_STATIC_SIGNALS mAtxStaticClocks[] = {
+ {SrcClk8, Enabled, All},
+ {SrcClk7, Enabled, All},
+ {SrcClk6, Enabled, All},
+ {SrcClk5, Enabled, All},
+ {SrcClk4, Enabled, All},
+ {SrcClk3, Enabled, All},
+ {SrcClk2, Enabled, All},
+ {SrcClk1, Enabled, All},
+ {SrcClk0, Enabled, All},
+ {Ref0, Enabled, All},
+ {Dot96, Enabled, All},
+ {Usb48, Enabled, All},
+ {PciClkF5, Enabled, All},
+ {PciClk0, Enabled, All},
+ {PciClk2, Enabled, All},
+ {PciClk3, Enabled, All},
+ {PciClk4, Disabled, All},
+ {Cr_B, EnabledWithSwitch, All},
+};
+
+//
+// ClockSxInfo Table
+// This is a list of clocks that need to be set to a known state when the
+// system enters S4 or S5.
+//
+EFI_STATIC_SIGNALS mAtxSxClocks[] = {
+ {SaveClockConfiguration, Disabled, All}
+};
+
+//
+// ATX settings structure
+//
+EFI_CLOCK_PLATFORM_INFO mAtxClockSettings = {
+ mAtxStaticClocks,
+ sizeof (mAtxStaticClocks) / sizeof (mAtxStaticClocks[0]),
+ mAtxSxClocks,
+ sizeof (mAtxSxClocks) / sizeof (mAtxSxClocks[0])
+};
+
+
+VOID
+InitializeClockRouting(
+ )
+{
+ EFI_STATUS Status;
+ UINTN BoardIdVarSize;
+ EFI_BOARD_FEATURES BoardIdVar;
+ EFI_CLOCK_PLATFORM_INFO *ClockPolicy;
+ EFI_HANDLE Handle;
+
+ ClockPolicy = &mDefClockPolicy;
+
+ //
+ // Do modifications based on board type
+ //
+ BoardIdVarSize = sizeof (EFI_BOARD_FEATURES);
+ Status = gRT->GetVariable (
+ BOARD_FEATURES_NAME,
+ &gEfiBoardFeaturesGuid,
+ NULL,
+ &BoardIdVarSize,
+ &BoardIdVar
+ );
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Isolate board type information
+ //
+ BoardIdVar = BoardIdVar & (B_BOARD_FEATURES_FORM_FACTOR_ATX |
+ B_BOARD_FEATURES_FORM_FACTOR_BTX |
+ B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX |
+ B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX);
+
+ if (BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_ATX ||
+ BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX) {
+ ClockPolicy = &mAtxClockSettings;
+ }
+
+ }
+
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiCk505ClockPlatformInfoGuid,
+ EFI_NATIVE_INTERFACE,
+ ClockPolicy
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Configuration.h b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Configuration.h new file mode 100644 index 0000000000..4eaf3bf700 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Configuration.h @@ -0,0 +1,673 @@ +/** @file
+ Driver configuration include file.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CONFIGURATION_H
+#define _CONFIGURATION_H
+
+//
+// Processor labels
+//
+#define PROCESSOR_HT_MODE 0x0100
+#define PROCESSOR_FSB_MULTIPLIER 0x0101
+#define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL 0x0211
+
+//
+// Memory labels
+//
+#define MEMORY_SLOT1_SPEED 0x0200
+#define MEMORY_SLOT2_SPEED 0x0201
+#define MEMORY_SLOT3_SPEED 0x0202
+#define MEMORY_SLOT4_SPEED 0x0203
+#define END_MEMORY_SLOT_SPEED 0x020F
+#define PERFORMANCE_MEMORY_PROFILE_CONTROL 0x0210
+#define UCLK_RATIO_CONTROL 0x0212
+
+//
+// Language label
+//
+#define FRONT_PAGE_ITEM_LANGUAGE 0x300
+
+//
+// Boot Labels
+//
+#define BOOT_DEVICE_PRIORITY_BEGIN 0x0400
+#define BOOT_DEVICE_PRIORITY_END 0x0401
+#define BOOT_OPTICAL_DEVICE_BEGIN 0x0410
+#define BOOT_OPTICAL_DEVICE_END 0x0411
+#define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420
+#define BOOT_REMOVABLE_DEVICE_END 0x0421
+#define BOOT_PXE_DEVICE_BEGIN 0x0430
+#define BOOT_PXE_DEVICE_END 0x0431
+#define BOOT_MENU_TYPE_BEGIN 0x0440
+#define BOOT_MENU_TYPE_END 0x0441
+#define BOOT_USB_DEVICE_BEGIN 0x0450
+#define BOOT_USB_DEVICE_END 0x0451
+#define BOOT_USB_FIRST_BEGIN 0x0460
+#define BOOT_USB_FIRST_END 0x0461
+#define BOOT_UEFI_BEGIN 0x0470
+#define BOOT_UEFI_END 0x0471
+#define BOOT_USB_UNAVAILABLE_BEGIN 0x0480
+#define BOOT_USB_UNAVAILABLE_END 0x0481
+#define BOOT_CD_UNAVAILABLE_BEGIN 0x0490
+#define BOOT_CD_UNAVAILABLE_END 0x0491
+#define BOOT_FDD_UNAVAILABLE_BEGIN 0x04A0
+#define BOOT_FDD_UNAVAILABLE_END 0x04A1
+#define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN 0x04B0
+#define BOOT_DEVICE_PRIORITY_DEFAULT_END 0x04B1
+#define BOOT_USB_OPT_LABEL_BEGIN 0x04C0
+#define BOOT_USB_OPT_LABEL_END 0x04C1
+
+#define VAR_EQ_ADMIN_NAME 0x0041 // A
+#define VAR_EQ_ADMIN_DECIMAL_NAME L"65"
+#define VAR_EQ_VIEW_ONLY_NAME 0x0042 // B
+#define VAR_EQ_VIEW_ONLY_DECIMAL_NAME L"66"
+#define VAR_EQ_CONFIG_MODE_NAME 0x0043 // C
+#define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67"
+#define VAR_EQ_CPU_EE_NAME 0x0045 // E
+#define VAR_EQ_CPU_EE_DECIMAL_NAME L"69"
+#define VAR_EQ_FLOPPY_MODE_NAME 0x0046 // F
+#define VAR_EQ_FLOPPY_MODE_DECIMAL_NAME L"70"
+#define VAR_EQ_HT_MODE_NAME 0x0048 // H
+#define VAR_EQ_HT_MODE_DECIMAL_NAME L"72"
+#define VAR_EQ_AHCI_MODE_NAME 0x0049 // I
+#define VAR_EQ_AHCI_MODE_DECIMAL_NAME L"73"
+#define VAR_EQ_CPU_LOCK_NAME 0x004C // L
+#define VAR_EQ_CPU_LOCK_DECIMAL_NAME L"76"
+#define VAR_EQ_NX_MODE_NAME 0x004E // N
+#define VAR_EQ_NX_MODE_DECIMAL_NAME L"78"
+#define VAR_EQ_RAID_MODE_NAME 0x0052 // R
+#define VAR_EQ_RAID_MODE_DECIMAL_NAME L"82"
+#define VAR_EQ_1394_MODE_NAME 0x0054 // T
+#define VAR_EQ_1394_MODE_DECIMAL_NAME L"84"
+#define VAR_EQ_USER_NAME 0x0055 // U
+#define VAR_EQ_USER_DECIMAL_NAME L"85"
+#define VAR_EQ_VIDEO_MODE_NAME 0x0056 // V
+#define VAR_EQ_VIDEO_MODE_DECIMAL_NAME L"86"
+#define VAR_EQ_LEGACY_FP_AUDIO_NAME 0x0057 // W
+#define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87"
+#define VAR_EQ_EM64T_CAPABLE_NAME 0x0058 // X
+#define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88"
+#define VAR_EQ_BOARD_FORMFACTOR_NAME 0x0059 // Y
+#define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89"
+#define VAR_EQ_UNCON_CPU_NAME 0x005B // ??
+#define VAR_EQ_UNCON_CPU_DECIMAL_NAME L"91"
+#define VAR_EQ_VAR_HIDE_NAME 0x005C // ??
+#define VAR_EQ_VAR_HIDE_DECIMAL_NAME L"92"
+#define VAR_EQ_ENERGY_LAKE_NAME 0x005D // ??
+#define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93"
+#define VAR_EQ_TPM_MODE_NAME 0x005E // ^
+#define VAR_EQ_TPM_MODE_DECIMAL_NAME L"94"
+#define VAR_EQ_DISCRETE_SATA_NAME 0x005F // ??
+#define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95"
+#define VAR_EQ_ROEM_SKU_NAME 0x0060 // ??
+#define VAR_EQ_ROEM_SKU_DECIMAL_NAME L"96"
+#define VAR_EQ_AMTSOL_MODE_NAME 0x0061 // ??
+#define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97"
+#define VAR_EQ_NO_PEG_MODE_NAME 0x0062 // ??
+#define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98"
+#define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063 // ??
+#define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99"
+#define VAR_EQ_FLOPPY_HIDE_NAME 0x0064 // ??
+#define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100"
+#define VAR_EQ_SERIAL_HIDE_NAME 0x0065 // ??
+#define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101"
+#define VAR_EQ_GV3_CAPABLE_NAME 0x0066 // f
+#define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102"
+#define VAR_EQ_2_MEMORY_NAME 0x0067 // ??
+#define VAR_EQ_2_MEMORY_DECIMAL_NAME L"103"
+#define VAR_EQ_2_SATA_NAME 0x0068 // ??
+#define VAR_EQ_2_SATA_DECIMAL_NAME L"104"
+#define VAR_EQ_NEC_SKU_NAME 0x0069 // ??
+#define VAR_EQ_NEC_SKU_DECIMAL_NAME L"105"
+#define VAR_EQ_AMT_MODE_NAME 0x006A // ??
+#define VAR_EQ_AMT_MODE_DECIMAL_NAME L"106"
+#define VAR_EQ_LCLX_SKU_NAME 0x006B // ??
+#define VAR_EQ_LCLX_SKU_DECIMAL_NAME L"107"
+#define VAR_EQ_VT_NAME 0x006C
+#define VAR_EQ_VT_DECIMAL_NAME L"108"
+#define VAR_EQ_LT_NAME 0x006D
+#define VAR_EQ_LT_DECIMAL_NAME L"109"
+#define VAR_EQ_ITK_BIOS_MOD_NAME 0x006E // ??
+#define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110"
+#define VAR_EQ_HPET_NAME 0x006F
+#define VAR_EQ_HPET_DECIMAL_NAME L"111"
+#define VAR_EQ_ADMIN_INSTALLED_NAME 0x0070 // ??
+#define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME L"112"
+#define VAR_EQ_USER_INSTALLED_NAME 0x0071 // ??
+#define VAR_EQ_USER_INSTALLED_DECIMAL_NAME L"113"
+#define VAR_EQ_CPU_CMP_NAME 0x0072
+#define VAR_EQ_CPU_CMP_DECIMAL_NAME L"114"
+#define VAR_EQ_LAN_MAC_ADDR_NAME 0x0073 // ??
+#define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME L"115"
+#define VAR_EQ_PARALLEL_HIDE_NAME 0x0074 // ??
+#define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116"
+#define VAR_EQ_AFSC_SETUP_NAME 0x0075
+#define VAR_EQ_AFSC_SETUP_DECIMAL_NAME L"117"
+#define VAR_EQ_MINICARD_MODE_NAME 0x0076 //
+#define VAR_EQ_MINICARD_MODE_DECIMAL_NAME L"118"
+#define VAR_EQ_VIDEO_IGD_NAME 0x0077 //
+#define VAR_EQ_VIDEO_IGD_DECIMAL_NAME L"119"
+#define VAR_EQ_ALWAYS_ENABLE_LAN_NAME 0x0078 //
+#define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME L"120"
+#define VAR_EQ_LEGACY_FREE_NAME 0x0079 //
+#define VAR_EQ_LEGACY_FREE_DECIMAL_NAME L"121"
+#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME 0x007A
+#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME L"122"
+#define VAR_EQ_CPU_FSB_NAME 0x007B //
+#define VAR_EQ_CPU_FSB_DECIMAL_NAME L"123"
+#define VAR_EQ_SATA0_DEVICE_NAME 0x007C //
+#define VAR_EQ_SATA0_DVICE_DECIMAL_NAME L"124"
+#define VAR_EQ_SATA1_DEVICE_NAME 0x007D //
+#define VAR_EQ_SATA1_DVICE_DECIMAL_NAME L"125"
+#define VAR_EQ_SATA2_DEVICE_NAME 0x007E //
+#define VAR_EQ_SATA2_DVICE_DECIMAL_NAME L"126"
+#define VAR_EQ_SATA3_DEVICE_NAME 0x007F //
+#define VAR_EQ_SATA3_DVICE_DECIMAL_NAME L"127"
+#define VAR_EQ_SATA4_DEVICE_NAME 0x0080 //
+#define VAR_EQ_SATA4_DVICE_DECIMAL_NAME L"128"
+#define VAR_EQ_SATA5_DEVICE_NAME 0x0081 //
+#define VAR_EQ_SATA5_DVICE_DECIMAL_NAME L"129"
+#define VAR_EQ_TPM_STATUS_NAME 0x0082 // To indicate if TPM is enabled
+#define VAR_EQ_TPM_STATUS_DECIMAL_NAME L"130"
+#define VAR_EQ_HECETA6E_PECI_CPU_NAME 0x0083
+#define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131"
+#define VAR_EQ_USB_2_NAME 0x0084 //
+#define VAR_EQ_USB_2_DECIMAL_NAME L"132"
+#define VAR_EQ_RVP_NAME 0x0085 //
+#define VAR_EQ_RVP_DECIMAL_NAME L"133"
+#define VAR_EQ_ECIR_NAME 0x0086
+#define VAR_EQ_ECIR_DECIMAL_NAME L"134"
+#define VAR_EQ_WAKONS5KB_NAME 0x0087
+#define VAR_EQ_WAKONS5KB_DECIMAL_NAME L"135"
+#define VAR_EQ_HDAUDIOLINKBP_NAME 0x0088
+#define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME L"136"
+#define VAR_EQ_FINGERPRINT_NAME 0x0089
+#define VAR_EQ_FINGERPRINT_DECIMAL_NAME L"137"
+#define VAR_EQ_BLUETOOTH_NAME 0x008A
+#define VAR_EQ_BLUETOOTH_DECIMAL_NAME L"138"
+#define VAR_EQ_WLAN_NAME 0x008B
+#define VAR_EQ_WLAN_DECIMAL_NAME L"139"
+#define VAR_EQ_1_PATA_NAME 0x008C
+#define VAR_EQ_1_PATA_DECIMAL_NAME L"140"
+#define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME 0x008D
+#define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME L"141"
+#define VAR_EQ_TURBO_MODE_CAP_NAME 0x008E
+#define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME L"142"
+#define VAR_EQ_XE_MODE_CAP_NAME 0x008F
+#define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME L"143"
+#define VAR_EQ_NPI_QPI_VOLTAGE_NAME 0x0090
+#define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144"
+#define VAR_EQ_PRE_PROD_NON_XE_NAME 0x0091
+#define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145"
+#define VAR_EQ_2_C0_MEMORY_NAME 0x0092 // ??
+#define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME L"146"
+#define VAR_EQ_LVDS_NAME 0x0093
+#define VAR_EQ_LVDS_DECIMAL_NAME L"147"
+#define VAR_EQ_USB_OPTION_SHOW_NAME 0x0094
+#define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME L"148"
+#define VAR_EQ_HDD_MASTER_INSTALLED_NAME 0x0095
+#define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME L"149"
+#define VAR_EQ_HDD_USER_INSTALLED_NAME 0x0096
+#define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME L"150"
+#define VAR_EQ_PS2_HIDE_NAME 0x0097 // ??
+#define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151"
+#define VAR_EQ_VIDEO_SLOT_NAME 0x0098
+#define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME L"152"
+#define VAR_EQ_HDMI_SLOT_NAME 0x0099
+#define VAR_EQ_HDMI_SLOT_DECIMAL_NAME L"153"
+#define VAR_EQ_SERIAL2_HIDE_NAME 0x009a
+#define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154"
+#define VAR_EQ_LVDS_WARNING_HIDE_NAME 0x009e
+#define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158"
+#define VAR_EQ_MSATA_HIDE_NAME 0x009f
+#define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159"
+#define VAR_EQ_PCI_SLOT1_NAME 0x00a0
+#define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160"
+#define VAR_EQ_PCI_SLOT2_NAME 0x00a1
+#define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161"
+//
+// Generic Form Ids
+//
+#define ROOT_FORM_ID 1
+
+//
+// Advance Page. Do not have to be sequential but have to be unique
+//
+#define CONFIGURATION_ROOT_FORM_ID 2
+#define BOOT_CONFIGURATION_ID 3
+#define ONBOARDDEVICE_CONFIGURATION_ID 4
+#define DRIVE_CONFIGURATION_ID 5
+#define FLOPPY_CONFIGURATION_ID 6
+#define EVENT_LOG_CONFIGURATION_ID 7
+#define VIDEO_CONFIGURATION_ID 8
+#define USB_CONFIGURATION_ID 9
+#define HARDWARE_MONITOR_CONFIGURATION_ID 10
+#define VIEW_EVENT_LOG_CONFIGURATION_ID 11
+#define MEMORY_OVERRIDE_ID 12
+#define CHIPSET_CONFIGURATION_ID 13
+#define BURN_IN_MODE_ID 14
+#define PCI_EXPRESS_ID 15
+#define MANAGEMENT_CONFIGURATION_ID 16
+#define CPU_CONFIGURATION_ID 17
+#define PCI_CONFIGURATION_ID 18
+#define SECURITY_CONFIGURATION_ID 19
+#define ZIP_CONFIGURATION_ID 20
+#define AFSC_FAN_CONTROL_ID 21
+#define VFR_FORMID_CSI 22
+#define VFR_FORMID_MEMORY 23
+#define VFR_FORMID_IOH 24
+#define VFR_FORMID_CPU_CSI 25
+#define VFR_FORMID_IOH_CONFIG 26
+#define VFR_FORMID_VTD 27
+#define VFR_FORMID_PCIE_P0 28
+#define VFR_FORMID_PCIE_P1 29
+#define VFR_FORMID_PCIE_P2 30
+#define VFR_FORMID_PCIE_P3 31
+#define VFR_FORMID_PCIE_P4 32
+#define VFR_FORMID_PCIE_P5 33
+#define VFR_FORMID_PCIE_P6 34
+#define VFR_FORMID_PCIE_P7 35
+#define VFR_FORMID_PCIE_P8 36
+#define VFR_FORMID_PCIE_P9 37
+#define VFR_FORMID_PCIE_P10 38
+#define VFR_FID_SKT0 39
+#define VFR_FID_IOH0 40
+#define VFR_FID_IOH_DEV_HIDE 41
+#define PROCESSOR_OVERRIDES_FORM_ID 42
+#define BUS_OVERRIDES_FORM_ID 43
+#define REF_OVERRIDES_FORM_ID 44
+#define MEMORY_INFORMATION_ID 45
+#define LVDS_WARNING_ID 46
+#define LVDS_CONFIGURATION_ID 47
+#define PCI_SLOT_CONFIGURATION_ID 48
+#define HECETA_CONFIGURATION_ID 49
+#define LVDS_EXPERT_CONFIGURATION_ID 50
+#define PCI_SLOT_7_ID 51
+#define PCI_SLOT_6_ID 52
+#define PCI_SLOT_5_ID 53
+#define PCI_SLOT_4_ID 54
+#define PCI_SLOT_3_ID 55
+#define PCI_SLOT_2_ID 56
+#define PCI_SLOT_1_ID 57
+#define BOOT_DISPLAY_ID 58
+#define CPU_PWR_CONFIGURATION_ID 59
+
+#define FSC_CONFIGURATION_ID 60
+#define FSC_CPU_TEMPERATURE_FORM_ID 61
+#define FSC_VTT_VOLTAGE_FORM_ID 62
+#define FSC_FEATURES_CONTROL_ID 63
+#define FSC_FAN_CONFIGURATION_ID 64
+#define FSC_PROCESSOR_FAN_CONFIGURATION_ID 65
+#define FSC_FRONT_FAN_CONFIGURATION_ID 66
+#define FSC_REAR_FAN_CONFIGURATION_ID 67
+#define FSC_AUX_FAN_CONFIGURATION_ID 68
+#define FSC_12_VOLTAGE_FORM_ID 69
+#define FSC_5_VOLTAGE_FORM_ID 70
+#define FSC_3P3_VOLTAGE_FORM_ID 71
+#define FSC_2P5_VOLTAGE_FORM_ID 72
+#define FSC_VCC_VOLTAGE_FORM_ID 73
+#define FSC_TEMPERATURE_FORM_ID 74
+#define FSC_MEM_TEMPERATURE_FORM_ID 75
+#define FSC_VR_TEMPERATURE_FORM_ID 76
+#define FSC_3P3STANDBY_VOLTAGE_FORM_ID 77
+#define FSC_5BACKUP_VOLTAGE_FORM_ID 78
+#define ROOT_MAIN_FORM_ID 79
+#define ROOT_BOOT_FORM_ID 80
+#define ROOT_MAINTENANCE_ID 81
+#define ROOT_POWER_FORM_ID 82
+#define ROOT_SECURITY_FORM_ID 83
+#define ROOT_PERFORMANCE_FORM_ID 84
+#define ROOT_SYSTEM_SETUP_FORM_ID 85
+
+#define ADDITIONAL_SYSTEM_INFO_FORM_ID 86
+
+#define THERMAL_CONFIG_FORM_ID 87
+
+#define PCI_SLOT_CONFIG_LABEL_ID_1 0x300A
+#define PCI_SLOT_CONFIG_LABEL_ID_2 0x300B
+#define PCI_SLOT_CONFIG_LABEL_ID_3 0x300C
+#define PCI_SLOT_CONFIG_LABEL_ID_4 0x300D
+#define PCI_SLOT_CONFIG_LABEL_ID_5 0x300E
+#define PCI_SLOT_CONFIG_LABEL_ID_6 0x300F
+#define PCI_SLOT_CONFIG_LABEL_ID_7 0x3010
+#define PCI_SLOT_CONFIG_LABEL_ID_8 0x3011
+
+//
+// Advance Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
+//
+#define CONFIGURATION_HARDWARE_CALLBACK_KEY 0x2000
+#define ADVANCE_VIDEO_CALLBACK_KEY 0x2001
+#define CONFIGURATION_FSC_CALLBACK_KEY 0x2002
+#define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY 0x2003
+#define CONFIGURATION_LVDS_CALLBACK_KEY 0x2004
+#define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY 0x2005
+#define ADVANCE_LVDS_CALLBACK_KEY 0x2010
+
+//
+// Main Callback Keys. Do not have to be sequential but have to be unique
+//
+#define MAIN_LANGUAGE_CALLBACK_KEY 0x3000
+
+//
+// Power Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
+//
+#define POWER_HARDWARE_CALLBACK_KEY 0x4000
+
+//
+// Performance Callback Keys. Do not have to be sequential but have to be unique
+//
+#define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000
+#define PERFORMANCE_CALLBACK_KEY 0x5001
+#define BUS_OVERRIDES_CALLBACK_KEY 0x5002
+#define MEMORY_CFG_CALLBACK_KEY 0x5003
+#define PERFORMANCE_STATUS_CALLBACK_KEY 0x5004
+#define MEMORY_RATIO_CALLBACK_KEY 0x5005
+#define MEMORY_MODE_CALLBACK_KEY 0x5006
+
+//
+// Security Callback Keys. Do not have to be sequential but have to be unique
+//
+#define SECURITY_SUPERVISOR_CALLBACK_KEY 0x1000
+#define SECURITY_USER_CALLBACK_KEY 0x1001
+#define SECURITY_CLEAR_ALL_CALLBACK_KEY 0x1002
+#define SECURITY_CLEAR_USER_CALLBACK_KEY 0x1004
+#define SECURITY_RESET_AMT_CALLBACK_KEY 0x1008
+#define SECURITY_CHANGE_VT_CALLBACK_KEY 0x1010
+#define SECURITY_MASTER_HDD_CALLBACK_KEY 0x1020
+#define SECURITY_USER_HDD_CALLBACK_KEY 0x1040
+
+//
+// Boot Callback Keys. Do not have to be sequential but have to be unique
+//
+#define BOOT_HYPERBOOT_CALLBACK_KEY 0x6003
+#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE 0x6004
+#define BOOT_HYPERBOOT_CALLBACK_KEY_USB 0x6005
+#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006
+
+//
+// IDCC/Setup FSB Frequency Override Range
+//
+#define EFI_IDCC_FSB_MIN 133
+#define EFI_IDCC_FSB_MAX 240
+#define EFI_IDCC_FSB_STEP 1
+
+//
+// Reference voltage
+//
+#define EFI_REF_DAC_MIN 0
+#define EFI_REF_DAC_MAX 255
+#define EFI_GTLREF_DEF 170
+#define EFI_DDRREF_DEF 128
+#define EFI_DIMMREF_DEF 128
+
+// Setup FSB Frequency Override Range
+//
+#define EFI_FSB_MIN 133
+#define EFI_FSB_MAX 240
+#define EFI_FSB_STEP 1
+#define EFI_FSB_AUTOMATIC 0
+#define EFI_FSB_MANUAL 1
+#define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX - EFI_FSB_MIN)/EFI_FSB_STEP) + 1
+#define FSB_FREQ_ENTRY_TYPE UINT16_TYPE
+
+//
+// Setup processor multiplier range
+//
+#define EFI_PROC_MULT_MIN 5
+#define EFI_PROC_MULT_MAX 40
+#define EFI_PROC_MULT_STEP 1
+#define EFI_PROC_AUTOMATIC 0
+#define EFI_PROC_MANUAL 1
+#define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX - EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1
+#define PROC_MULT_ENTRY_TYPE UINT8_TYPE
+
+//
+// PCI Express Definitions
+//
+#define EFI_PCIE_FREQ_DEF 0x0
+
+#define PCIE_FREQ_ENTRY_TYPE UINT8_TYPE
+#define PCIE_FREQ_ENTRY_7 0x7
+#define PCIE_FREQ_ENTRY_6 0x6
+#define PCIE_FREQ_ENTRY_5 0x5
+#define PCIE_FREQ_ENTRY_4 0x4
+#define PCIE_FREQ_ENTRY_3 0x3
+#define PCIE_FREQ_ENTRY_2 0x2
+#define PCIE_FREQ_ENTRY_1 0x1
+#define PCIE_FREQ_ENTRY_0 0x0
+
+#define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8
+#define PCIE_FREQ_TRANSLATION_TABLE { PCIE_FREQ_ENTRY_0, \
+ PCIE_FREQ_ENTRY_1, \
+ PCIE_FREQ_ENTRY_2, \
+ PCIE_FREQ_ENTRY_3, \
+ PCIE_FREQ_ENTRY_4, \
+ PCIE_FREQ_ENTRY_5, \
+ PCIE_FREQ_ENTRY_6, \
+ PCIE_FREQ_ENTRY_7 }
+
+
+#define PCIE_FREQ_PRECISION 2
+#define PCIE_FREQ_VALUE_7 10924
+#define PCIE_FREQ_VALUE_6 10792
+#define PCIE_FREQ_VALUE_5 10660
+#define PCIE_FREQ_VALUE_4 10528
+#define PCIE_FREQ_VALUE_3 10396
+#define PCIE_FREQ_VALUE_2 10264
+#define PCIE_FREQ_VALUE_1 10132
+#define PCIE_FREQ_VALUE_0 10000
+
+#define PCIE_FREQ_VALUES { PCIE_FREQ_VALUE_0, \
+ PCIE_FREQ_VALUE_1, \
+ PCIE_FREQ_VALUE_2, \
+ PCIE_FREQ_VALUE_3, \
+ PCIE_FREQ_VALUE_4, \
+ PCIE_FREQ_VALUE_5, \
+ PCIE_FREQ_VALUE_6, \
+ PCIE_FREQ_VALUE_7 }
+
+//
+// Memory Frequency Definitions
+//
+#define MEMORY_REF_FREQ_ENTRY_DEF 0x08
+
+#define MEMORY_REF_FREQ_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_REF_FREQ_ENTRY_3 0x04
+#define MEMORY_REF_FREQ_ENTRY_2 0x00
+#define MEMORY_REF_FREQ_ENTRY_1 0x02
+#define MEMORY_REF_FREQ_ENTRY_0 0x01
+
+#define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_REF_FREQ_TRANSLATION_TABLE { MEMORY_REF_FREQ_ENTRY_0, \
+ MEMORY_REF_FREQ_ENTRY_1, \
+ MEMORY_REF_FREQ_ENTRY_2, \
+ MEMORY_REF_FREQ_ENTRY_3 }
+
+#define MEMORY_REF_FREQ_PRECISION 0
+#define MEMORY_REF_FREQ_VALUE_3 333
+#define MEMORY_REF_FREQ_VALUE_2 267
+#define MEMORY_REF_FREQ_VALUE_1 200
+#define MEMORY_REF_FREQ_VALUE_0 133
+
+#define MEMORY_REF_FREQ_VALUES { MEMORY_REF_FREQ_VALUE_0, \
+ MEMORY_REF_FREQ_VALUE_1, \
+ MEMORY_REF_FREQ_VALUE_2, \
+ MEMORY_REF_FREQ_VALUE_3 }
+
+
+//
+// Memory Reference Frequency Definitions
+//
+
+#define MEMORY_FREQ_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_FREQ_ENTRY_3 0x4
+#define MEMORY_FREQ_ENTRY_2 0x3
+#define MEMORY_FREQ_ENTRY_1 0x2
+#define MEMORY_FREQ_ENTRY_0 0x1
+
+#define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_FREQ_TRANSLATION_TABLE { MEMORY_FREQ_ENTRY_0, \
+ MEMORY_FREQ_ENTRY_1, \
+ MEMORY_FREQ_ENTRY_2, \
+ MEMORY_FREQ_ENTRY_3 }
+
+
+#define MEMORY_FREQ_MULT_PRECISION 2
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_3 240
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_2 200
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_1 160
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_0 120
+
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_3 300
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_2 250
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_1 200
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_0 150
+
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_3 400
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_2 333
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_1 267
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_0 200
+
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_3 600
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_2 500
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_1 400
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_0 300
+
+#define MEMORY_FREQ_MULT_333MHZ_VALUES { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \
+ MEMORY_FREQ_MULT_333MHZ_VALUE_1, \
+ MEMORY_FREQ_MULT_333MHZ_VALUE_2, \
+ MEMORY_FREQ_MULT_333MHZ_VALUE_3 }
+
+#define MEMORY_FREQ_MULT_266MHZ_VALUES { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \
+ MEMORY_FREQ_MULT_266MHZ_VALUE_1, \
+ MEMORY_FREQ_MULT_266MHZ_VALUE_2, \
+ MEMORY_FREQ_MULT_266MHZ_VALUE_3 }
+
+#define MEMORY_FREQ_MULT_200MHZ_VALUES { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \
+ MEMORY_FREQ_MULT_200MHZ_VALUE_1, \
+ MEMORY_FREQ_MULT_200MHZ_VALUE_2, \
+ MEMORY_FREQ_MULT_200MHZ_VALUE_3 }
+
+#define MEMORY_FREQ_MULT_133MHZ_VALUES { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \
+ MEMORY_FREQ_MULT_133MHZ_VALUE_1, \
+ MEMORY_FREQ_MULT_133MHZ_VALUE_2, \
+ MEMORY_FREQ_MULT_133MHZ_VALUE_3 }
+
+//
+// CAS Memory Timing Definitions
+//
+
+#define MEMORY_TCL_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_TCL_ENTRY_3 0x2
+#define MEMORY_TCL_ENTRY_2 0x1
+#define MEMORY_TCL_ENTRY_1 0x0
+#define MEMORY_TCL_ENTRY_0 0x3
+
+#define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_TCL_TRANSLATION_TABLE { MEMORY_TCL_ENTRY_0, \
+ MEMORY_TCL_ENTRY_1, \
+ MEMORY_TCL_ENTRY_2, \
+ MEMORY_TCL_ENTRY_3 }
+
+
+#define MEMORY_TCL_PRECISION 0
+#define MEMORY_TCL_VALUE_3 3
+#define MEMORY_TCL_VALUE_2 4
+#define MEMORY_TCL_VALUE_1 5
+#define MEMORY_TCL_VALUE_0 6
+
+#define MEMORY_TCL_VALUES { MEMORY_TCL_VALUE_0, \
+ MEMORY_TCL_VALUE_1, \
+ MEMORY_TCL_VALUE_2, \
+ MEMORY_TCL_VALUE_3 }
+
+
+//
+// TRCD Memory Timing Definitions
+//
+
+#define MEMORY_TRCD_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_TRCD_ENTRY_3 0x0
+#define MEMORY_TRCD_ENTRY_2 0x1
+#define MEMORY_TRCD_ENTRY_1 0x2
+#define MEMORY_TRCD_ENTRY_0 0x3
+
+#define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_TRCD_TRANSLATION_TABLE { MEMORY_TRCD_ENTRY_0, \
+ MEMORY_TRCD_ENTRY_1, \
+ MEMORY_TRCD_ENTRY_2, \
+ MEMORY_TRCD_ENTRY_3 }
+
+
+#define MEMORY_TRCD_PRECISION 0
+#define MEMORY_TRCD_VALUE_3 2
+#define MEMORY_TRCD_VALUE_2 3
+#define MEMORY_TRCD_VALUE_1 4
+#define MEMORY_TRCD_VALUE_0 5
+
+#define MEMORY_TRCD_VALUES { MEMORY_TRCD_VALUE_0, \
+ MEMORY_TRCD_VALUE_1, \
+ MEMORY_TRCD_VALUE_2, \
+ MEMORY_TRCD_VALUE_3 }
+
+
+//
+// TRP Memory Timing Definitions
+//
+
+#define MEMORY_TRP_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_TRP_ENTRY_3 0x0
+#define MEMORY_TRP_ENTRY_2 0x1
+#define MEMORY_TRP_ENTRY_1 0x2
+#define MEMORY_TRP_ENTRY_0 0x3
+
+#define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_TRP_TRANSLATION_TABLE { MEMORY_TRP_ENTRY_0, \
+ MEMORY_TRP_ENTRY_1, \
+ MEMORY_TRP_ENTRY_2, \
+ MEMORY_TRP_ENTRY_3 }
+
+
+#define MEMORY_TRP_PRECISION 0
+#define MEMORY_TRP_VALUE_3 2
+#define MEMORY_TRP_VALUE_2 3
+#define MEMORY_TRP_VALUE_1 4
+#define MEMORY_TRP_VALUE_0 5
+
+#define MEMORY_TRP_VALUES { MEMORY_TRP_VALUE_0, \
+ MEMORY_TRP_VALUE_1, \
+ MEMORY_TRP_VALUE_2, \
+ MEMORY_TRP_VALUE_3 }
+
+
+//
+// TRAS Memory Timing Definitions
+//
+#define MEMORY_TRAS_MIN 4
+#define MEMORY_TRAS_MAX 18
+#define MEMORY_TRAS_STEP 1
+#define MEMORY_TRAS_DEFAULT 13
+#define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX - MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1
+#define MEMORY_TRAS_TYPE UINT8_TYPE
+
+//
+// Uncore Multiplier Definitions
+//
+#define UCLK_RATIO_MIN 12
+#define UCLK_RATIO_MAX 30
+#define UCLK_RATIO_DEFAULT 20
+
+#endif // #ifndef _CONFIGURATION_H
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IchRegTable.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IchRegTable.c new file mode 100644 index 0000000000..589c97846f --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IchRegTable.c @@ -0,0 +1,110 @@ +/** @file
+ Register initialization table for SC.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include <Library/EfiRegTableLib.h>
+#include <Library/SteppingLib.h>
+
+extern EFI_PLATFORM_INFO_HOB mPlatformInfo;
+
+#define R_EFI_PCI_SVID 0x2C
+
+/**
+ Updates the mSubsystemIdRegs table, and processes it.
+ This should program the Subsystem Vendor and Device IDs.
+
+**/
+VOID
+InitializeSubsystemIds (
+ )
+{
+ EFI_REG_TABLE *RegTablePtr;
+ UINT32 SubsystemVidDid;
+ UINT32 SubsystemAudioVidDid;
+ UINTN Stepping;
+ EFI_REG_TABLE SubsystemIdRegsPCIESC [] = {
+ //
+ // Program SVID and SID for PCI devices.
+ // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance
+ //
+ PCI_WRITE (
+ SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,
+ V_SC_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,
+ V_SC_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+
+ #ifdef PCIESC_SUPPORT
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_SC_PCIE_DEVICE_1, PCI_FUNCTION_NUMBER_PCIE_ROOT_PORT_1, R_PCIE_SVID, EfiPciWidthUint32,
+ V_SC_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ #endif
+
+ TERMINATE_TABLE
+ };
+
+ EFI_REG_TABLE SubsystemIdRegs [] = {
+ PCI_WRITE (
+ SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,
+ V_SC_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,
+ V_SC_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+
+ TERMINATE_TABLE
+ };
+
+ SubsystemVidDid = mPlatformInfo.SsidSvid;
+ SubsystemAudioVidDid = mPlatformInfo.SsidSvid;
+
+ Stepping = BxtStepping ();
+ if ((Stepping != BxtA0) && (Stepping != BxtA1)) {
+ RegTablePtr = SubsystemIdRegsPCIESC;
+ } else {
+ RegTablePtr = SubsystemIdRegs;
+ }
+
+ //
+ // Check Board ID GPI to see if we need to use alternate SSID
+ //
+ // While we are not at the end of the table
+ //
+ while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {
+ //
+ // If the data to write is the original SSID
+ //
+ if (RegTablePtr->PciWrite.Data == ((V_SC_DEFAULT_SID << 16) | V_INTEL_VENDOR_ID)) {
+ //
+ // Then overwrite it to use the alternate SSID
+ //
+ RegTablePtr->PciWrite.Data = SubsystemVidDid;
+ }
+ //
+ // Go to next table entry
+ //
+ RegTablePtr ++;
+ }
+
+ //
+ // Program the SSVID/SSDID
+ //
+ ProcessRegTablePci (RegTablePtr, mPciRootBridgeIo, NULL);
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IchTcoReset.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IchTcoReset.c new file mode 100644 index 0000000000..5b89f63352 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IchTcoReset.c @@ -0,0 +1,200 @@ +/** @file
+ Implements the programming of events in TCO Reset.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include <Protocol/TcoReset.h>
+#include <Protocol/HwWatchdogTimer.h>
+
+EFI_STATUS
+EFIAPI
+EnableTcoReset (
+ IN UINT32 *RcrbGcsSaveValue
+ );
+
+EFI_STATUS
+EFIAPI
+DisableTcoReset (
+ OUT UINT32 RcrbGcsRestoreValue
+ );
+
+EFI_TCO_RESET_PROTOCOL mTcoResetProtocol = {
+ EnableTcoReset,
+ DisableTcoReset
+};
+
+
+/**
+ Enables the TCO timer to reset the system in case of a system hang. This is
+ used when writing the clock registers.
+
+ @param[in] RcrbGcsSaveValue This is the value of the RCRB GCS register before it is
+ changed by this procedure. This will be used to restore
+ the settings of this register in PpiDisableTcoReset.
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+EnableTcoReset (
+ IN UINT32 *RcrbGcsSaveValue
+ )
+{
+ UINT16 TmpWord;
+ UINT16 AcpiBaseAddr;
+ EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL *WatchdogTimerProtocol;
+ EFI_STATUS Status;
+ UINTN PbtnDisableInterval = 4; //Default value
+
+ //
+ // Get Watchdog Timer protocol.
+ //
+ Status = gBS->LocateProtocol (&gEfiWatchdogTimerDriverProtocolGuid, NULL, (VOID **) &WatchdogTimerProtocol);
+
+ //
+ // If the protocol is present, shut off the Timer as we enter BDS
+ //
+ if (!EFI_ERROR (Status)) {
+ WatchdogTimerProtocol->RestartWatchdogTimer ();
+ WatchdogTimerProtocol->AllowKnownReset (TRUE);
+ }
+
+ if (*RcrbGcsSaveValue == 0) {
+ PbtnDisableInterval = PcdGet32 (PcdPBTNDisableInterval);
+ } else {
+ PbtnDisableInterval = *RcrbGcsSaveValue * 10 / 6;
+ }
+
+ //
+ // Read ACPI Base Address
+ //
+ AcpiBaseAddr = (UINT16) PcdGet16 (PcdScAcpiIoPortBaseAddress);
+
+ //
+ // Stop TCO if not already stopped
+ //
+ TmpWord = IoRead16 (AcpiBaseAddr + R_TCO_CNT);
+ TmpWord |= B_TCO_CNT_TMR_HLT;
+ IoWrite16 (AcpiBaseAddr + R_TCO_CNT, TmpWord);
+
+ //
+ // Clear second TCO status
+ //
+ IoWrite32 (AcpiBaseAddr + R_TCO_STS, B_TCO_STS_SECOND_TO);
+
+ //
+ // Enable reboot on TCO timeout
+ //
+ *RcrbGcsSaveValue = MmioRead32 (PMC_BASE_ADDRESS + R_PMC_PM_CFG);
+ MmioAnd8 (PMC_BASE_ADDRESS + R_PMC_PM_CFG, (UINT8) ~B_PMC_PM_CFG_NO_REBOOT);
+
+ //
+ // Set TCO reload value (interval *.6s)
+ //
+ IoWrite32 (AcpiBaseAddr + R_TCO_TMR, (UINT32) (PbtnDisableInterval << 16));
+
+ //
+ // Force TCO to load new value
+ //
+ IoWrite8 (AcpiBaseAddr + R_TCO_RLD, 4);
+
+ //
+ // Clear second TCO status
+ //
+ IoWrite32 (AcpiBaseAddr + R_TCO_STS, B_TCO_STS_SECOND_TO);
+
+ //
+ // Start TCO timer running
+ //
+ TmpWord = IoRead16 (AcpiBaseAddr + R_TCO_CNT);
+ TmpWord &= ~(B_TCO_CNT_TMR_HLT);
+ IoWrite16 (AcpiBaseAddr + R_TCO_CNT, TmpWord);
+
+ //
+ // Clear Sleep Type Enable
+ //
+ IoWrite16 (AcpiBaseAddr + R_SMI_EN,
+ (UINT16) (IoRead16 (AcpiBaseAddr + R_SMI_EN) & (~B_SMI_EN_ON_SLP_EN)));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Disables the TCO timer.
+ This is used after writing the clock registers.
+
+ @param[out] RcrbGcsRestoreValue Value saved in PpiEnableTcoReset so that it can restored.
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+DisableTcoReset (
+ OUT UINT32 RcrbGcsRestoreValue
+ )
+{
+ UINT16 TmpWord;
+ UINT16 AcpiBaseAddr;
+ EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL *WatchdogTimerProtocol;
+ EFI_STATUS Status;
+
+ //
+ // Read ACPI Base Address
+ //
+ AcpiBaseAddr = (UINT16) PcdGet16 (PcdScAcpiIoPortBaseAddress);
+
+ //
+ // Stop the TCO timer
+ //
+ TmpWord = IoRead16 (AcpiBaseAddr + R_TCO_CNT);
+ TmpWord |= B_TCO_CNT_TMR_HLT;
+ IoWrite16 (AcpiBaseAddr + R_TCO_CNT, TmpWord);
+
+ //
+ // Get Watchdog Timer protocol.
+ //
+ Status = gBS->LocateProtocol (&gEfiWatchdogTimerDriverProtocolGuid, NULL, (VOID **) &WatchdogTimerProtocol);
+
+ //
+ // If the protocol is present, shut off the Timer as we enter BDS
+ //
+ if (!EFI_ERROR (Status)) {
+ WatchdogTimerProtocol->AllowKnownReset (FALSE);
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+VOID
+InitTcoReset (
+ )
+{
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiTcoResetProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mTcoResetProtocol
+ );
+
+ ASSERT_EFI_ERROR (Status);
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IdePlatformPolicy.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IdePlatformPolicy.c new file mode 100644 index 0000000000..76cd7cba86 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/IdePlatformPolicy.c @@ -0,0 +1,48 @@ +/** @file
+ Platform IDE init driver's policy according to setup variable.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include "Protocol/PlatformIdeInit.h"
+
+EFI_PLATFORM_IDE_INIT_PROTOCOL mPlatformIdeInit = {
+ TRUE
+};
+
+
+/**
+ Updates the feature policies according to the setup variable.
+
+**/
+VOID
+InitPlatformIdePolicy (
+ )
+{
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+
+ if ( mSystemConfiguration.SmartMode ) {
+ mPlatformIdeInit.SmartMode = FALSE;
+ }
+
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiPlatformIdeInitProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mPlatformIdeInit
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciBus.h b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciBus.h new file mode 100644 index 0000000000..92be4e7142 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciBus.h @@ -0,0 +1,382 @@ +/** @file
+ Header files and data structures needed by PCI Bus module.
+
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_PCI_BUS_H_
+#define _EFI_PCI_BUS_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/LoadedImage.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/LoadFile2.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHotPlugRequest.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/PciPlatform.h>
+#include <Protocol/PciHotPlugInit.h>
+#include <Protocol/Decompress.h>
+#include <Protocol/BusSpecificDriverOverride.h>
+#include <Protocol/IncompatiblePciDeviceSupport.h>
+#include <Protocol/PciOverride.h>
+#include <Protocol/PciEnumerationComplete.h>
+
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeCoffLib.h>
+
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/PeImage.h>
+#include <IndustryStandard/Acpi.h>
+
+typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
+typedef struct _PCI_BAR PCI_BAR;
+
+#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
+#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
+
+#define EFI_PCI_IOV_POLICY_ARI 0x0001
+#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
+#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
+
+typedef enum {
+ PciBarTypeUnknown = 0,
+ PciBarTypeIo16,
+ PciBarTypeIo32,
+ PciBarTypeMem32,
+ PciBarTypePMem32,
+ PciBarTypeMem64,
+ PciBarTypePMem64,
+ PciBarTypeIo,
+ PciBarTypeMem,
+ PciBarTypeMaxType
+} PCI_BAR_TYPE;
+
+
+#define VGABASE1 0x3B0
+#define VGALIMIT1 0x3BB
+
+#define VGABASE2 0x3C0
+#define VGALIMIT2 0x3DF
+
+#define ISABASE 0x100
+#define ISALIMIT 0x3FF
+
+//
+// PCI BAR parameters
+//
+struct _PCI_BAR {
+ UINT64 BaseAddress;
+ UINT64 Length;
+ UINT64 Alignment;
+ PCI_BAR_TYPE BarType;
+ BOOLEAN Prefetchable;
+ UINT8 MemType;
+ UINT16 Offset;
+};
+
+//
+// defined in PCI Card Specification, 8.0
+//
+#define PCI_CARD_MEMORY_BASE_0 0x1C
+#define PCI_CARD_MEMORY_LIMIT_0 0x20
+#define PCI_CARD_MEMORY_BASE_1 0x24
+#define PCI_CARD_MEMORY_LIMIT_1 0x28
+#define PCI_CARD_IO_BASE_0_LOWER 0x2C
+#define PCI_CARD_IO_BASE_0_UPPER 0x2E
+#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
+#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
+#define PCI_CARD_IO_BASE_1_LOWER 0x34
+#define PCI_CARD_IO_BASE_1_UPPER 0x36
+#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
+#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
+#define PCI_CARD_BRIDGE_CONTROL 0x3E
+
+#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
+#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
+
+#define PPB_BAR_0 0
+#define PPB_BAR_1 1
+#define PPB_IO_RANGE 2
+#define PPB_MEM32_RANGE 3
+#define PPB_PMEM32_RANGE 4
+#define PPB_PMEM64_RANGE 5
+#define PPB_MEM64_RANGE 0xFF
+
+#define P2C_BAR_0 0
+#define P2C_MEM_1 1
+#define P2C_MEM_2 2
+#define P2C_IO_1 3
+#define P2C_IO_2 4
+
+#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
+#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
+#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
+#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
+#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
+#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
+#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
+
+#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
+
+//
+// Define option for attribute
+//
+#define EFI_SET_SUPPORTS 0
+#define EFI_SET_ATTRIBUTES 1
+
+#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
+
+struct _PCI_IO_DEVICE {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PROTOCOL PciIo;
+ LIST_ENTRY Link;
+
+ EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_LOAD_FILE2_PROTOCOL LoadFile2;
+
+ //
+ // PCI configuration space header type
+ //
+ PCI_TYPE00 Pci;
+
+ //
+ // Bus number, Device number, Function number
+ //
+ UINT8 BusNumber;
+ UINT8 DeviceNumber;
+ UINT8 FunctionNumber;
+
+ //
+ // BAR for this PCI Device
+ //
+ PCI_BAR PciBar[PCI_MAX_BAR];
+
+ //
+ // The bridge device this pci device is subject to
+ //
+ PCI_IO_DEVICE *Parent;
+
+ //
+ // A linked list for children Pci Device if it is bridge device
+ //
+ LIST_ENTRY ChildList;
+
+ //
+ // TURE if the PCI bus driver creates the handle for this PCI device
+ //
+ BOOLEAN Registered;
+
+ //
+ // TRUE if the PCI bus driver successfully allocates the resource required by
+ // this PCI device
+ //
+ BOOLEAN Allocated;
+
+ //
+ // The attribute this PCI device currently set
+ //
+ UINT64 Attributes;
+
+ //
+ // The attributes this PCI device actually supports
+ //
+ UINT64 Supports;
+
+ //
+ // The resource decode the bridge supports
+ //
+ UINT32 Decodes;
+
+ //
+ // TRUE if the ROM image is from the PCI Option ROM BAR
+ //
+ BOOLEAN EmbeddedRom;
+
+ //
+ // The OptionRom Size
+ //
+ UINT64 RomSize;
+
+ //
+ // The OptionRom Size
+ //
+ UINT64 RomBase;
+
+ //
+ // TRUE if all OpROM (in device or in platform specific position) have been processed
+ //
+ BOOLEAN AllOpRomProcessed;
+
+ //
+ // TRUE if there is any EFI driver in the OptionRom
+ //
+ BOOLEAN BusOverride;
+
+ //
+ // A list tracking reserved resource on a bridge device
+ //
+ LIST_ENTRY ReservedResourceList;
+
+ //
+ // A list tracking image handle of platform specific overriding driver
+ //
+ LIST_ENTRY OptionRomDriverList;
+
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
+ EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
+
+ BOOLEAN IsPciExp;
+ //
+ // For SR-IOV
+ //
+ UINT8 PciExpressCapabilityOffset;
+ UINT32 AriCapabilityOffset;
+ UINT32 SrIovCapabilityOffset;
+ UINT32 MrIovCapabilityOffset;
+ PCI_BAR VfPciBar[PCI_MAX_BAR];
+ UINT32 SystemPageSize;
+ UINT16 InitialVFs;
+ UINT16 ReservedBusNum;
+ //
+ // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
+ // but some chipsets support non-stardard I/O window aligments less than 4K.
+ // This field is used to support this case.
+ //
+ UINT16 BridgeIoAlignment;
+};
+
+#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
+ CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
+
+#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
+ CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
+
+#define PCI_IO_DEVICE_FROM_LINK(a) \
+ CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
+
+#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
+ CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
+
+
+
+//
+// Global Variables
+//
+extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
+extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
+extern BOOLEAN gFullEnumeration;
+extern UINTN gPciHostBridgeNumber;
+extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
+extern UINT64 gAllOne;
+extern UINT64 gAllZero;
+extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
+extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
+extern BOOLEAN mReserveIsaAliases;
+extern BOOLEAN mReserveVgaAliases;
+
+/**
+ Macro that checks whether device is a GFX device.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a a GFX device.
+ @retval FALSE Device is not a a GFX device.
+
+**/
+#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
+
+/**
+ Test to see if this driver supports ControllerHandle. Any ControllerHandle
+ than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
+
+ @param[in] This Protocol instance pointer.
+ @param[in] Controller Handle of device to test.
+ @param[in] RemainingDevicePath Optional parameter use to pick a specific child.
+ device to start.
+
+ @retval EFI_SUCCESS This driver supports this device.
+ @retval EFI_ALREADY_STARTED This driver is already running on this device.
+ @retval other This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+PciBusDriverBindingSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+/**
+ Start this driver on ControllerHandle and enumerate Pci bus and start
+ all device under PCI bus.
+
+ @param[in] This Protocol instance pointer.
+ @param[in] Controller Handle of device to bind driver to.
+ @param[in] RemainingDevicePath Optional parameter use to pick a specific child.
+ device to start.
+
+ @retval EFI_SUCCESS This driver is added to ControllerHandle.
+ @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.
+ @retval other This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+PciBusDriverBindingStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+/**
+ Stop this driver on ControllerHandle. Support stoping any child handles
+ created by this driver.
+
+ @param[in] This Protocol instance pointer.
+ @param[in] Controller Handle of device to stop driver on.
+ @param[in] NumberOfChildren Number of Handles in ChildHandleBuffer. If number of
+ children is zero stop the entire bus driver.
+ @param[in] ChildHandleBuffer List of Child Handles to Stop.
+
+ @retval EFI_SUCCESS This driver is removed ControllerHandle.
+ @retval other This driver was not removed from this device.
+
+**/
+EFI_STATUS
+EFIAPI
+PciBusDriverBindingStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c new file mode 100644 index 0000000000..b8645a2771 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c @@ -0,0 +1,517 @@ +/** @file
+ Platform PCI Bus Initialization Driver.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include "Library/DxeServicesTableLib.h"
+#include "PciBus.h"
+#include "Guid/PciLanInfo.h"
+
+extern VOID *mPciLanInfo;
+extern UINTN mPciLanCount;
+
+extern EFI_HANDLE mImageHandle;
+extern SYSTEM_CONFIGURATION mSystemConfiguration;
+
+VOID *mPciRegistration;
+
+#define NCR_VENDOR_ID 0x1000
+#define ATI_VENDOR_ID 0x1002
+#define INTEL_VENDOR_ID 0x8086
+#define ATI_RV423_ID 0x5548
+#define ATI_RV423_ID2 0x5d57
+#define ATI_RV380_ID 0x3e50
+#define ATI_RV370_ID 0x5b60
+#define SI_VENDOR_ID 0x1095
+#define SI_SISATA_ID 0x3114
+#define SI_SIRAID_PCIUNL 0x40
+#define INTEL_82573E_IDER 0x108D
+
+typedef struct {
+ UINT8 ClassCode;
+ UINT8 SubClassCode;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+} BAD_DEVICE_TABLE;
+
+BAD_DEVICE_TABLE BadDeviceTable[] = {
+ {(UINT8) PCI_CLASS_MASS_STORAGE, (UINT8) PCI_CLASS_MASS_STORAGE_SCSI, (UINT16) NCR_VENDOR_ID, (UINT16) 0xffff}, // Any NCR cards
+ {(UINT8) PCI_CLASS_MASS_STORAGE, (UINT8) PCI_CLASS_MASS_STORAGE_IDE, (UINT16) INTEL_VENDOR_ID, (UINT16) INTEL_82573E_IDER}, // Intel i82573E Tekoa GBit Lan IDE-R
+ {(UINT8) 0xff, (UINT8) 0xff, (UINT16) 0xffff, (UINT16) 0xffff}
+};
+
+
+EFI_STATUS
+PciBusDriverHook (
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT FilterEvent;
+
+ //
+ // Register for callback to PCI I/O protocol
+ //
+ Status = gBS->CreateEvent (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ PciBusEvent,
+ NULL,
+ &FilterEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register for protocol notifications on this event
+ //
+ Status = gBS->RegisterProtocolNotify (
+ &gEfiPciIoProtocolGuid,
+ FilterEvent,
+ &mPciRegistration
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+
+VOID
+InitBadBars(
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT16 VendorId,
+ IN UINT16 DeviceId
+ )
+{
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
+ UINT64 BaseAddress = 0;
+ UINT64 TempBaseAddress = 0;
+ UINT8 RevId = 0;
+ UINT32 Bar;
+ UINT64 IoSize;
+ UINT64 MemSize;
+ UINTN MemSizeBits;
+
+ PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
+ switch (VendorId) {
+ case ATI_VENDOR_ID:
+ //
+ // ATI fix-ups. At this time all ATI cards in BadDeviceTable
+ // have same problem in that OPROM BAR needs to be increased.
+ //
+ Bar = 0x30 ;
+ //
+ // Get original BAR address
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &BaseAddress
+ );
+ //
+ // Find BAR size
+ //
+ TempBaseAddress = 0xffffffff;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+
+ TempBaseAddress &= 0xfffffffe;
+ MemSize = 1;
+ while ((TempBaseAddress & 0x01) == 0) {
+ TempBaseAddress = TempBaseAddress >> 1;
+ MemSize = MemSize << 1;
+ }
+
+ //
+ // Free up allocated memory memory and re-allocate with increased size.
+ //
+ Status = gDS->FreeMemorySpace (
+ BaseAddress,
+ MemSize
+ );
+
+ //
+ // Force new alignment
+ //
+ MemSize = 0x8000000;
+ MemSizeBits = 28;
+
+ Status = gDS->AllocateMemorySpace (
+ EfiGcdAllocateAnySearchBottomUp,
+ EfiGcdMemoryTypeMemoryMappedIo,
+ MemSizeBits, // Alignment
+ MemSize,
+ &BaseAddress,
+ mImageHandle,
+ NULL
+ );
+
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &BaseAddress
+ );
+
+ break;
+ case NCR_VENDOR_ID:
+#define MIN_NCR_IO_SIZE 0x800
+#define NCR_GRAN 11 // 2**11 = 0x800
+ //
+ // NCR SCSI cards like 8250S lie about IO needed. Assign as least 0x80.
+ //
+ for (Bar = 0x10; Bar < 0x28; Bar+= 4) {
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &BaseAddress
+ );
+
+ if (BaseAddress && 0x01) {
+ TempBaseAddress = 0xffffffff;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ TempBaseAddress &= 0xfffffffc;
+ IoSize = 1;
+ while ((TempBaseAddress & 0x01) == 0) {
+ TempBaseAddress = TempBaseAddress >> 1;
+ IoSize = IoSize << 1;
+ }
+ if (IoSize < MIN_NCR_IO_SIZE) {
+ Status = gDS->FreeIoSpace (
+ BaseAddress,
+ IoSize
+ );
+
+ Status = gDS->AllocateIoSpace (
+ EfiGcdAllocateAnySearchTopDown,
+ EfiGcdIoTypeIo,
+ NCR_GRAN, // Alignment
+ MIN_NCR_IO_SIZE,
+ &BaseAddress,
+ mImageHandle,
+ NULL
+ );
+ TempBaseAddress = BaseAddress + 1;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ }
+ }
+ }
+
+ break;
+
+ case INTEL_VENDOR_ID:
+ if (DeviceId == INTEL_82573E_IDER) {
+ //
+ // Tekoa i82573E IDE-R fix-ups. At this time A2 step and earlier parts do not
+ // support any BARs except BAR0. Other BARS will actualy map to BAR0 so disable
+ // them all for Control Blocks and Bus mastering ops as well as Secondary IDE
+ // Controller.
+ // All Tekoa A2 or earlier step chips for now.
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_REVISION_ID_OFFSET,
+ 1,
+ (VOID *) &RevId
+ );
+ if (RevId <= 0x02) {
+ for (Bar = 0x14; Bar < 0x24; Bar+= 4) {
+ //
+ // Maybe want to clean this up a bit later but for now just clear out the secondary
+ // Bars don't worry aboyut freeing up thge allocs.
+ //
+ TempBaseAddress = 0x0;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ } // end for
+ } else {
+ //
+ // Tekoa A3 or above:
+ // Clear bus master base address (PCI register 0x20)
+ // since Tekoa does not fully support IDE Bus Mastering
+ //
+ TempBaseAddress = 0x0;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0x20,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return;
+}
+
+
+VOID
+ProgramPciLatency (
+ IN EFI_PCI_IO_PROTOCOL *PciIo
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Program Master Latency Timer
+ //
+ if (mSystemConfiguration.PciLatency != 0) {
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_LATENCY_TIMER_OFFSET,
+ 1,
+ &mSystemConfiguration.PciLatency
+ );
+ }
+
+ return;
+}
+
+
+/**
+ During S5 shutdown, we need to program PME in all LAN devices.
+ Here we identify LAN devices and save their bus/dev/func.
+
+**/
+VOID
+SavePciLanAddress (
+ IN EFI_PCI_IO_PROTOCOL *PciIo
+ )
+{
+ EFI_STATUS Status;
+ UINTN PciSegment,
+ PciBus,
+ PciDevice,
+ PciFunction;
+ VOID *NewBuffer;
+ PCI_LAN_INFO *x;
+
+ Status = PciIo->GetLocation (
+ PciIo,
+ &PciSegment,
+ &PciBus,
+ &PciDevice,
+ &PciFunction
+ );
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ mPciLanCount ++;
+ Status = gBS->AllocatePool (
+ EfiBootServicesData,
+ mPciLanCount * sizeof (PCI_LAN_INFO),
+ (VOID **) &NewBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ if (mPciLanCount > 1) {
+ //
+ // copy old data into new, larger buffer
+ //
+ gBS->CopyMem (
+ NewBuffer,
+ mPciLanInfo,
+ (mPciLanCount - 1) * sizeof (PCI_LAN_INFO)
+ );
+ //
+ // free the old memory buffer
+ //
+ gBS->FreePool (mPciLanInfo);
+
+ }
+
+ //
+ // init the new entry
+ //
+ x = (PCI_LAN_INFO *) NewBuffer + (mPciLanCount - 1);
+ x->PciBus = (UINT8) PciBus;
+ x->PciDevice = (UINT8) PciDevice;
+ x->PciFunction = (UINT8) PciFunction;
+
+ mPciLanInfo = NewBuffer;
+
+ return;
+}
+
+
+VOID
+EFIAPI
+PciBusEvent (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_IO_DEVICE *PciIoDevice;
+ UINT64 Supports;
+ UINTN Index;
+ UINT8 mCacheLineSize = 0x10;
+ UINTN Seg, Bus, Dev, Fun;
+
+ while (TRUE) {
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (
+ ByRegisterNotify,
+ NULL,
+ mPciRegistration,
+ &BufferSize,
+ &Handle
+ );
+
+ if (EFI_ERROR (Status)) {
+ //
+ // If no more notification events exist
+ //
+ return;
+ }
+
+ Status = gBS->HandleProtocol (
+ Handle,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+
+ PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
+ //
+ // Enable I/O for bridge so port 0x80 codes will come out
+ //
+ if (PciIoDevice->Pci.Hdr.VendorId == V_INTEL_VENDOR_ID) {
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationSupported,
+ 0,
+ &Supports
+ );
+
+ Supports &= EFI_PCI_DEVICE_ENABLE;
+ //
+ // Work around start, PMC command register IO enable(BIT0) will always read back as 0, though it supports IO
+ // so the attributes for IO will not be set, here we set it
+ //
+ Status = PciIo->GetLocation (PciIo, &Seg, &Bus, &Dev, &Fun);
+ if ((Seg ==0) && (Bus == 0) && (Dev == 13) && (Fun == 1)) {
+ Supports |= BIT0;
+ }
+ //
+ // Work around end.
+ //
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
+ break;
+ }
+
+ //
+ // Program PCI Latency Timer
+ //
+ ProgramPciLatency (PciIo);
+
+ //
+ // Program Cache Line Size to 64 bytes (0x10 DWORDs)
+ //
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_CACHELINE_SIZE_OFFSET,
+ 1,
+ &mCacheLineSize
+ );
+
+ //
+ // If PCI LAN device, save bus/dev/func info
+ // so we can program PME during S5 shutdown
+ //
+ if (PciIoDevice->Pci.Hdr.ClassCode[2] == PCI_CLASS_NETWORK) {
+ SavePciLanAddress (PciIo);
+ break;
+ }
+
+ //
+ // Workaround for cards with bad BARs
+ //
+ Index = 0;
+ while (BadDeviceTable[Index].ClassCode != 0xff) {
+ if (BadDeviceTable[Index].DeviceId == 0xffff) {
+ if ((PciIoDevice->Pci.Hdr.ClassCode[2] == BadDeviceTable[Index].ClassCode) &&
+ (PciIoDevice->Pci.Hdr.ClassCode[1] == BadDeviceTable[Index].SubClassCode) &&
+ (PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId)) {
+ InitBadBars (PciIo, BadDeviceTable[Index].VendorId, BadDeviceTable[Index].DeviceId);
+ }
+ } else {
+ if ((PciIoDevice->Pci.Hdr.ClassCode[2] == BadDeviceTable[Index].ClassCode) &&
+ (PciIoDevice->Pci.Hdr.ClassCode[1] == BadDeviceTable[Index].SubClassCode) &&
+ (PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId) &&
+ (PciIoDevice->Pci.Hdr.DeviceId == BadDeviceTable[Index].DeviceId)) {
+
+ InitBadBars (PciIo, BadDeviceTable[Index].VendorId, BadDeviceTable[Index].DeviceId);
+ }
+ }
+ ++Index;
+ }
+ break;
+ }
+
+ return;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c new file mode 100644 index 0000000000..e034e6ed82 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c @@ -0,0 +1,877 @@ +/** @file
+ Platform Initialization Driver.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include "Platform.h"
+
+#include <Library/S3BootScriptLib.h>
+#include <Library/PciLib.h>
+#include <Library/SideBandLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/PlatformSecureDefaultsLib.h>
+#include <Library/SteppingLib.h>
+#include <Library/DevicePathLib.h>
+#include <Protocol/UsbPolicy.h>
+#include <Protocol/TpmMp.h>
+#include <Protocol/SeCPlatformPolicy.h>
+#include <Protocol/SeCOperation.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Guid/DataHubRecords.h>
+#include <Guid/PciLanInfo.h>
+#include <Guid/BxtVariable.h>
+#include <Guid/EventGroup.h>
+#include <Guid/AuthenticatedVariableFormat.h>
+#include <PlatformBootMode.h>
+#include <Library/HeciMsgLib.h>
+#include <Ppi/SiPolicyPpi.h>
+#include <Library/GpioLib.h>
+
+#if (ENBDT_PF_ENABLE == 1) //BXTP
+ #include <Library/PlatformCmosLib.h>
+#endif
+
+extern EFI_GUID gEfiBootMediaHobGuid;
+
+EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
+SYSTEM_CONFIGURATION mSystemConfiguration;
+UINT32 mSetupVariableAttributes;
+EFI_HANDLE mImageHandle;
+BOOLEAN mMfgMode = FALSE;
+UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
+EFI_PLATFORM_INFO_HOB mPlatformInfo;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_EVENT mEndOfDxeEvent;
+EFI_EVENT mReadyToBootEvent;
+UINT32 mSubsystemVidDid;
+UINTN mPciLanCount = 0;
+VOID *mPciLanInfo = NULL;
+EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};
+BOOLEAN mPMCReadyToBootFirstTime = TRUE;
+EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;
+
+BXT_GPIO_PAD_INIT SdcardGpio[] =
+{ //
+ // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L, Inverted,GPI_ROUT,IOSstae, IOSTerm, MMIO_Offset, Community
+ //
+ BXT_GPIO_PAD_CONF (L"GPIO_177 SDCARD_CD_B", M0, GPI , GPIO_D, NA , Edge ,Wake_Disabled, P_20K_H, NA , NA ,TxDRxE , NA , 0x04a8 , SOUTHWEST) //SD Card Wake Int
+};
+
+VOID
+EFIAPI
+PMCReadyToBoot (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 PciBar0RegOffset;
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
+ EFI_GUID SSRAMBASEGuid = { 0x9cfa1ece, 0x4488, 0x49be, { 0x9a, 0x4b, 0xe9, 0xb5, 0x11, 0x82, 0x65, 0x77 } };
+ UINT32 Data32;
+
+ if (mPMCReadyToBootFirstTime == FALSE) {
+ return;
+ }
+ mPMCReadyToBootFirstTime = FALSE;
+
+ Status = gBS->LocateProtocol (
+ &gEfiGlobalNvsAreaProtocolGuid,
+ NULL,
+ (VOID **) &GlobalNvsArea
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // Save PMC IPC1 Bar0 (PcdPmcIpc1BaseAddress0) to GNVS and size is 0x2000(8KB).
+ //
+ PciBar0RegOffset = (UINT32) MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_PMC_IPC1, PCI_FUNCTION_NUMBER_PMC_IPC1, R_PMC_IPC1_BASE);
+ DEBUG ((DEBUG_INFO, " IPC1 BAR0 MMIO = %x \n ", (MmioRead32 (PciBar0RegOffset) & 0xFFFFE000)));
+ GlobalNvsArea->Area->IPCBar0Address = (MmioRead32 (PciBar0RegOffset) & 0xFFFFE000);
+ GlobalNvsArea->Area->IPCBar0Length = 0x2000;
+ //
+ // Save PMC IPC1 Bar1 (PcdPmcIpc1BaseAddress0) to GNVS and size is 0x2000(8KB).
+ //
+ PciBar0RegOffset = (UINT32) MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_PMC_IPC1, (PCI_FUNCTION_NUMBER_PMC_SSRAM), 0x10);
+ DEBUG ((DEBUG_INFO, " SSRAM MMIO Bar = %x \n ", MmioRead32 (PciBar0RegOffset) & 0xFFFFFFF0));
+ GlobalNvsArea->Area->SSRAMBar0Address = MmioRead32 (PciBar0RegOffset) & 0xFFFFFFF0;
+ GlobalNvsArea->Area->SSRAMBar0Length = 0x2000;
+
+ Status = gRT->SetVariable (
+ L"SSRAMBASE",
+ &SSRAMBASEGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof (UINT32),
+ &(GlobalNvsArea->Area->SSRAMBar0Address)
+ );
+
+ SideBandAndThenOr32 (
+ 0xC6,
+ 0x0300 + 0x001C,
+ 0xFFFFFFFF,
+ (BIT1 | BIT0)
+ );
+
+ SideBandAndThenOr32 (
+ 0xC6,
+ 0x0300 + 0x0038,
+ 0xFFFFFFFF,
+ BIT0
+ );
+
+ //
+ // Switch the PMC SSRAM to ACPI mode.
+ //
+ SideBandAndThenOr32 (
+ 0x95,
+ 0x208,
+ 0xFFFFFFFF,
+ BIT0 | B_PMC_IOSF2OCP_PCICFGCTRL3_BAR1_DISABLE3
+ );
+
+ //
+ // Program PMC ACPI IRQ.
+ //
+ Data32 = SideBandRead32 (0x95, 0x204);
+ Data32 |= BIT1;
+ Data32 |= 0x00028000;
+ SideBandWrite32 (0x95, 0x204, Data32);
+
+ Data32 = SideBandRead32 (0x95, 0x204);
+ DEBUG ((DEBUG_INFO, " PMC Interrupt value= %x \n ", Data32));
+
+ }
+}
+
+
+VOID
+EFIAPI
+InitPciDevPME (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+#ifdef SATA_SUPPORT
+ //
+ // Program SATA PME_EN
+ //
+ SataPciCfg32Or (R_SATA_PMCS, B_SATA_PMCS_PMEE);
+#endif
+}
+
+
+/**
+ SMI handler to enable ACPI mode
+ Dispatched on reads from APM port with value 0xA0
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+ SCI mode is then enabled.
+
+ Disable SW SMI Timer
+
+ Clear all ACPI event status and disable all ACPI events
+ Disable PM sources except power button
+ Clear status bits
+
+ Disable GPE0 sources
+ Clear status bits
+
+ Disable GPE1 sources
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+
+ @param[in] Event EFI Event Handle
+ @param[in] Context Pointer to Notify Context
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EnableAcpiCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINT8 OutputValue;
+ UINT32 SmiEn;
+ UINT16 Pm1Cnt;
+ UINT16 AcpiBaseAddr;
+
+ DEBUG ((DEBUG_INFO, "EnableAcpiCallback ++ (DXE)\n"));
+
+ //
+ // Read ACPI Base Address
+ //
+ AcpiBaseAddr = (UINT16) PcdGet16 (PcdScAcpiIoPortBaseAddress);
+
+ //
+ // Disable SW SMI Timer
+ //
+ SmiEn = IoRead32 (AcpiBaseAddr + R_SMI_EN);
+ SmiEn &= ~B_SMI_STS_SWSMI_TMR;
+ IoWrite32 (AcpiBaseAddr + R_SMI_EN, SmiEn);
+
+ //
+ // Disable PM sources except power button
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_PM1_EN, B_ACPI_PM1_EN_PWRBTN);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ OutputValue = RTC_ADDRESS_REGISTER_D;
+ IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, OutputValue);
+ OutputValue = 0x0;
+ OutputValue = IoRead8 (PCAT_RTC_DATA_REGISTER);
+
+ //
+ // Enable SCI
+ //
+ Pm1Cnt = IoRead16 (AcpiBaseAddr + R_ACPI_PM1_CNT);
+ Pm1Cnt |= B_ACPI_PM1_CNT_SCI_EN;
+ IoWrite16 (AcpiBaseAddr + R_ACPI_PM1_CNT, Pm1Cnt);
+}
+
+
+#if (ENBDT_PF_ENABLE == 1) //BXTP
+VOID
+EFIAPI
+CheckCmosBatteryLost (
+ VOID
+ )
+{
+ UINT8 Buffer8 = 0;
+
+ if (!CheckCmosBatteryStatus ()) {
+ Buffer8 = MmioRead8 (PMC_BASE_ADDRESS + R_PMC_GEN_PMCON_1);
+
+ //
+ // CMOS Battery then clear status
+ //
+ if (Buffer8 & B_PMC_GEN_PMCON_RTC_PWR_STS) {
+ Buffer8 &= ~B_PMC_GEN_PMCON_RTC_PWR_STS;
+ MmioWrite8 (PMC_BASE_ADDRESS + R_PMC_GEN_PMCON_1, Buffer8);
+ }
+ }
+}
+#endif //#if (ENBDT_PF_ENABLE == 1) //BXTP
+
+
+VOID
+PlatformScInitBeforeBoot (
+ VOID
+ )
+{
+ //
+ // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
+ //
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (SPI_BASE_ADDRESS + (R_SPI_OPMENU0)),
+ 1,
+ (VOID *) (UINTN) (SPI_BASE_ADDRESS + (R_SPI_OPMENU0))
+ );
+
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (SPI_BASE_ADDRESS + (R_SPI_OPMENU1)),
+ 1,
+ (VOID *) (UINTN) (SPI_BASE_ADDRESS + (R_SPI_OPMENU1))
+ );
+
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint16,
+ (UINTN) (SPI_BASE_ADDRESS + R_SPI_OPTYPE),
+ 1,
+ (VOID *) (UINTN) (SPI_BASE_ADDRESS + R_SPI_OPTYPE)
+ );
+
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint16,
+ (UINTN) (SPI_BASE_ADDRESS + R_SPI_PREOP),
+ 1,
+ (VOID *) (UINTN) (SPI_BASE_ADDRESS + R_SPI_PREOP)
+ );
+
+ return;
+}
+
+
+/**
+ Saves UART2 Base Address To Restore on S3 Resume Flows
+
+ @param[in] Event A pointer to the Event that triggered the callback.
+ @param[in] Context A pointer to private data registered with the callback function.
+
+**/
+VOID
+EFIAPI
+ConfigureUart2OnReadyToBoot (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Uart2BaseAddressRegister = 0;
+
+ //
+ // Save the UART2 BAR As It Will Need Restored Manually
+ // On S3 Resume to Match the Value Written to the DBG2 ACPI Table
+ //
+
+ Uart2BaseAddressRegister = MmPciAddress (
+ 0,
+ DEFAULT_PCI_BUS_NUMBER_SC,
+ PCI_DEVICE_NUMBER_LPSS_HSUART,
+ PCI_FUNCTION_NUMBER_LPSS_HSUART2,
+ R_LPSS_IO_BAR
+ );
+
+ mSystemConfiguration.Uart2KernelDebugBaseAddress = (UINT32) (MmioRead32 (Uart2BaseAddressRegister) & B_LPSS_IO_BAR_BA);
+
+ Status = gRT->SetVariable (
+ L"Setup",
+ &gEfiSetupVariableGuid,
+ mSetupVariableAttributes,
+ sizeof (SYSTEM_CONFIGURATION),
+ &mSystemConfiguration
+ );
+
+ ASSERT_EFI_ERROR (Status);
+}
+
+
+#if (ENBDT_PF_ENABLE == 1) //BXTP
+/**
+ This function handles PlatformInit task at the end of DXE
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the
+ Event.
+
+**/
+VOID
+EFIAPI
+EndofDxeCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+}
+#endif //BXTP
+
+
+VOID
+EFIAPI
+ReadyToBootFunction (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+ //
+ // Switch SD Card detect pin from native to GPI so OS can detect card insertion
+ // events.
+ //
+ DEBUG ((EFI_D_INFO, "%a(#%d) - Programming SD Card detect pin as GPI...\n", __FUNCTION__, __LINE__));
+
+ GpioPadConfigTable (sizeof (SdcardGpio) / sizeof (SdcardGpio[0]), SdcardGpio);
+
+ if (mPciLanInfo != NULL) {
+ //
+ // save LAN info to a variable
+ //
+ gRT->SetVariable (
+ L"PciLanInfo",
+ &gEfiPciLanInfoGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ mPciLanCount * sizeof (PCI_LAN_INFO),
+ mPciLanInfo
+ );
+
+ gBS->FreePool (mPciLanInfo);
+ mPciLanInfo = NULL;
+ }
+
+ return;
+}
+
+
+/**
+ Disable SecureBoot Configuration
+
+**/
+VOID
+EFIAPI
+DisableSecureBootCfg (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ CHAR16 *MfgTest = L"NULL";
+ UINT8 SecureBootCfg;
+ UINTN DataSize;
+
+ //
+ // create MFGTEST with attribute of NV,BS & RT ,Default value = NULL , This parameter is reserved for future USE.
+ //
+ Status = gRT->SetVariable (
+ L"MFGTEST",
+ &gMfgModeVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof (MfgTest),
+ MfgTest
+ );
+
+ DataSize = sizeof (UINT8);
+ Status = gRT->GetVariable (
+ EFI_SECURE_BOOT_ENABLE_NAME,
+ &gEfiSecureBootEnableDisableGuid,
+ NULL,
+ &DataSize,
+ &SecureBootCfg
+ );
+
+ if (SecureBootCfg) {
+ SecureBootCfg = 0x00; //Disable SecureBoot
+ Status = gRT->SetVariable (
+ EFI_SECURE_BOOT_ENABLE_NAME,
+ &gEfiSecureBootEnableDisableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ sizeof (UINT8),
+ &SecureBootCfg
+ );
+
+ gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
+ }
+}
+
+
+/**
+ Initializes manufacturing and config mode setting.
+
+**/
+VOID
+InitMfgAndConfigModeStateVar (
+ VOID
+ )
+{
+ EFI_PLATFORM_SETUP_ID *BootModeBuffer;
+ VOID *HobList;
+
+ HobList = GetFirstGuidHob (&gEfiPlatformBootModeGuid);
+ if (HobList != NULL) {
+ BootModeBuffer = GET_GUID_HOB_DATA (HobList);
+ //
+ // Check if in Manufacturing mode
+ //
+ if (!CompareMem (&BootModeBuffer->SetupName, MANUFACTURE_SETUP_NAME, StrSize (MANUFACTURE_SETUP_NAME))) {
+ mMfgMode = TRUE;
+ DisableSecureBootCfg ();
+ }
+ }
+}
+
+
+/**
+ Initializes platform boot mode setting.
+
+**/
+VOID
+InitPlatformBootMode (
+ VOID
+ )
+{
+ EFI_PLATFORM_SETUP_ID *BootModeBuffer;
+ VOID *HobList;
+
+ HobList = GetFirstGuidHob (&gEfiPlatformBootModeGuid);
+
+ if (HobList != NULL) {
+ BootModeBuffer = GET_GUID_HOB_DATA (HobList);
+ mPlatformBootMode = BootModeBuffer->PlatformBootMode;
+ }
+
+}
+
+
+VOID
+InitPlatformUsbPolicy (
+ VOID
+ )
+{
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+
+ Handle = NULL;
+
+ mUsbPolicyData.Version = (UINT8) USB_POLICY_PROTOCOL_REVISION_2;
+ mUsbPolicyData.UsbOperationMode = HIGH_SPEED;
+ mUsbPolicyData.LegacyKBEnable = LEGACY_KB_EN;
+ mUsbPolicyData.LegacyMSEnable = LEGACY_MS_EN;
+ mUsbPolicyData.LegacyUsbEnable = mSystemConfiguration.UsbLegacy;
+ mUsbPolicyData.CodeBase = ICBD_CODE_BASE;
+
+ //
+ // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
+ //
+ mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;
+
+ //
+ // Some platform need legacy free, 0 = LEGACY_FREE_UN_SUPP
+ //
+ mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;
+
+ //
+ // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
+ //
+ mUsbPolicyData.CodeBase = (UINT8) ICBD_CODE_BASE;
+
+
+ //
+ // Set for reduce usb post time
+ //
+ mUsbPolicyData.UsbTimeTue = 0x00;
+ mUsbPolicyData.InternelHubExist = 0x01;
+ mUsbPolicyData.EnumWaitPortStableStall = 100;
+
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gUsbPolicyGuid,
+ EFI_NATIVE_INTERFACE,
+ &mUsbPolicyData
+ );
+ ASSERT_EFI_ERROR (Status);
+
+}
+
+
+VOID
+InitSeC (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ DXE_SEC_POLICY_PROTOCOL *SeCPlatformPolicy;
+ EFI_PEI_HOB_POINTERS HobPtr;
+ MBP_CURRENT_BOOT_MEDIA *BootMediaData;
+ SEC_OPERATION_PROTOCOL *SeCOp;
+
+ DEBUG ((DEBUG_INFO, "InitSeC ++\n"));
+
+ Status = gBS->LocateProtocol (&gDxePlatformSeCPolicyGuid, NULL, (VOID **) &SeCPlatformPolicy);
+
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ SeCPlatformPolicy->SeCConfig.EndOfPostEnabled = mSystemConfiguration.SeCEOPEnable;
+ DEBUG ((DEBUG_INFO, "InitSeC mDxePlatformSeCPolicy->SeCConfig.EndOfPostEnabled %x %x\n", SeCPlatformPolicy->SeCConfig.EndOfPostEnabled,mSystemConfiguration.SeCEOPEnable));
+
+ //
+ // Get Boot Media Hob, save to SystemConfigData for next S3 cycle.
+ //
+ DEBUG ((DEBUG_INFO, "CSE Boot Device record is %x from SystemConfigData\n", mSystemConfiguration.CseBootDevice));
+ HobPtr.Guid = GetFirstGuidHob (&gEfiBootMediaHobGuid);
+ ASSERT (HobPtr.Guid != NULL);
+ BootMediaData = (MBP_CURRENT_BOOT_MEDIA *) GET_GUID_HOB_DATA (HobPtr.Guid);
+
+ if (mSystemConfiguration.CseBootDevice != BootMediaData->PhysicalData) {
+ mSystemConfiguration.CseBootDevice= (UINT8) BootMediaData->PhysicalData;
+ DEBUG ((DEBUG_INFO, "Current CSE Boot Device is %x. Update to SystemConfigData\n", BootMediaData->PhysicalData));
+
+ Status = gRT->SetVariable (
+ L"Setup",
+ &gEfiSetupVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ sizeof (SYSTEM_CONFIGURATION),
+ &mSystemConfiguration
+ );
+ }
+
+ Status = gBS->LocateProtocol (
+ &gEfiSeCOperationProtocolGuid,
+ NULL,
+ (VOID **) &SeCOp
+ );
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ Status = SeCOp->PerformSeCOperation (SEC_OP_CHECK_UNCONFIG);
+ Status = SeCOp->PerformSeCOperation (SEC_OP_CHECK_HMRFPO);
+
+}
+
+
+VOID
+InitPlatformResolution (
+ VOID
+ )
+{
+ PANEL_RESOLUTION PanelResolution[] = {
+ 0, 0, 0, // Native Mode, Find the highest resolution which GOP supports.
+ 1, 640, 480,
+ 2, 800, 600,
+ 3, 1024, 768,
+ 4, 1280, 1024,
+ 5, 1366, 768,
+ 6, 1680, 1050,
+ 7, 1920, 1200,
+ 8, 1280, 800,
+ };
+
+ //
+ // Set the Panel Resolution.
+ //
+ PcdSet32S (PcdVideoHorizontalResolution, PanelResolution[mSystemConfiguration.IgdFlatPanel].HorizontalResolution);
+ PcdSet32S (PcdVideoVerticalResolution, PanelResolution[mSystemConfiguration.IgdFlatPanel].VerticalResolution);
+}
+
+
+/**
+ This is the standard EFI driver point for the Driver. This
+ driver is responsible for setting up any platform specific policy or
+ initialization information.
+
+ @param[in] ImageHandle Handle for the image of this driver.
+ @param[in] SystemTable Pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS Policy decisions set.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatform (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN VarSize;
+ EFI_EVENT EfiExitBootServicesEvent;
+ EFI_HOB_GUID_TYPE *FdoEnabledGuidHob = NULL;
+ EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
+ EFI_PEI_HOB_POINTERS Hob;
+
+ mImageHandle = ImageHandle;
+
+ VarSize = sizeof (EFI_PLATFORM_INFO_HOB);
+ Status = gRT->GetVariable(
+ L"PlatformInfo",
+ &gEfiBxtVariableGuid,
+ NULL,
+ &VarSize,
+ &mPlatformInfo
+ );
+
+ InitMfgAndConfigModeStateVar (); // Initialize Product Board ID variable
+ InitPlatformBootMode ();
+
+ VarSize = 0;
+ Status = gRT->GetVariable (
+ L"db",
+ &gEfiImageSecurityDatabaseGuid,
+ NULL,
+ &VarSize,
+ NULL
+ );
+
+ VarSize = 0;
+ Status = gRT->GetVariable (
+ L"dbx",
+ &gEfiImageSecurityDatabaseGuid,
+ NULL,
+ &VarSize,
+ NULL
+ );
+
+
+ VarSize = 0;
+ Status = gRT->GetVariable (
+ L"KEK",
+ &gEfiGlobalVariableGuid,
+ NULL,
+ &VarSize,
+ NULL
+ );
+
+ VarSize = 0;
+ Status = gRT->GetVariable (
+ L"PK",
+ &gEfiGlobalVariableGuid,
+ NULL,
+ &VarSize,
+ NULL
+ );
+
+ VarSize = sizeof (SYSTEM_CONFIGURATION);
+ Status = gRT->GetVariable (
+ L"Setup",
+ &gEfiSetupVariableGuid,
+ &mSetupVariableAttributes,
+ &VarSize,
+ &mSystemConfiguration
+ );
+
+ Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (Hob.Raw != NULL);
+ PlatformInfoHob = GET_GUID_HOB_DATA (Hob.Raw);
+
+ mSystemConfiguration.BoardId = PlatformInfoHob->BoardId;
+
+ if (mSystemConfiguration.PlatformSettingEn == 0) {
+ if (PlatformInfoHob->PmicVersion == 0) {
+ mSystemConfiguration.EnableRenderStandby = 0;
+ }
+ mSystemConfiguration.PlatformSettingEn = 1;
+ }
+
+ mSystemConfiguration.PmicSetupDefault = 0;
+ if (PlatformInfoHob->PmicVersion == 0) {
+ mSystemConfiguration.PmicSetupDefault = 1;
+ mSystemConfiguration.MaxPkgCState = 0;
+ }
+
+ Status = gRT->SetVariable (
+ L"Setup",
+ &gEfiSetupVariableGuid,
+ mSetupVariableAttributes,
+ VarSize,
+ &mSystemConfiguration
+ );
+
+ ASSERT_EFI_ERROR (Status);
+
+ Status = EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ ReadyToBootFunction,
+ NULL,
+ &mReadyToBootEvent
+ );
+
+ //
+ // Create a ReadyToBoot Event to run the PME init process
+ //
+ Status = EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ InitPciDevPME,
+ NULL,
+ &mReadyToBootEvent
+ );
+
+ //
+ // Configure UART2 at ReadyToBoot if kernel debug is enabled (setup for S3 resume)
+ //
+ if (GetBxtSeries () == BxtP && mSystemConfiguration.OsDbgEnable) {
+ Status = EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ ConfigureUart2OnReadyToBoot,
+ NULL,
+ &mReadyToBootEvent
+ );
+ }
+
+ //
+ // Initialize BXT Platform Policy
+ // SiPolicy is consumed by HSTI Silicon driver
+ //
+ InitSiPolicy ();
+
+ ReportStatusCodeEx (
+ EFI_PROGRESS_CODE,
+ EFI_COMPUTING_UNIT_CHIPSET | EFI_CHIPSET_PC_DXE_NB_INIT,
+ 0,
+ &gEfiCallerIdGuid,
+ NULL,
+ NULL,
+ 0
+ );
+ InitPlatformSaPolicy (&mSystemConfiguration);
+
+ //
+ // Dis-arm RTC Alarm Interrupt
+ //
+ IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);
+ IoWrite8 (PCAT_RTC_DATA_REGISTER, IoRead8 (PCAT_RTC_DATA_REGISTER) & ~B_RTC_ALARM_INT_ENABLE);
+
+ InitPlatformIdePolicy ();
+ InitPlatformUsbPolicy ();
+ InitSioPlatformPolicy ();
+ InitializeClockRouting ();
+ InitTcoReset ();
+
+ InitPlatformResolution ();
+ //
+ // Install PCI Bus Driver Hook
+ //
+ PciBusDriverHook ();
+ PlatformScInitBeforeBoot ();
+ InitSeC ();
+
+ FdoEnabledGuidHob = GetFirstGuidHob (&gFdoModeEnabledHobGuid);
+ if (FdoEnabledGuidHob != NULL) {
+ //
+ // Secure boot must be disabled in Flash Descriptor Override (FDO) boot
+ //
+ EnableCustomMode ();
+ DeleteKeys ();
+ }
+
+#if (ENBDT_PF_ENABLE == 1) //BXTP
+ CheckCmosBatteryLost ();
+
+#ifdef SENSOR_INFO_VAR_SUPPORT
+ InitializeSensorInfoVariable (); // Initialize Sensor Info variable
+#endif
+ //
+ // Performing PlatformInitEndOfDxe after the gEfiEndOfDxeEventGroup is signaled.
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ EndofDxeCallback,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &mEndOfDxeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+#endif // #if (ENBDT_PF_ENABLE == 1) //BXTP
+
+ //
+ // IPC1 and SRAM update before boot
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ PMCReadyToBoot,
+ NULL,
+ &gEfiEventExitBootServicesGuid,
+ &EfiExitBootServicesEvent
+ );
+
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ EnableAcpiCallback,
+ NULL,
+ &gEfiEventExitBootServicesGuid,
+ &EfiExitBootServicesEvent
+ );
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.h b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.h new file mode 100644 index 0000000000..843d912bce --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.h @@ -0,0 +1,262 @@ +/** @file
+ Header file for Platform Initialization Driver.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_DRIVER_H
+#define _PLATFORM_DRIVER_H
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Framework/FrameworkInternalFormRepresentation.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/FrameworkFormCallback.h>
+#include <Protocol/CpuIo.h>
+#include <Protocol/BootScriptSave.h>
+#include <Protocol/DataHub.h>
+#include <Protocol/PciIo.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/BoardFeatures.h>
+#include <Guid/SetupVariable.h>
+#include <Guid/PlatformInfo.h>
+#include <IndustryStandard/Pci22.h>
+#include <ScAccess.h>
+#include <SaAccess.h>
+#include <CMOSMap.h>
+#include <PlatformBaseAddresses.h>
+#include <SetupMode.h>
+#include <PlatformBootMode.h>
+
+//
+// Internal (Locoal) Header files
+//
+#include "Configuration.h"
+
+#define _EFI_H_ //skip efi.h
+
+#define PCAT_RTC_ADDRESS_REGISTER 0x74
+#define PCAT_RTC_DATA_REGISTER 0x75
+
+#define RTC_ADDRESS_REGISTER_A 0x0A
+#define RTC_ADDRESS_REGISTER_B 0x0B
+#define RTC_ADDRESS_REGISTER_C 0x0C
+#define RTC_ADDRESS_REGISTER_D 0x0D
+
+#define B_RTC_ALARM_INT_ENABLE 0x20
+#define B_RTC_ALARM_INT_STATUS 0x20
+
+//
+// Platform driver GUID
+//
+#define EFI_PLATFORM_DRIVER_GUID \
+ { 0x056E7324, 0xA718, 0x465b, 0x9A, 0x84, 0x22, 0x8F, 0x06, 0x64, 0x2B, 0x4F }
+
+#define EFI_SECTION_STRING 0x1C
+#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#define PREFIX_BLANK 0x04
+
+#pragma pack(1)
+
+typedef UINT64 EFI_BOARD_FEATURES;
+typedef UINT16 STRING_REF;
+typedef UINT16 EFI_FORM_LABEL;
+
+typedef struct {
+ CHAR8 AaNumber[7];
+ UINT8 BoardId;
+ EFI_BOARD_FEATURES Features;
+ UINT16 SubsystemDeviceId;
+ UINT16 AudioSubsystemDeviceId;
+ UINT64 AcpiOemTableId;
+} BOARD_ID_DECODE;
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FORM_ROUTINE) (
+ SYSTEM_CONFIGURATION *SetupBuffer
+ );
+
+typedef struct {
+ CHAR16 *OptionString; ///< Passed in string to generate a token for in a truly dynamic form creation
+ STRING_REF StringToken; ///< This is used when creating a single op-code without generating a StringToken (have one already)
+ UINT16 Value;
+ UINT8 Flags;
+ UINT16 Key;
+} IFR_OPTION;
+
+typedef struct {
+ UINT8 Number;
+ UINT32 HorizontalResolution;
+ UINT32 VerticalResolution;
+} PANEL_RESOLUTION;
+
+#pragma pack()
+
+//
+// Prototypes
+//
+/**
+ Saves UART2 Base Address To Restore on S3 Resume Flows
+
+ @param[in] Event A pointer to the Event that triggered the callback.
+ @param[in] Context A pointer to private data registered with the callback function.
+
+**/
+VOID
+EFIAPI
+ConfigureUart2OnReadyToBoot (
+ EFI_EVENT Event,
+ VOID *Context
+ );
+
+//
+// Prototypes defined in Platform.c start
+//
+VOID
+EFIAPI
+ReadyToBootFunction (
+ EFI_EVENT Event,
+ VOID *Context
+ );
+
+UINT8
+ReadCmosBank1Byte (
+ IN EFI_CPU_IO2_PROTOCOL *CpuIo,
+ IN UINT8 Index
+ );
+
+VOID
+WriteCmosBank1Byte (
+ IN EFI_CPU_IO2_PROTOCOL *CpuIo,
+ IN UINT8 Index,
+ IN UINT8 Data
+ );
+
+//
+// Prototypes defined in BoardId.c
+//
+VOID
+InitializeBoardId (
+ );
+
+//
+// Prototypes defined in PciDevice.c
+//
+EFI_STATUS
+PciBusDriverHook (
+ );
+
+VOID
+EFIAPI
+PciBusEvent (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ );
+
+//
+// Prototypes defined in IdePlatformPolicy.c
+//
+VOID
+InitPlatformIdePolicy (
+ VOID
+ );
+
+//
+// Prototypes defined in ClockControl.c
+//
+VOID
+InitializeClockRouting (
+ VOID
+ );
+
+//
+// Prototypes defined in SlotConfig.c
+//
+VOID
+InitializeSlotInfo (
+ VOID
+ );
+
+//
+// Prototypes defined in SiPolicy.c
+//
+VOID
+InitSiPolicy (
+ VOID
+ );
+
+//
+// Prototypes defined in SensorVar.c
+//
+#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
+VOID
+InitializeSensorInfoVariable (
+ );
+#endif
+
+//
+// Prototypes defined in IchTcoReset.c
+//
+VOID
+InitTcoReset (
+ VOID
+ );
+
+//
+// Prototypes defined in SioPlatformPolicy.c
+//
+VOID
+InitPlatformSaPolicy (
+ SYSTEM_CONFIGURATION* SystemConfiguration
+ );
+
+VOID
+InitSioPlatformPolicy (
+ VOID
+ );
+
+//
+// Global externs
+//
+extern SYSTEM_CONFIGURATION mSystemConfiguration;
+
+extern EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
+extern UINT32 mSubsystemVidDid;
+
+extern UINT8 mBoardIdIndex;
+extern BOOLEAN mFoundAANum;
+extern EFI_BOARD_FEATURES mBoardFeatures;
+extern UINT16 mSubsystemDeviceId;
+extern UINT16 mSubsystemAudioDeviceId;
+extern CHAR8 BoardAaNumber[];
+
+extern BOARD_ID_DECODE mBoardIdDecodeTable[];
+extern UINTN mBoardIdDecodeTableSize;
+
+extern BOOLEAN mMfgMode;
+extern UINT32 mPlatformBootMode;
+
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf new file mode 100644 index 0000000000..e00588170e --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf @@ -0,0 +1,138 @@ +## @file
+# Component description file for platform DXE driver
+#
+# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxePlatform
+ FILE_GUID = 947558B9-64EB-4764-9F74-5EDBEA0C7481
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ PI_SPECIFICATION_VERSION = 0x0001000A
+ ENTRY_POINT = InitializePlatform
+
+[Sources.Common]
+ ClockControl.c
+ SiPolicy.c
+ Platform.c
+ IchRegTable.c
+ IdePlatformPolicy.c
+ SioPlatformPolicy.c
+ SaPlatformPolicy.c
+ PciDevice.c
+ IchTcoReset.c
+ SensorVar.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ BroxtonPlatformPkg/PlatformPkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ PlatformSecureDefaultsLib
+ DxeServicesTableLib
+ DebugLib
+ HiiLib
+ PrintLib
+ UefiLib
+ S3BootScriptLib
+ ReportStatusCodeLib
+ EfiRegTableLib
+ BiosIdLib
+ PcdLib
+ SideBandLib
+ DxePolicyUpdateLib
+ DxeSaPolicyLib
+ ConfigBlockLib
+ GpioLib
+ BasePlatformCmosLib
+
+[Guids]
+ gEfiBiosIdGuid
+ gEfiPlatformBootModeGuid
+ gEfiBoardFeaturesGuid
+ gItkDataVarGuid
+ gDmiDataGuid
+ gIdccDataHubGuid
+ gEfiPciLanInfoGuid
+ gEfiNormalSetupGuid
+ gEfiGlobalVariableGuid
+ gEfiEventExitBootServicesGuid
+ gEfiBxtVariableGuid
+ gMfgModeVariableGuid
+ gEfiSecureBootEnableDisableGuid
+ gEfiBootMediaHobGuid
+ gEfiSetupVariableGuid
+ gEfiEndOfDxeEventGroupGuid ## CONSUMES
+ gEfiImageSecurityDatabaseGuid
+ gEfiPlatformInfoGuid
+ gFdoModeEnabledHobGuid ## CONSUMES
+
+[Protocols]
+ gDxeSiPolicyProtocolGuid # PRODUCES
+ gEfiPciRootBridgeIoProtocolGuid # CONSUMES ## GUID
+ gEfiVariableArchProtocolGuid
+ gEfiVariableWriteArchProtocolGuid
+ gEfiHiiConfigAccessProtocolGuid
+ gEfiBootScriptSaveProtocolGuid
+ gEfiCpuIo2ProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiDiskInfoProtocolGuid
+ gEfiPs2PolicyProtocolGuid
+ gEfiIsaAcpiProtocolGuid
+ gEfiDataHubProtocolGuid
+ gEfiPciIoProtocolGuid
+ gEfiTpmMpDriverProtocolGuid
+ gEfiLpcWpce791PolicyProtocolGuid
+ gUsbPolicyGuid
+ gSaPolicyProtocolGuid
+ gEfiCk505ClockPlatformInfoGuid
+ gEfiLpcWpc83627PolicyProtocolGuid
+ gEfiUsbLegacyPlatformProtocolGuid
+ gEfiTcoResetProtocolGuid
+ gEfiWatchdogTimerDriverProtocolGuid
+ gEfiPlatformIdeInitProtocolGuid
+ gEfiGlobalNvsAreaProtocolGuid
+ gDxePlatformTdtPolicyGuid
+ gDxePlatformSeCPolicyGuid
+ gEfiSeCOperationProtocolGuid
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution
+ gEfiBxtTokenSpaceGuid.PcdScAcpiIoPortBaseAddress
+ gEfiBxtTokenSpaceGuid.PcdPmcSsramBaseAddress0
+ gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress
+ gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection
+
+[Depex]
+ gEfiPciRootBridgeIoProtocolGuid AND
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid AND
+ gEfiBootScriptSaveProtocolGuid AND
+ gEfiCpuIo2ProtocolGuid AND
+ gEfiGlobalNvsAreaProtocolGuid
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SaPlatformPolicy.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SaPlatformPolicy.c new file mode 100644 index 0000000000..68724427a8 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SaPlatformPolicy.c @@ -0,0 +1,42 @@ +/** @file
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include <Protocol/SaPolicy.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Library/DxeSaPolicyLib.h>
+#include <Library/DxeSaPolicyUpdateLib.h>
+#include <Library/ConfigBlockLib.h>
+
+VOID
+InitPlatformSaPolicy (
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ )
+{
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaPolicy;
+
+ //
+ // Call CreateSaDxeConfigBlocks to initialize SA DXE policy structure
+ // and get all Intel default policy settings.
+ //
+ Status = CreateSaDxeConfigBlocks (&SaPolicy);
+ DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR (Status);
+
+ UpdateDxeSaPolicy (SaPolicy, SystemConfiguration);
+
+ Status = SaInstallPolicyProtocol (SaPolicy);
+ ASSERT_EFI_ERROR (Status);
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SensorVar.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SensorVar.c new file mode 100644 index 0000000000..32c610cd0c --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SensorVar.c @@ -0,0 +1,104 @@ +/** @file
+ Initialization for the Sensor Info variable.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include "Guid/SensorInfoVariable.h"
+
+//
+// Sensor Information (board specific)
+//
+
+#define TEMPERATURE_SENSORS_COUNT 4
+#define VOLTAGE_SENSORS_COUNT 6
+#define FAN_SENSORS_COUNT 4
+#define FAN_CONTROLLERS_COUNT 3
+
+TYPEDEF_TEMP_SENSOR_SECTION(TEMPERATURE_SENSORS_COUNT);
+TYPEDEF_VOLT_SENSOR_SECTION(VOLTAGE_SENSORS_COUNT);
+TYPEDEF_FAN_SENSOR_SECTION(FAN_SENSORS_COUNT);
+TYPEDEF_FAN_CONTROLLER_SECTION(FAN_CONTROLLERS_COUNT);
+TYPEDEF_SENSOR_INFO_VAR;
+
+SENSOR_INFO_VAR mSensorInfoData = {
+ //
+ // Temperature Sensors
+ //
+ TEMPERATURE_SENSORS_COUNT,
+ {
+ { 0, 3, CPU_CORE_TEMPERATURE, TRUE },
+ { 0, 1, MOTHERBOARD_AMBIENT_TEMPERATURE, FALSE },
+ { 0, 2, VR_TEMPERATURE, FALSE },
+ { 0, 0, IOH_TEMPERATURE, FALSE }
+ },
+
+ //
+ // Voltage Sensors
+ //
+ VOLTAGE_SENSORS_COUNT,
+ {
+ { 0, 0, PLUS_12_VOLTS },
+ { 0, 1, PLUS_5_VOLTS },
+ { 0, 2, PLUS_3P3_VOLTS },
+ { 0, 3, MCH_VCC_VOLTAGE },
+ { 0, 4, CPU_1_VCCP_VOLTAGE },
+ { 0, 5, CPU_VTT_VOLTAGE }
+ },
+
+ //
+ // Fan Speed Sensors
+ //
+ FAN_SENSORS_COUNT,
+ {
+ { 0, 0, CPU_COOLING_FAN, FAN_4WIRE, 0 },
+ { 0, 1, AUX_COOLING_FAN, FAN_4WIRE, 1 },
+ { 0, 2, CHASSIS_INLET_FAN, FAN_3WIRE_VOLTAGE, 1 },
+ { 0, 3, CHASSIS_OUTLET_FAN, FAN_3WIRE_VOLTAGE, 2 }
+ },
+
+ //
+ // Fan Speed Controllers
+ //
+ FAN_CONTROLLERS_COUNT,
+ {
+ { 0, 0, CPU_COOLING_FAN, { 0, 0xff, 0xff, 0xff } },
+ { 0, 1, CHASSIS_COOLING_FAN, { 1, 2, 0xff, 0xff } },
+ { 0, 2, CHASSIS_COOLING_FAN, { 3, 0xff, 0xff, 0xff } }
+ }
+};
+
+
+/**
+ Write the Sensor Info variable if it does not already exist.
+
+**/
+VOID
+InitializeSensorInfoVariable (
+ )
+{
+ //
+ // Set the Sensor Info variable. If it already exists and the data matches,
+ // the variable driver will simply return without writing; otherwise, the
+ // driver will write the variable.
+ //
+ gRT->SetVariable (
+ gEfiSensorInfoVarNameWithPassword,
+ &gEfiSensorInfoVarGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof (SENSOR_INFO_VAR),
+ &mSensorInfoData
+ );
+
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SiPolicy.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SiPolicy.c new file mode 100644 index 0000000000..ca80487640 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SiPolicy.c @@ -0,0 +1,62 @@ +/** @file
+ Initilize Cpu DXE Platform Policy.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Guid/StatusCodeDataTypeId.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Protocol/SiPolicyProtocol.h>
+
+DXE_SI_POLICY_PROTOCOL mSiPolicyData = { 0 };
+
+/**
+ Initilize Intel Cpu DXE Platform Policy.
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+
+**/
+EFI_STATUS
+EFIAPI
+InitSiPolicy(
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE ImageHandle;
+
+ ImageHandle = NULL;
+ mSiPolicyData.Revision = DXE_SI_POLICY_PROTOCOL_REVISION_1;
+
+ //
+ // Install the DXE_SI_POLICY_PROTOCOL interface
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gDxeSiPolicyProtocolGuid,
+ &mSiPolicyData,
+ NULL
+ );
+
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SioPlatformPolicy.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SioPlatformPolicy.c new file mode 100644 index 0000000000..16b59121d8 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/SioPlatformPolicy.c @@ -0,0 +1,63 @@ +/** @file
+ Sio Platform Policy Setting.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformDxe.h"
+#include <Protocol/LpcWpc83627Policy.h>
+
+
+EFI_WPC83627_POLICY_PROTOCOL mSio83627PolicyData = {
+ { EFI_WPC83627_COM1_ENABLE, // Com1
+ EFI_WPC83627_LPT1_ENABLE, // Lpt1
+ EFI_WPC83627_FDD_DISABLE, // Floppy
+ EFI_WPC83627_FDD_WRITE_ENABLE, // FloppyWriteProtect
+ EFI_WPC83627_RESERVED_DEFAULT, // Port80
+ EFI_WPC83627_ECIR_DISABLE, // CIR
+ EFI_WPC83627_PS2_KBC_ENABLE, // Ps2Keyboard
+ EFI_WPC83627_RESERVED_DEFAULT, // Ps2Mouse
+ EFI_WPC83627_COM2_ENABLE, // Com2
+ EFI_WPC83627_COM3_ENABLE, // Com3
+ EFI_WPC83627_COM4_ENABLE, // Com4
+ EFI_WPC83627_RESERVED_DEFAULT, // Dac
+ 0x00 // Rsvd
+ },
+ LptModeEcp, // LptMode
+};
+
+
+/**
+ Publish the platform SIO policy setting.
+
+ @retval EFI_SUCCESS
+
+**/
+VOID
+InitSioPlatformPolicy(
+ )
+{
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+
+ Handle = NULL;
+
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiLpcWpc83627PolicyProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mSio83627PolicyData
+ );
+
+ ASSERT_EFI_ERROR (Status);
+}
+
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