diff options
| author | Michael Kinney <michael.d.kinney@intel.com> | 2015-12-15 19:23:57 +0000 |
|---|---|---|
| committer | mdkinney <mdkinney@Edk2> | 2015-12-15 19:23:57 +0000 |
| commit | b303605e1b7e113b4311daf161c6c3289350447b (patch) | |
| tree | 67bf068eb99ea84822f234b7194ee1084ee5455a /QuarkPlatformPkg/Library/PlatformHelperLib | |
| parent | 9b6bbcdbfdf5e54c6d1ed538ea8076d0858fb164 (diff) | |
| download | edk2-platforms-b303605e1b7e113b4311daf161c6c3289350447b.tar.xz | |
QuarkPlatformPkg: Add new package for Galileo boards
Changes for V4
==============
1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
from QuarkPlatformPkg commit to QuarkSocPkg commit
2) Fix incorrect license header in PlatformSecLibModStrs.uni
Changes for V3
==============
1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc
This is required because QuarkMin.dsc uses the emulated variable
driver that does not preserve any non-volatile UEFI variables
across reset. If the condition is met where the memory type
information variable needs to be updated, then the system will reset
every time the UEFI Shell is run. By setting this PCD to FALSE,
then reset action is disabled.
2) Move one binary file to QuarkSocBinPkg
3) Change RMU.bin FILE statements to INF statement in DSC FD region
to be compatible with PACKAGES_PATH search for QuarkSocBinPkg
Changes for V2
==============
1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
2) Configure PcdPciSerialParameters for PCI serial driver for Quark
3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM
4) Convert all UNI files to utf-8
5) Replace tabs with spaces and remove trailing spaces
6) Add License.txt
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'QuarkPlatformPkg/Library/PlatformHelperLib')
7 files changed, 1498 insertions, 0 deletions
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h b/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h new file mode 100644 index 0000000000..ce4aff1559 --- /dev/null +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h @@ -0,0 +1,57 @@ +/** @file
+Common header file shared by all source files in this component.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef __COMMON_HEADER_H_
+#define __COMMON_HEADER_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CapsuleLib.h>
+#include <Library/IntelQNCLib.h>
+#include <Platform.h>
+#include <PlatformBoards.h>
+#include <Pcal9555.h>
+#include <QNCAccess.h>
+#include <Library/QNCAccessLib.h>
+#include <IohAccess.h>
+
+#include <Library/PlatformHelperLib.h>
+
+//
+// Routines shared between souce modules in this component.
+//
+
+EFI_STATUS
+WriteFirstFreeSpiProtect (
+ IN CONST UINT32 PchRootComplexBar,
+ IN CONST UINT32 DirectValue,
+ IN CONST UINT32 BaseAddress,
+ IN CONST UINT32 Length,
+ OUT UINT32 *OffsetPtr
+ );
+
+VOID
+Pcal9555SetPortRegBit (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST UINT8 RegBase,
+ IN CONST BOOLEAN LogicOne
+ );
+
+#endif
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf b/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf new file mode 100644 index 0000000000..eeaa68792d --- /dev/null +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf @@ -0,0 +1,76 @@ +## @file
+# Library producing helper routines for this platform.
+#
+# Copyright (c) 2013 Intel Corporation.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxePlatformHelperLib
+ FILE_GUID = 02805010-2591-4ed3-827B-A218F34AE0D7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformHelperLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ PlatformHelperLib.c
+ PlatformHelperDxe.c
+ PlatformLeds.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ QuarkSocPkg/QuarkSocPkg.dec
+ QuarkPlatformPkg/QuarkPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ BaseMemoryLib
+ SerialPortLib
+ S3BootScriptLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ DxeServicesLib
+ HobLib
+ IntelQNCLib
+ I2cLib
+
+[Protocols]
+ gEfiSpiProtocolGuid
+ gEfiSmmSpiProtocolGuid
+ gEfiSmmBase2ProtocolGuid
+ gEdkiiVariableLockProtocolGuid ## CONSUMES
+
+[Guids]
+ gEfiGlobalVariableGuid
+ gEfiImageSecurityDatabaseGuid
+ gEfiQuarkCapsuleGuid
+ gQuarkVariableLockGuid ## CONSUMES
+ gEfiMemoryConfigDataGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize
+ gQuarkPlatformTokenSpaceGuid.PcdPkX509File
+ gQuarkPlatformTokenSpaceGuid.PcdKekX509File
+ gQuarkPlatformTokenSpaceGuid.PcdKekRsa2048File
+ gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf b/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf new file mode 100644 index 0000000000..97e21153d9 --- /dev/null +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf @@ -0,0 +1,51 @@ +## @file
+# Library producing helper routines for this platform.
+#
+# Copyright (c) 2013-2015 Intel Corporation.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiPlatformHelperLib
+ FILE_GUID = 024D3127-7B60-48f4-A6FE-726E19CD4CEB
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformHelperLib|PEIM PEI_CORE SEC
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ PlatformHelperLib.c
+ PlatformHelperPei.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ QuarkSocPkg/QuarkSocPkg.dec
+ QuarkPlatformPkg/QuarkPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ BaseMemoryLib
+ PeiServicesTablePointerLib
+ PeiServicesLib
+ SerialPortLib
+ QNCAccessLib
+ I2cLib
+
+[Pcd]
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c new file mode 100644 index 0000000000..9cfbc0716c --- /dev/null +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c @@ -0,0 +1,732 @@ +/** @file
+Implementation of helper routines for DXE environment.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/S3BootScriptLib.h>
+#include <Library/DxeServicesLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/I2cLib.h>
+#include <Protocol/SmmBase2.h>
+#include <Protocol/Spi.h>
+#include <Protocol/VariableLock.h>
+
+#include <Guid/MemoryConfigData.h>
+#include <Guid/QuarkVariableLock.h>
+
+#include "CommonHeader.h"
+
+#define FLASH_BLOCK_SIZE SIZE_4KB
+
+//
+// Global variables.
+//
+EFI_SPI_PROTOCOL *mPlatHelpSpiProtocolRef = NULL;
+
+//
+// Routines defined in other source modules of this component.
+//
+
+//
+// Routines local to this component.
+//
+
+//
+// Routines shared with other souce modules in this component.
+//
+
+BOOLEAN
+Pcal9555GetPortRegBit (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST UINT8 RegBase
+ )
+{
+ EFI_STATUS Status;
+ UINTN ReadLength;
+ UINTN WriteLength;
+ UINT8 Data[2];
+ EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;
+ EFI_I2C_ADDR_MODE I2cAddrMode;
+ UINT8 *RegValuePtr;
+ UINT8 GpioNumMask;
+ UINT8 SubAddr;
+
+ I2cDeviceAddr.I2CDeviceAddress = (UINTN) Pcal9555SlaveAddr;
+ I2cAddrMode = EfiI2CSevenBitAddrMode;
+
+ if (GpioNum < 8) {
+ SubAddr = RegBase;
+ GpioNumMask = (UINT8) (1 << GpioNum);
+ } else {
+ SubAddr = RegBase + 1;
+ GpioNumMask = (UINT8) (1 << (GpioNum - 8));
+ }
+
+ //
+ // Output port value always at 2nd byte in Data variable.
+ //
+ RegValuePtr = &Data[1];
+
+ //
+ // On read entry sub address at 2nd byte, on read exit output
+ // port value in 2nd byte.
+ //
+ Data[1] = SubAddr;
+ WriteLength = 1;
+ ReadLength = 1;
+ Status = I2cReadMultipleByte (
+ I2cDeviceAddr,
+ I2cAddrMode,
+ &WriteLength,
+ &ReadLength,
+ &Data[1]
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Adjust output port bit given callers request.
+ //
+ return ((*RegValuePtr & GpioNumMask) != 0);
+}
+
+VOID
+Pcal9555SetPortRegBit (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST UINT8 RegBase,
+ IN CONST BOOLEAN LogicOne
+ )
+{
+ EFI_STATUS Status;
+ UINTN ReadLength;
+ UINTN WriteLength;
+ UINT8 Data[2];
+ EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;
+ EFI_I2C_ADDR_MODE I2cAddrMode;
+ UINT8 *RegValuePtr;
+ UINT8 GpioNumMask;
+ UINT8 SubAddr;
+
+ I2cDeviceAddr.I2CDeviceAddress = (UINTN) Pcal9555SlaveAddr;
+ I2cAddrMode = EfiI2CSevenBitAddrMode;
+
+ if (GpioNum < 8) {
+ SubAddr = RegBase;
+ GpioNumMask = (UINT8) (1 << GpioNum);
+ } else {
+ SubAddr = RegBase + 1;
+ GpioNumMask = (UINT8) (1 << (GpioNum - 8));
+ }
+
+ //
+ // Output port value always at 2nd byte in Data variable.
+ //
+ RegValuePtr = &Data[1];
+
+ //
+ // On read entry sub address at 2nd byte, on read exit output
+ // port value in 2nd byte.
+ //
+ Data[1] = SubAddr;
+ WriteLength = 1;
+ ReadLength = 1;
+ Status = I2cReadMultipleByte (
+ I2cDeviceAddr,
+ I2cAddrMode,
+ &WriteLength,
+ &ReadLength,
+ &Data[1]
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Adjust output port bit given callers request.
+ //
+ if (LogicOne) {
+ *RegValuePtr = *RegValuePtr | GpioNumMask;
+ } else {
+ *RegValuePtr = *RegValuePtr & ~(GpioNumMask);
+ }
+
+ //
+ // Update register. Sub address at 1st byte, value at 2nd byte.
+ //
+ WriteLength = 2;
+ Data[0] = SubAddr;
+ Status = I2cWriteMultipleByte (
+ I2cDeviceAddr,
+ I2cAddrMode,
+ &WriteLength,
+ Data
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+
+
+EFI_SPI_PROTOCOL *
+LocateSpiProtocol (
+ IN EFI_SMM_SYSTEM_TABLE2 *Smst
+ )
+{
+ if (mPlatHelpSpiProtocolRef == NULL) {
+ if (Smst != NULL) {
+ Smst->SmmLocateProtocol (
+ &gEfiSmmSpiProtocolGuid,
+ NULL,
+ (VOID **) &mPlatHelpSpiProtocolRef
+ );
+ } else {
+ gBS->LocateProtocol (
+ &gEfiSpiProtocolGuid,
+ NULL,
+ (VOID **) &mPlatHelpSpiProtocolRef
+ );
+ }
+ ASSERT (mPlatHelpSpiProtocolRef != NULL);
+ }
+ return mPlatHelpSpiProtocolRef;
+}
+
+//
+// Routines exported by this source module.
+//
+
+/**
+ Find pointer to RAW data in Firmware volume file.
+
+ @param FvNameGuid Firmware volume to search. If == NULL search all.
+ @param FileNameGuid Firmware volume file to search for.
+ @param SectionData Pointer to RAW data section of found file.
+ @param SectionDataSize Pointer to UNITN to get size of RAW data.
+
+ @retval EFI_SUCCESS Raw Data found.
+ @retval EFI_INVALID_PARAMETER FileNameGuid == NULL.
+ @retval EFI_NOT_FOUND Firmware volume file not found.
+ @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE).
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFindFvFileRawDataSection (
+ IN CONST EFI_GUID *FvNameGuid OPTIONAL,
+ IN CONST EFI_GUID *FileNameGuid,
+ OUT VOID **SectionData,
+ OUT UINTN *SectionDataSize
+ )
+{
+ if (FileNameGuid == NULL || SectionData == NULL || SectionDataSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ if (FvNameGuid != NULL) {
+ return EFI_UNSUPPORTED; // Searching in specific FV unsupported in DXE.
+ }
+
+ return GetSectionFromAnyFv (FileNameGuid, EFI_SECTION_RAW, 0, SectionData, SectionDataSize);
+}
+
+/**
+ Find free spi protect register and write to it to protect a flash region.
+
+ @param DirectValue Value to directly write to register.
+ if DirectValue == 0 the use Base & Length below.
+ @param BaseAddress Base address of region in Flash Memory Map.
+ @param Length Length of region to protect.
+
+ @retval EFI_SUCCESS Free spi protect register found & written.
+ @retval EFI_NOT_FOUND Free Spi protect register not found.
+ @retval EFI_DEVICE_ERROR Unable to write to spi protect register.
+**/
+EFI_STATUS
+EFIAPI
+PlatformWriteFirstFreeSpiProtect (
+ IN CONST UINT32 DirectValue,
+ IN CONST UINT32 BaseAddress,
+ IN CONST UINT32 Length
+ )
+{
+ UINT32 FreeOffset;
+ UINT32 PchRootComplexBar;
+ EFI_STATUS Status;
+
+ PchRootComplexBar = QNC_RCRB_BASE;
+
+ Status = WriteFirstFreeSpiProtect (
+ PchRootComplexBar,
+ DirectValue,
+ BaseAddress,
+ Length,
+ &FreeOffset
+ );
+
+ if (!EFI_ERROR (Status)) {
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (PchRootComplexBar + FreeOffset),
+ 1,
+ (VOID *) (UINTN) (PchRootComplexBar + FreeOffset)
+ );
+ }
+
+ return Status;
+}
+
+/**
+ Lock legacy SPI static configuration information.
+
+ Function will assert if unable to lock config.
+
+**/
+VOID
+EFIAPI
+PlatformFlashLockConfig (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_SPI_PROTOCOL *SpiProtocol;
+
+ //
+ // Enable lock of legacy SPI static configuration information.
+ //
+
+ SpiProtocol = LocateSpiProtocol (NULL); // This routine will not be called in SMM.
+ ASSERT_EFI_ERROR (SpiProtocol != NULL);
+ if (SpiProtocol != NULL) {
+ Status = SpiProtocol->Lock (SpiProtocol);
+
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO, "Platform: Spi Config Locked Down\n"));
+ } else if (Status == EFI_ACCESS_DENIED) {
+ DEBUG ((EFI_D_INFO, "Platform: Spi Config already locked down\n"));
+ } else {
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+}
+
+/**
+ Platform Variable Lock.
+
+ @retval EFI_SUCCESS Platform Variable Lock successful.
+ @retval EFI_NOT_FOUND No protocol instances were found that match Protocol and
+ Registration.
+
+**/
+VOID
+EFIAPI
+PlatformVariableLock (
+ )
+{
+ EFI_STATUS Status;
+ EDKII_VARIABLE_LOCK_PROTOCOL *VariableLockProtocol;
+
+ Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **)&VariableLockProtocol);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = VariableLockProtocol->RequestToLock (
+ VariableLockProtocol,
+ QUARK_VARIABLE_LOCK_NAME,
+ &gQuarkVariableLockGuid
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ // Memory Config Data shouldn't be writable when Quark Variable Lock is enabled.
+ Status = VariableLockProtocol->RequestToLock (
+ VariableLockProtocol,
+ EFI_MEMORY_CONFIG_DATA_NAME,
+ &gEfiMemoryConfigDataGuid
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Lock regions and config of SPI flash given the policy for this platform.
+
+ Function will assert if unable to lock regions or config.
+
+ @param PreBootPolicy If TRUE do Pre Boot Flash Lock Policy.
+
+**/
+VOID
+EFIAPI
+PlatformFlashLockPolicy (
+ IN CONST BOOLEAN PreBootPolicy
+ )
+{
+ EFI_STATUS Status;
+ UINT64 CpuAddressNvStorage;
+ UINT64 CpuAddressFlashDevice;
+ UINT64 SpiAddress;
+ EFI_BOOT_MODE BootMode;
+ UINTN SpiFlashDeviceSize;
+
+ BootMode = GetBootModeHob ();
+
+ SpiFlashDeviceSize = (UINTN) PcdGet32 (PcdSpiFlashDeviceSize);
+ CpuAddressFlashDevice = SIZE_4GB - SpiFlashDeviceSize;
+ DEBUG (
+ (EFI_D_INFO,
+ "Platform:FlashDeviceSize = 0x%08x Bytes\n",
+ SpiFlashDeviceSize)
+ );
+
+ //
+ // If not in update or recovery mode, lock stuff down
+ //
+ if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
+
+ //
+ // Lock regions
+ //
+ CpuAddressNvStorage = (UINT64) PcdGet32 (PcdFlashNvStorageVariableBase);
+
+ //
+ // Lock from start of flash device up to Smi writable flash storage areas.
+ //
+ SpiAddress = 0;
+ if (!PlatformIsSpiRangeProtected ((UINT32) SpiAddress, (UINT32) (CpuAddressNvStorage - CpuAddressFlashDevice))) {
+ DEBUG (
+ (EFI_D_INFO,
+ "Platform: Protect Region Base:Len 0x%08x:0x%08x\n",
+ (UINTN) SpiAddress, (UINTN)(CpuAddressNvStorage - CpuAddressFlashDevice))
+ );
+ Status = PlatformWriteFirstFreeSpiProtect (
+ 0,
+ (UINT32) SpiAddress,
+ (UINT32) (CpuAddressNvStorage - CpuAddressFlashDevice)
+ );
+
+ ASSERT_EFI_ERROR (Status);
+ }
+ //
+ // Move Spi Address to after Smi writable flash storage areas.
+ //
+ SpiAddress = CpuAddressNvStorage - CpuAddressFlashDevice;
+ SpiAddress += ((UINT64) PcdGet32 (PcdFlashNvStorageVariableSize));
+
+ //
+ // Lock from end of OEM area to end of flash part.
+ //
+ if (!PlatformIsSpiRangeProtected ((UINT32) SpiAddress, SpiFlashDeviceSize - ((UINT32) SpiAddress))) {
+ DEBUG (
+ (EFI_D_INFO,
+ "Platform: Protect Region Base:Len 0x%08x:0x%08x\n",
+ (UINTN) SpiAddress,
+ (UINTN) (SpiFlashDeviceSize - ((UINT32) SpiAddress)))
+ );
+ ASSERT (SpiAddress < ((UINT64) SpiFlashDeviceSize));
+ Status = PlatformWriteFirstFreeSpiProtect (
+ 0,
+ (UINT32) SpiAddress,
+ SpiFlashDeviceSize - ((UINT32) SpiAddress)
+ );
+
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+
+ //
+ // Always Lock flash config registers if about to boot a boot option
+ // else lock depending on boot mode.
+ //
+ if (PreBootPolicy || (BootMode != BOOT_ON_FLASH_UPDATE)) {
+ PlatformFlashLockConfig ();
+ }
+
+ //
+ // Enable Quark Variable lock if PreBootPolicy.
+ //
+ if (PreBootPolicy) {
+ PlatformVariableLock ();
+ }
+}
+
+/**
+ Erase and Write to platform flash.
+
+ Routine accesses one flash block at a time, each access consists
+ of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
+ of DoErase & DoWrite params must be TRUE.
+
+ Limitations:-
+ CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
+ DataSize must be a multiple of FLASH_BLOCK_SIZE.
+
+ @param Smst If != NULL then InSmm and use to locate
+ SpiProtocol.
+ @param CpuWriteAddress Address in CPU memory map of flash region.
+ @param Data The buffer containing the data to be written.
+ @param DataSize Amount of data to write.
+ @param DoErase Earse each block.
+ @param DoWrite Write to each block.
+
+ @retval EFI_SUCCESS Operation successful.
+ @retval EFI_NOT_READY Required resources not setup.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval Others Unexpected error happened.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFlashEraseWrite (
+ IN VOID *Smst,
+ IN UINTN CpuWriteAddress,
+ IN UINT8 *Data,
+ IN UINTN DataSize,
+ IN BOOLEAN DoErase,
+ IN BOOLEAN DoWrite
+ )
+{
+ EFI_STATUS Status;
+ UINT64 CpuBaseAddress;
+ SPI_INIT_INFO *SpiInfo;
+ UINT8 *WriteBuf;
+ UINTN Index;
+ UINTN SpiWriteAddress;
+ EFI_SPI_PROTOCOL *SpiProtocol;
+
+ if (!DoErase && !DoWrite) {
+ return EFI_INVALID_PARAMETER;
+ }
+ if (DoWrite && Data == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ if ((CpuWriteAddress % FLASH_BLOCK_SIZE) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+ if ((DataSize % FLASH_BLOCK_SIZE) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+ SpiProtocol = LocateSpiProtocol ((EFI_SMM_SYSTEM_TABLE2 *)Smst);
+ if (SpiProtocol == NULL) {
+ return EFI_NOT_READY;
+ }
+
+ //
+ // Find info to allow usage of SpiProtocol->Execute.
+ //
+ Status = SpiProtocol->Info (
+ SpiProtocol,
+ &SpiInfo
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ ASSERT (SpiInfo->InitTable != NULL);
+ ASSERT (SpiInfo->EraseOpcodeIndex < SPI_NUM_OPCODE);
+ ASSERT (SpiInfo->ProgramOpcodeIndex < SPI_NUM_OPCODE);
+
+ CpuBaseAddress = PcdGet32 (PcdFlashAreaBaseAddress) - (UINT32)SpiInfo->InitTable->BiosStartOffset;
+ ASSERT(CpuBaseAddress >= (SIZE_4GB - SIZE_8MB));
+ if (CpuWriteAddress < CpuBaseAddress) {
+ return (EFI_INVALID_PARAMETER);
+ }
+
+ SpiWriteAddress = CpuWriteAddress - ((UINTN) CpuBaseAddress);
+ WriteBuf = Data;
+ DEBUG (
+ (EFI_D_INFO, "PlatformFlashWrite:SpiWriteAddress=%08x EraseIndex=%d WriteIndex=%d\n",
+ SpiWriteAddress,
+ (UINTN) SpiInfo->EraseOpcodeIndex,
+ (UINTN) SpiInfo->ProgramOpcodeIndex
+ ));
+ for (Index =0; Index < DataSize / FLASH_BLOCK_SIZE; Index++) {
+ if (DoErase) {
+ DEBUG (
+ (EFI_D_INFO, "PlatformFlashWrite:Erase[%04x] SpiWriteAddress=%08x\n",
+ Index,
+ SpiWriteAddress
+ ));
+ Status = SpiProtocol->Execute (
+ SpiProtocol,
+ SpiInfo->EraseOpcodeIndex,// OpcodeIndex
+ 0, // PrefixOpcodeIndex
+ FALSE, // DataCycle
+ TRUE, // Atomic
+ FALSE, // ShiftOut
+ SpiWriteAddress, // Address
+ 0, // Data Number
+ NULL,
+ EnumSpiRegionAll // SPI_REGION_TYPE
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+
+ if (DoWrite) {
+ DEBUG (
+ (EFI_D_INFO, "PlatformFlashWrite:Write[%04x] SpiWriteAddress=%08x\n",
+ Index,
+ SpiWriteAddress
+ ));
+ Status = SpiProtocol->Execute (
+ SpiProtocol,
+ SpiInfo->ProgramOpcodeIndex, // OpcodeIndex
+ 0, // PrefixOpcodeIndex
+ TRUE, // DataCycle
+ TRUE, // Atomic
+ TRUE, // ShiftOut
+ SpiWriteAddress, // Address
+ FLASH_BLOCK_SIZE, // Data Number
+ WriteBuf,
+ EnumSpiRegionAll
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ WriteBuf+=FLASH_BLOCK_SIZE;
+ }
+ SpiWriteAddress+=FLASH_BLOCK_SIZE;
+ }
+ return EFI_SUCCESS;
+}
+
+/** Check if System booted with recovery Boot Stage1 image.
+
+ @retval TRUE If system booted with recovery Boot Stage1 image.
+ @retval FALSE If system booted with normal stage1 image.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformIsBootWithRecoveryStage1 (
+ VOID
+ )
+{
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ return FALSE;
+}
+
+/**
+ Set the direction of Pcal9555 IO Expander GPIO pin.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio direction to configure - values 0-7 for Port0
+ and 8-15 for Port1.
+ @param CfgAsInput If TRUE set pin direction as input else set as output.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioSetDir (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST BOOLEAN CfgAsInput
+ )
+{
+ Pcal9555SetPortRegBit (
+ Pcal9555SlaveAddr,
+ GpioNum,
+ PCAL9555_REG_CFG_PORT0,
+ CfgAsInput
+ );
+}
+
+/**
+ Set the level of Pcal9555 IO Expander GPIO high or low.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+ @param HighLevel If TRUE set pin high else set pin low.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioSetLevel (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST BOOLEAN HighLevel
+ )
+{
+ Pcal9555SetPortRegBit (
+ Pcal9555SlaveAddr,
+ GpioNum,
+ PCAL9555_REG_OUT_PORT0,
+ HighLevel
+ );
+}
+
+/**
+
+ Enable pull-up/pull-down resistors of Pcal9555 GPIOs.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioEnablePull (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum
+ )
+{
+ Pcal9555SetPortRegBit (
+ Pcal9555SlaveAddr,
+ GpioNum,
+ PCAL9555_REG_PULL_EN_PORT0,
+ TRUE
+ );
+}
+
+/**
+
+ Disable pull-up/pull-down resistors of Pcal9555 GPIOs.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioDisablePull (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum
+ )
+{
+ Pcal9555SetPortRegBit (
+ Pcal9555SlaveAddr,
+ GpioNum,
+ PCAL9555_REG_PULL_EN_PORT0,
+ FALSE
+ );
+}
+
+/**
+
+ Get state of Pcal9555 GPIOs.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+
+ @retval TRUE GPIO pin is high
+ @retval FALSE GPIO pin is low
+**/
+BOOLEAN
+EFIAPI
+PlatformPcal9555GpioGetState (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum
+ )
+{
+ return Pcal9555GetPortRegBit (Pcal9555SlaveAddr, GpioNum, PCAL9555_REG_IN_PORT0);
+}
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c new file mode 100644 index 0000000000..6aefdb3794 --- /dev/null +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c @@ -0,0 +1,263 @@ +/** @file
+Helper routines with common PEI / DXE implementation.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+
+CHAR16 *mPlatTypeNameTable[] = { EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION };
+UINTN mPlatTypeNameTableLen = ((sizeof(mPlatTypeNameTable)) / sizeof (CHAR16 *));
+
+//
+// Routines defined in other source modules of this component.
+//
+
+//
+// Routines local to this source module.
+//
+
+//
+// Routines shared with other souce modules in this component.
+//
+
+EFI_STATUS
+WriteFirstFreeSpiProtect (
+ IN CONST UINT32 PchRootComplexBar,
+ IN CONST UINT32 DirectValue,
+ IN CONST UINT32 BaseAddress,
+ IN CONST UINT32 Length,
+ OUT UINT32 *OffsetPtr
+ )
+{
+ UINT32 RegVal;
+ UINT32 Offset;
+ UINT32 StepLen;
+
+ ASSERT (PchRootComplexBar > 0);
+
+ Offset = 0;
+ if (OffsetPtr != NULL) {
+ *OffsetPtr = Offset;
+ }
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) == 0) {
+ Offset = R_QNC_RCRB_SPIPBR0;
+ } else {
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1) == 0) {
+ Offset = R_QNC_RCRB_SPIPBR1;
+ } else {
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2) == 0) {
+ Offset = R_QNC_RCRB_SPIPBR2;
+ }
+ }
+ }
+ if (Offset != 0) {
+ if (DirectValue == 0) {
+ StepLen = ALIGN_VALUE (Length,SIZE_4KB); // Bring up to 4K boundary.
+ RegVal = BaseAddress + StepLen - 1;
+ RegVal &= 0x00FFF000; // Set EDS Protected Range Limit (PRL).
+ RegVal |= ((BaseAddress >> 12) & 0xfff); // or in EDS Protected Range Base (PRB).
+ } else {
+ RegVal = DirectValue;
+ }
+ //
+ // Enable protection.
+ //
+ RegVal |= B_QNC_RCRB_SPIPBRn_WPE;
+ MmioWrite32 (PchRootComplexBar + Offset, RegVal);
+ if (RegVal == MmioRead32 (PchRootComplexBar + Offset)) {
+ if (OffsetPtr != NULL) {
+ *OffsetPtr = Offset;
+ }
+ return EFI_SUCCESS;
+ }
+ return EFI_DEVICE_ERROR;
+ }
+ return EFI_NOT_FOUND;
+}
+
+//
+// Routines exported by this component.
+//
+
+/**
+ Read 8bit character from debug stream.
+
+ Block until character is read.
+
+ @return 8bit character read from debug stream.
+
+**/
+CHAR8
+EFIAPI
+PlatformDebugPortGetChar8 (
+ VOID
+ )
+{
+ CHAR8 Got;
+
+ do {
+ if (SerialPortPoll ()) {
+ if (SerialPortRead ((UINT8 *) &Got, 1) == 1) {
+ break;
+ }
+ }
+ } while (TRUE);
+
+ return Got;
+}
+
+/**
+ Clear SPI Protect registers.
+
+ @retval EFI_SUCCESS SPI protect registers cleared.
+ @retval EFI_ACCESS_DENIED Unable to clear SPI protect registers.
+**/
+
+EFI_STATUS
+EFIAPI
+PlatformClearSpiProtect (
+ VOID
+ )
+{
+ UINT32 PchRootComplexBar;
+
+ PchRootComplexBar = QNC_RCRB_BASE;
+ //
+ // Check if the SPI interface has been locked-down.
+ //
+ if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0, 0);
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1, 0);
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2, 0);
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Determine if an SPI address range is protected.
+
+ @param SpiBaseAddress Base of SPI range.
+ @param Length Length of SPI range.
+
+ @retval TRUE Range is protected.
+ @retval FALSE Range is not protected.
+**/
+BOOLEAN
+EFIAPI
+PlatformIsSpiRangeProtected (
+ IN CONST UINT32 SpiBaseAddress,
+ IN CONST UINT32 Length
+ )
+{
+ UINT32 RegVal;
+ UINT32 Offset;
+ UINT32 Limit;
+ UINT32 ProtectedBase;
+ UINT32 ProtectedLimit;
+ UINT32 PchRootComplexBar;
+
+ PchRootComplexBar = QNC_RCRB_BASE;
+
+ if (Length > 0) {
+ Offset = R_QNC_RCRB_SPIPBR0;
+ Limit = SpiBaseAddress + (Length - 1);
+ do {
+ RegVal = MmioRead32 (PchRootComplexBar + Offset);
+ if ((RegVal & B_QNC_RCRB_SPIPBRn_WPE) != 0) {
+ ProtectedBase = (RegVal & 0xfff) << 12;
+ ProtectedLimit = (RegVal & 0x00fff000) + 0xfff;
+ if (SpiBaseAddress >= ProtectedBase && Limit <= ProtectedLimit) {
+ return TRUE;
+ }
+ }
+ if (Offset == R_QNC_RCRB_SPIPBR0) {
+ Offset = R_QNC_RCRB_SPIPBR1;
+ } else if (Offset == R_QNC_RCRB_SPIPBR1) {
+ Offset = R_QNC_RCRB_SPIPBR2;
+ } else {
+ break;
+ }
+ } while (TRUE);
+ }
+ return FALSE;
+}
+
+/**
+ Set Legacy GPIO Level
+
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.
+ @param GpioNum GPIO bit to change.
+ @param HighLevel If TRUE set GPIO High else Set GPIO low.
+
+**/
+VOID
+EFIAPI
+PlatformLegacyGpioSetLevel (
+ IN CONST UINT32 LevelRegOffset,
+ IN CONST UINT32 GpioNum,
+ IN CONST BOOLEAN HighLevel
+ )
+{
+ UINT32 RegValue;
+ UINT32 GpioBaseAddress;
+ UINT32 GpioNumMask;
+
+ GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
+ ASSERT (GpioBaseAddress > 0);
+
+ RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
+ GpioNumMask = (1 << GpioNum);
+ if (HighLevel) {
+ RegValue |= (GpioNumMask);
+ } else {
+ RegValue &= ~(GpioNumMask);
+ }
+ IoWrite32 (GpioBaseAddress + LevelRegOffset, RegValue);
+}
+
+/**
+ Get Legacy GPIO Level
+
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.
+ @param GpioNum GPIO bit to check.
+
+ @retval TRUE If bit is SET.
+ @retval FALSE If bit is CLEAR.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformLegacyGpioGetLevel (
+ IN CONST UINT32 LevelRegOffset,
+ IN CONST UINT32 GpioNum
+ )
+{
+ UINT32 RegValue;
+ UINT32 GpioBaseAddress;
+ UINT32 GpioNumMask;
+
+ GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
+ RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
+ GpioNumMask = (1 << GpioNum);
+ return ((RegValue & GpioNumMask) != 0);
+}
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c new file mode 100644 index 0000000000..50a0e42743 --- /dev/null +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c @@ -0,0 +1,167 @@ +/** @file
+Implementation of Helper routines for PEI enviroment.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/I2cLib.h>
+
+#include "CommonHeader.h"
+
+//
+// Routines defined in other source modules of this component.
+//
+
+//
+// Routines local to this source module.
+//
+
+//
+// Routines exported by this source module.
+//
+
+/**
+ Find pointer to RAW data in Firmware volume file.
+
+ @param FvNameGuid Firmware volume to search. If == NULL search all.
+ @param FileNameGuid Firmware volume file to search for.
+ @param SectionData Pointer to RAW data section of found file.
+ @param SectionDataSize Pointer to UNITN to get size of RAW data.
+
+ @retval EFI_SUCCESS Raw Data found.
+ @retval EFI_INVALID_PARAMETER FileNameGuid == NULL.
+ @retval EFI_NOT_FOUND Firmware volume file not found.
+ @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE).
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFindFvFileRawDataSection (
+ IN CONST EFI_GUID *FvNameGuid OPTIONAL,
+ IN CONST EFI_GUID *FileNameGuid,
+ OUT VOID **SectionData,
+ OUT UINTN *SectionDataSize
+ )
+{
+ EFI_STATUS Status;
+ UINTN Instance;
+ EFI_PEI_FV_HANDLE VolumeHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_SECTION_TYPE SearchType;
+ EFI_FV_INFO VolumeInfo;
+ EFI_FV_FILE_INFO FileInfo;
+ CONST EFI_PEI_SERVICES **PeiServices;
+
+ if (FileNameGuid == NULL || SectionData == NULL || SectionDataSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ *SectionData = NULL;
+ *SectionDataSize = 0;
+
+ PeiServices = GetPeiServicesTablePointer ();
+ SearchType = EFI_SECTION_RAW;
+ for (Instance = 0; !EFI_ERROR((PeiServicesFfsFindNextVolume (Instance, &VolumeHandle))); Instance++) {
+ if (FvNameGuid != NULL) {
+ Status = PeiServicesFfsGetVolumeInfo (VolumeHandle, &VolumeInfo);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ if (!CompareGuid (FvNameGuid, &VolumeInfo.FvName)) {
+ continue;
+ }
+ }
+ Status = PeiServicesFfsFindFileByName (FileNameGuid, VolumeHandle, &FileHandle);
+ if (!EFI_ERROR (Status)) {
+ Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ if (IS_SECTION2(FileInfo.Buffer)) {
+ *SectionDataSize = SECTION2_SIZE(FileInfo.Buffer) - sizeof(EFI_COMMON_SECTION_HEADER2);
+ } else {
+ *SectionDataSize = SECTION_SIZE(FileInfo.Buffer) - sizeof(EFI_COMMON_SECTION_HEADER);
+ }
+ Status = PeiServicesFfsFindSectionData (SearchType, FileHandle, SectionData);
+ if (!EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ }
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Find free spi protect register and write to it to protect a flash region.
+
+ @param DirectValue Value to directly write to register.
+ if DirectValue == 0 the use Base & Length below.
+ @param BaseAddress Base address of region in Flash Memory Map.
+ @param Length Length of region to protect.
+
+ @retval EFI_SUCCESS Free spi protect register found & written.
+ @retval EFI_NOT_FOUND Free Spi protect register not found.
+ @retval EFI_DEVICE_ERROR Unable to write to spi protect register.
+**/
+EFI_STATUS
+EFIAPI
+PlatformWriteFirstFreeSpiProtect (
+ IN CONST UINT32 DirectValue,
+ IN CONST UINT32 BaseAddress,
+ IN CONST UINT32 Length
+ )
+{
+ return WriteFirstFreeSpiProtect (
+ QNC_RCRB_BASE,
+ DirectValue,
+ BaseAddress,
+ Length,
+ NULL
+ );
+}
+
+/** Check if System booted with recovery Boot Stage1 image.
+
+ @retval TRUE If system booted with recovery Boot Stage1 image.
+ @retval FALSE If system booted with normal stage1 image.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformIsBootWithRecoveryStage1 (
+ VOID
+ )
+{
+ BOOLEAN IsRecoveryBoot;
+ QUARK_EDKII_STAGE1_HEADER *Edk2ImageHeader;
+
+ Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) PcdGet32 (PcdEsramStage1Base);
+ switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) {
+ case QUARK_STAGE1_RECOVERY_IMAGE_TYPE:
+ //
+ // Recovery Boot
+ //
+ IsRecoveryBoot = TRUE;
+ break;
+ default:
+ //
+ // Normal Boot
+ //
+ IsRecoveryBoot = FALSE;
+ break;
+ }
+
+ return IsRecoveryBoot;
+}
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c new file mode 100644 index 0000000000..56c47b8075 --- /dev/null +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c @@ -0,0 +1,152 @@ +/** @file
+Platform helper LED routines.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include "CommonHeader.h"
+
+//
+// Routines defined in other source modules of this component.
+//
+
+//
+// Routines local to this source module.
+//
+
+VOID
+GalileoGen2RouteOutFlashUpdateLed (
+ VOID
+ )
+{
+ //
+ // For GpioNums below values 0 to 7 are for Port0 ie P0-0 - P0-7 and
+ // values 8 to 15 are for Port1 ie P1-0 - P1-7.
+ //
+
+ //
+ // Disable Pull-ups / pull downs on EXP0 pin for LVL_B_PU7 signal.
+ //
+ PlatformPcal9555GpioDisablePull (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
+ 15 // P1-7.
+ );
+
+ //
+ // Make LVL_B_OE7_N an output pin.
+ //
+ PlatformPcal9555GpioSetDir (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
+ 14, // P1-6.
+ FALSE
+ );
+
+ //
+ // Set level of LVL_B_OE7_N to low.
+ //
+ PlatformPcal9555GpioSetLevel (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR,
+ 14,
+ FALSE
+ );
+
+ //
+ // Make MUX8_SEL an output pin.
+ //
+ PlatformPcal9555GpioSetDir (
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
+ 14, // P1-6.
+ FALSE
+ );
+
+ //
+ // Set level of MUX8_SEL to low to route GPIO_SUS<5> to LED.
+ //
+ PlatformPcal9555GpioSetLevel (
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
+ 14, // P1-6.
+ FALSE
+ );
+}
+
+//
+// Routines exported by this source module.
+//
+
+/**
+ Init platform LEDs into known state.
+
+ @param PlatformType Executing platform type.
+ @param I2cBus Pointer to I2c Host controller protocol.
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformLedInit (
+ IN CONST EFI_PLATFORM_TYPE Type
+ )
+{
+ EFI_BOOT_MODE BootMode;
+
+ BootMode = GetBootModeHob ();
+
+ //
+ // Init Flash update / recovery LED in OFF state.
+ //
+ if (BootMode == BOOT_ON_FLASH_UPDATE || BootMode == BOOT_IN_RECOVERY_MODE) {
+ if (Type == GalileoGen2) {
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, FALSE);
+ GalileoGen2RouteOutFlashUpdateLed ();
+ } else if (Type == Galileo) {
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO, FALSE);
+ } else {
+ //
+ // These platforms have no flash update LED.
+ //
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Turn on or off platform flash update LED.
+
+ @param PlatformType Executing platform type.
+ @param TurnOn If TRUE turn on else turn off.
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFlashUpdateLed (
+ IN CONST EFI_PLATFORM_TYPE Type,
+ IN CONST BOOLEAN TurnOn
+ )
+{
+ if (Type == GalileoGen2) {
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, TurnOn);
+ } else if (Type == Galileo) {
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO, TurnOn);
+ } else {
+ //
+ // These platforms have no flash update LED.
+ //
+ }
+
+ return EFI_SUCCESS;
+}
|