diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-22 19:41:14 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:15:02 +0800 |
| commit | a674eea1c47a6aa0170b2beb07d4f2bbefc798e0 (patch) | |
| tree | 3db2b004775c74c311c7c5b7b3998f0c6dc91c32 /Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi | |
| parent | f0a77159beb39438f311993bf6cd4136aa7e02fc (diff) | |
| download | edk2-platforms-a674eea1c47a6aa0170b2beb07d4f2bbefc798e0.tar.xz | |
BroxtonSiPkg: Add Cpu Include file and Library
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi')
6 files changed, 517 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/BiosGuardConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/BiosGuardConfig.h new file mode 100644 index 0000000000..4eae2c81e8 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/BiosGuardConfig.h @@ -0,0 +1,52 @@ +/** @file
+ CPU policy PPI produced by a platform driver specifying various
+ expected CPU settings. This PPI is consumed by CPU PEI modules.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BIOS_GUARD_CONFIG_H_
+#define _BIOS_GUARD_CONFIG_H_
+
+#include "BiosGuardDefinitions.h"
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gBiosGuardConfigGuid;
+
+#pragma pack(push, 1)
+
+#define BIOS_GUARD_CONFIG_REVISION 1
+
+/**
+ Platform policies for BIOS Guard Configuration for all processor security features configuration.
+ Platform code can pass relevant configuration data through this structure.
+ @note The policies are marked are either <b>(Required)</b> or <b>(Optional)</b>
+ - <b>(Required)</b> : This policy is recommended to be properly configured for proper functioning of reference code and silicon initialization
+ - <b>(Optional)</b> : This policy is recommended for validation purpose only.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 GUID number for main entry of config block
+ BGUP_HEADER BgupHeader; ///< BIOS Guard update package header that will be packaged along with BIOS Guard script and update data.
+ BGPDT Bgpdt; ///< BIOS Guard Platform Data Table contains all the platform data that will be parsed by BIOS Guard module.
+ UINT64 BgpdtHash[4]; ///< Hash of the BGPDT that will be programmed to PLAT_FRMW_PROT_HASH_0/1/2/3 MSR.
+ UINT8 EcCmdDiscovery; ///< EC Command discovery.
+ UINT8 EcCmdProvisionEav; ///< EC Command Provision Eav.
+ UINT8 EcCmdLock; ///< EC Command Lock.
+ UINT8 Rsvd; ///< Reserved for DWORD alignment.
+ BIOSGUARD_LOG BiosGuardLog; ///< BIOS Guard log.
+} BIOS_GUARD_CONFIG;
+
+#pragma pack(pop)
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuConfig.h new file mode 100644 index 0000000000..8e59736b37 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuConfig.h @@ -0,0 +1,141 @@ +/** @file
+ CPU policy PPI produced by a platform driver specifying various
+ expected CPU settings. This PPI is consumed by CPU PEI modules.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack(push, 1)
+
+//
+// CPU_CONFIG revisions
+//
+#define CPU_CONFIG_REVISION 1
+
+///
+/// Enums for EC Command Type
+///
+typedef enum {
+ SendEcCmds = 1,
+ SendEcValue,
+ ReceiveEcValue,
+ EcCmdMax
+} EC_COMMAND_TYPE;
+
+/**
+ This function is for platform code to provide EC Commands since different BIOS might have different EC.
+ Platform code need to provide a function for CPU code to call to communicate with EC.
+
+ @param[in] This Driver context.
+ @param[in] EcCmdType EC Command Type.
+ @param[in] EcCmd EC Command Byte to send.
+ @param[in] SendData EC Data Byte to send.
+ @param[in] ReceiveData EC Data Byte received.
+
+ @retval EFI_SUCCESS Command Read/ Write Success
+ @retval EFI_DEVICE_ERROR Command Read/ Write Error
+ @retval EFI_OUT_OF_RESOURCES No enough resources (such as out of memory).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_SEND_EC_COMMAND) (
+ IN EC_COMMAND_TYPE EcCmdType,
+ IN UINT8 EcCmd,
+ IN UINT8 SendData,
+ IN OUT UINT8 *ReceiveData
+ );
+
+///
+/// Platform Specific Socket Information
+///
+typedef struct {
+ EFI_PHYSICAL_ADDRESS SocketDesignation;
+ EFI_PHYSICAL_ADDRESS SerialNumber;
+ EFI_PHYSICAL_ADDRESS AssetTag;
+ EFI_PHYSICAL_ADDRESS PartNumber;
+ UINT16 MaxSpeed;
+ UINT8 ProcessorUpgrade;
+ UINT8 Rsvd;
+} SMBIOS_SOCKET_INFO;
+
+/**
+ Platform Policies for CPU features configuration Platform code can enable/disable/configure features through this structure.
+ @note The policies are marked are either <b>(Required)</b> or <b>(Optional)</b>.
+ - <b>(Required)</b>: This policy is recommended to be properly configured for proper functioning of reference code and silicon initialization.
+ - <b>(Optional)</b>: This policy is recommended for validation purpose only.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 GUID number for main entry of config block
+ //
+ // Bit definition for functionality enable/disable.
+ //
+ UINT32 HyperThreading : 1; ///< <b>(Optional)</b> Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>.
+ UINT32 VmxEnable : 1; ///< <b>(Optional)</b> Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
+ UINT32 MlcStreamerPrefetcher : 1; ///< <b>(Optional)</b> Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
+ UINT32 MlcSpatialPrefetcher : 1; ///< <b>(Optional)</b> Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>.
+ UINT32 SmxEnable : 1; ///< <b>(Optional)</b> Enable or Disable Secure Mode Extensions feature; 0: Disable; <b>1: Enable</b>.
+ UINT32 MonitorMwaitEnable : 1; ///< <b>(Optional)</b> Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
+ UINT32 MachineCheckEnable : 1; ///< <b>(Optional)</b> Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
+ UINT32 AesEnable : 1; ///< <b>(Optional)</b> Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; <b>1: Enable</b>.
+ UINT32 DebugInterfaceEnable : 1; ///< <b>(Optional)</b> Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
+ UINT32 DebugInterfaceLockEnable : 1; ///< <b>(Optional)</b> Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
+ /**
+ <b>(Required)</b> Policies to obtain CPU temperature.
+ - <b>0: ACPI thermal management uses EC reported temperature values</b>.
+ - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.
+ - 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition.
+ **/
+ UINT32 EnableDts : 2;
+ UINT32 ApIdleManner : 2; ///< <b>(Optional)</b> AP Idle Manner of waiting for SIPI; <b>1: HALT loop</b>; 2: MWAIT loop; 3: RUN loop.
+ UINT32 ApHandoffManner : 2; ///< <b>(Debug)</b> Settings for AP Handoff to OS; <b>1: HALT loop</b>; 2: MWAIT loop.
+ UINT32 ActiveProcessorCores : 3; ///< <b>(Debug)</b> Number of active cores. <b>0: All</b>.
+ UINT32 DisableCore1 : 1; ///< <b>(Debug)</b> Enable/Disable Core 1 <b>
+ UINT32 DisableCore2 : 1; ///< <b>(Debug)</b> Enable/Disable Core 2 <b>
+ UINT32 DisableCore3 : 1; ///< <b>(Debug)</b> Enable/Disable Core 3 <b>
+ /**
+ <b>(Debug)</b> Processor Early Power On Configuration FCLK setting.
+ - <b>0: 800 MHz (ULT/ULX)</b>.
+ - <b>1: 1 GHz (DT/Halo)</b>
+ - 2: 400 MHz.
+ - 3: Reserved.
+ **/
+ UINT32 FClkFrequency : 2;
+ UINT32 JtagC10PowerGateDisable : 1; ///< <b>(Debug)</b> Power JTAG in C10 and deeper power states; <b>0: Disable</b>; 1: Enable.
+ UINT32 ProcTraceOutputScheme : 1; ///< <b>(Debug)</b> Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
+ UINT32 ProcTraceEnable : 1; ///< <b>(Debug)</b> Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
+ UINT32 ThreeStrikeCounterDisable : 1; ///< <b>(Debug)</b> Disable Three strike counter; <b>0: Enable counter</b>; 1: Disable counter.
+ UINT32 VoltageOptimizer : 1; ///< <b>(Optional)</b> Enable or Disable Voltage Optimizer feature <b>0: Disable</b>; 1: Enable
+ UINT32 FlashWearOutProtection : 1; ///< Flash Wear-out Protection; <b>0: Disable</b>; 1: Enable
+ UINT32 SkipMpInit : 2; /// < For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
+ UINT32 PackageDts : 1; ///< <b>(Debug)</b> Power JTAG in C10 and deeper power states; <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits :31; ///< Bits reserved for DWORD alignment.
+ UINT8 CpuRatio; ///< <b>(Debug)</b> CPU ratio value.
+ UINT8 SmmbaseSwSmiNumber; ///< <b>(Required)</b> Software SMI Number from Smbase.
+ UINT8 ProcTraceMemSize; ///< <b>(Optional)</b> Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); <b>0xFF: Disable</b>.
+ UINT8 Rsvd; ///< Reserved for DWORD alignment.
+ EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< <b>(Required)</b> Platform code provides the address of the correct microcode patch.
+ PLATFORM_SEND_EC_COMMAND SendEcCmd; ///< Platform code can provide interface to communicate with EC through this function.
+ EFI_PHYSICAL_ADDRESS SmbiosSocketInfo; ///< This points to SMBIOS_SOCKET_INFO structure which is used to fill in the socket-related info for SMBIOS table type 4.
+} CPU_CONFIG;
+
+#pragma pack(pop)
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuConfigPreMem.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuConfigPreMem.h new file mode 100644 index 0000000000..e75d5cbbf2 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuConfigPreMem.h @@ -0,0 +1,51 @@ +/** @file
+ CPU policy PPI produced by a platform driver specifying various
+ expected CPU settings. This PPI is consumed by CPU PEI modules.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_CONFIG_PREMEM_H_
+#define _CPU_CONFIG_PREMEM_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gCpuConfigPreMemGuid;
+
+#pragma pack(push, 1)
+
+//
+// CPU_CONFIG_PREMEM revisions
+//
+#define CPU_CONFIG_PREMEM_REVISION 1
+
+/**
+ Platform Policies for CPU features configuration Platform code can enable/disable/configure features through this structure.
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 GUID number for main entry of config block
+ UINT32 BistOnReset : 1; ///< Enable or Disable BIST on Reset; <b>0: Disable</b>; 1 Enable.
+ UINT32 Txt : 1; ///< Enable or Disable TXT; <b>0: Disable</b>; 1: Enable.
+ UINT32 SkipStopPbet : 1; ///< Skip Stop PBET Timer <b>0: Disabled</b>, 1: Enabled
+ UINT32 BiosGuard : 1; ///< Enable or Disable BIOS Guard; 0: Disable, <b>1:Enable</b>
+ UINT32 EnableC6Dram : 1; ///< C6DRAM Memory. <b>0: C6DRAM Disabled</b>; 1: C6DRAM Enabled.
+ UINT32 FlashWearOutProtection : 1; ///< Flash Wear-Out Protection; <b>0: Disable</b>; 1: Enable
+ UINT32 RsvdBits :25; ///< Bits reserved for DWORD alignment.
+ UINT16 TotalFlashSize; ///< Total Flash Size on the system in KB
+ UINT16 BiosSize; ///< BIOS Size in KB
+} CPU_CONFIG_PREMEM;
+
+#pragma pack(pop)
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuOverclockingConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuOverclockingConfig.h new file mode 100644 index 0000000000..0fdb00fe73 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuOverclockingConfig.h @@ -0,0 +1,52 @@ +/** @file
+ CPU policy PPI produced by a platform driver specifying various
+ expected CPU settings. This PPI is consumed by CPU PEI modules.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_OVERCLOCKING_CONFIG_H_
+#define _CPU_OVERCLOCKING_CONFIG_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gCpuOverclockingConfigGuid;
+
+#pragma pack(push, 1)
+
+#define CPU_OVERCLOCKING_CONFIG_REVISION 1
+
+/**
+ Overclocking Configuration controls which use the CPU overclocking mailbox interface are defined in this structure.
+ Platform code can pass in data to the mailbox through this structure.
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 GUID number for main entry of config block
+ UINT32 CoreVoltageMode : 1; ///< Core voltage mode; <b>0: Adaptive</b>; 1: Override.
+ UINT32 RingVoltageMode : 1; ///< CLR voltage mode; <b>0: Adaptive</b>; 1:Override
+ UINT32 OcSupport : 1; ///< Over clocking support; <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 29; ///< Bits reserved for DWORD alignment.
+ INT16 CoreVoltageOffset; ///< The voltage offset applied to the core while operating in turbo mode.
+ UINT16 CoreVoltageOverride; ///< The core voltage override which is applied to the entire range of cpu core frequencies.
+ UINT16 CoreExtraTurboVoltage; ///< Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
+ UINT16 CoreMaxOcTurboRatio; ///< Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit.
+ INT16 RingVoltageOffset; ///< The voltage offset applied to CLR while operating in turbo mode.
+ UINT16 RingVoltageOverride; ///< The clr voltage override which is applied to the entire range of cpu frequencies.
+ UINT16 RingExtraTurboVoltage; ///< Extra Turbo voltage applied to clr.
+ UINT16 RingMaxOcTurboRatio; ///< Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit.
+} CPU_OVERCLOCKING_CONFIG;
+
+#pragma pack(pop)
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuPolicy.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuPolicy.h new file mode 100644 index 0000000000..70545c6384 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/CpuPolicy.h @@ -0,0 +1,54 @@ +/** @file
+ CPU policy PPI produced by a platform driver specifying various
+ expected CPU settings. This PPI is consumed by CPU PEI modules.
+
+ Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_POLICY_PPI_H_
+#define _CPU_POLICY_PPI_H_
+
+#include <ConfigBlock.h>
+#include <CpuAccess.h>
+#include <CpuDataStruct.h>
+#include <Ppi/BiosGuardConfig.h>
+#include <Ppi/CpuConfigPreMem.h>
+#include <Ppi/CpuConfig.h>
+#include <Ppi/CpuOverclockingConfig.h>
+#include <Ppi/PowerMgmtConfig.h>
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSiCpuPolicyPpiGuid;
+
+#pragma pack(1)
+
+//
+// SI_CPU_POLICY_PPI revisions
+//
+#define SI_CPU_POLICY_PPI_REVISION 1
+
+/**
+ The PPI allows the platform code to publish a set of configuration information that the
+ CPU drivers will use to configure the processor in the PEI phase.
+ This Policy PPI needs to be initialized for CPU configuration.
+ @note The PPI has to be published before processor PEIMs are dispatched.
+
+**/
+typedef struct {
+ CONFIG_BLOCK_TABLE_HEADER ConfigBlockTableHeader;
+} SI_CPU_POLICY_PPI;
+
+#pragma pack()
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/PowerMgmtConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/PowerMgmtConfig.h new file mode 100644 index 0000000000..1038ac2c1f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Ppi/PowerMgmtConfig.h @@ -0,0 +1,167 @@ +/** @file
+ CPU policy PPI produced by a platform driver specifying various
+ expected CPU settings. This PPI is consumed by CPU PEI modules.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _POWER_MGMT_CONFIG_H_
+#define _POWER_MGMT_CONFIG_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPowerMgmtConfigGuid;
+
+#pragma pack(push, 1)
+
+#define POWER_MGMT_CONFIG_REVISION 1
+
+///
+/// Define maximum number of custom ratio states supported
+///
+#define MAX_CUSTOM_RATIO_TABLE_ENTRIES 20
+
+///
+/// PPM Package C State Limit
+///
+typedef enum {
+ PkgC0 = 0,
+ PkgC1,
+ PkgC2,
+ PkgCpuDefault = 254
+} MAX_PKG_C_STATE;
+
+///
+/// Custom Power Uints.User can choose to enter in MilliWatts or Watts
+///
+typedef enum {
+ PowerUnitWatts = 0, ///< in Watts
+ PowerUnit125MilliWatts, ///< in 125 Milli Watts. Example 11.250 W Value to use for Power limits 90
+ PowerUnitMax
+} CUSTOM_POWER_UNIT;
+
+/**
+ Power management Configuration for all Processor Power Management Features
+ Configs are in this field. Platform code can enable/disable features through this field.
+ @note The policies are marked are either <b>(Required)</b> or <b>(Optional)</b>.
+ - <b>(Required)</b>: This policy is recommended to be properly configured for proper functioning of reference code and silicon initialization.
+ - <b>(Optional)</b>: This policy is recommended for validation purpose only.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 GUID number for main entry of config block
+ UINT32 Eist : 1; ///< <b>(Test)</b> Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
+ UINT32 Cx : 1; ///< <b>(Test)</b> Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
+ UINT32 C1e : 1; ///< <b>(Test)</b> Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
+ UINT32 C1AutoDemotion : 1; ///< <b>(Test)</b> Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; <b>1: C1 Auto demotion</b>;
+ UINT32 C3AutoDemotion : 1; ///< <b>(Test)</b> Enable or Disable C6/C7 auto demotion to C3 0: Disabled; <b>1: C3 Auto demotion</b>;
+ UINT32 TurboMode : 1; ///< <b>(Test)</b> Enable or Disable long duration Turbo Mode. Disable; <b>1: Enable</b>
+ UINT32 PowerLimit2Enable : 1; ///< Enable or Disable short duration Turbo Mode. Disable; <b>1: Enable</b>
+ UINT32 C1UnDemotion : 1; ///< Enable or Disable C1UnDemotion. 0: Disabled; <b>1: C1 Auto undemotion</b>;
+ UINT32 C3UnDemotion : 1; ///< <b>(Test)</b> Enable or Disable C3UnDemotion. 0: Disabled; <b>1: C3 Auto undemotion</b>;
+ UINT32 PkgCStateDemotion : 1; ///< <b>(Test)</b> Enable or Disable Package Cstate Demotion. <b>Disable</b>; 1: Enable
+ UINT32 PkgCStateUnDemotion : 1; ///< <b>(Test)</b> Enable or Disable Package Cstate UnDemotion. <b>Disable</b>; 1: Enable
+ UINT32 TimedMwait : 1; ///< <b>(Test)</b> Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable
+ UINT32 PlatformPowerLimit1 : 1; ///< MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power
+ UINT32 PlatformPowerLimit2 : 1; ///< MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power
+ UINT32 SkipSetBootPState : 1; ///< Choose whether to skip SetBootPState function for all APs; <b>0: Do not skip</b>; 1: Skip.
+ UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and 0x618[63]: Lock all Turbo settings; <b>0: Disable</b>; 1: Enable.
+ UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 615h lock; <b>0: Disable</b>; 1: Enable.
+ UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 601h lock; <b>0: Disable</b>; 1: Enable.
+ UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty Cycle; <b>0</b>.
+ UINT32 PowerLimit1Enable : 1; ///< Enable or Disable long duration Turbo Mode
+ UINT32 PowerLimit1ClampEnable : 1; ///< Enable or Disable clamp mode for long duration Turbo
+ UINT32 Rsvd1Bits : 4; ///< Bits reserved for DWORD alignment.
+ UINT32 PlatformPowerLimit1Time : 8; ///< MSR 0x65C[23:17]: PL1 timewindow in seconds.
+ UINT32 PmgCstCfgCtrIoMwaitRedirection : 1; ///< <b>(Test)</b> Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
+ UINT32 PmgCstCfgCtrlLock : 1; ///< <b>(Test)</b> If enabled, sets MSR 0xE2[15]; 0: Disable; <b>1: Enable</b>.
+ UINT32 ProcHotLock : 1; ///< <b>(Test)</b> If enabled, sets MSR 0x1FC[23]; <b>0: Disable</b>; 1: Enable.
+ UINT32 BiProcHot : 1; ///< <b>(Test)</b> Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>.
+ UINT32 TStates : 1; ///< <b>(Test)</b> Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
+ UINT32 DisableProcHotOut : 1; ///< <b>(Test)</b> Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
+ UINT32 DisableVrThermalAlert : 1; ///< <b>(Test)</b> Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
+ UINT32 ProcHotResponse : 1; ///< <b>(Test)</b> Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
+ UINT32 AutoThermalReporting : 1; ///< <b>(Test)</b> Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
+ UINT32 ThermalMonitor : 1; ///< <b>(Test)</b> Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>.
+ UINT32 EnableCCx : 1; ///< <b>(Optional)</b> Max Core Cstate, fused value
+ UINT32 UnlimitedCstate : 1; ///< <b>(Optional)</b> Max Core Cstate, no limit
+ UINT32 EnableC1 : 1; ///< <b>(Optional)</b> Max Core Cstate, C1
+ UINT32 EnableC3 : 1; ///< <b>(Optional)</b> Max Core Cstate, C3
+ UINT32 EnableC6 : 1; ///< <b>(Optional)</b> Max Core Cstate, C6
+ UINT32 EnableC7 : 1; ///< <b>(Optional)</b> Max Core Cstate, C7
+ UINT32 EnableC8 : 1; ///< <b>(Optional)</b> Max Core Cstate, C8
+ UINT32 EnableC9 : 1; ///< <b>(Optional)</b> Max Core Cstate, C9
+ UINT32 EnableC10 : 1; ///< <b>(Optional)</b> Max Core Cstate, C10
+ UINT32 BootPState : 1; ///< <b>(Optional)</b> Boot PState with HFM or LFM. 0: HFM; <b>1: LFM</b>;
+ UINT32 VrConfig : 1; ///< <b>(Optional)</b> Enable or Disable VR Config for VCC and VNN Rails; <b>0: Disable</b>; 1: Enable.
+ UINT32 Rsvd2Bits : 3; ///< Bits reserved for DWORD alignment.
+ UINT16 CustomPowerLimit1; ///< Custom Package Long duration turbo mode power limit in 1/8 watt units.
+ UINT16 CustomPowerLimit1Time; ///< Custom Package Long duration turbo mode time window in seconds.
+ UINT16 PowerLimit1; ///< Package Long duration turbo mode power limit in 1/8 watt units.
+ UINT16 PowerLimit2; ///< Package Short duration turbo mode power limit in 1/8 watt units.
+ UINT16 PowerLimit3; ///< Package PL3 power limit in 1/8 watt units.
+ UINT16 PowerLimit4; ///< Package PL4 power limit in 1/8 watt units.
+ UINT16 PlatformPowerLimit1Power; ///< MSR 0x65C[14:0]: Platform PL1 power in 1/8 watt units.
+ UINT16 PlatformPowerLimit2Power; ///< MSR 0x65C[46:32]]: Platform PL2 power in 1/8 watt units.
+ UINT32 PowerLimit1Time; ///< Package Long duration turbo mode time window in seconds.
+ UINT32 PowerLimit3Time; ///< Package PL3 time window range for this policy from 3ms to 64ms.
+ UINT16 DdrPowerLimit; ///< DDR Power Limits
+ UINT16 RatioLimitProgramable; ///< RatioLimitProgramable
+
+ /**
+ - 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 1-Core Ratio Limit + OC Bins.
+ - This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
+ - 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.
+ - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ - 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.
+ - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ - 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.
+ - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ **/
+ UINT8 RatioLimit[4];
+ /**
+ TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated
+ TCC will be activated at TCC Activation Temperature, in volts.
+ For SKL Y SKU, the recommended default for this policy is <b>10</b>, For all other SKUs the recommended default are <b>0</b>
+ @note The policy is recommended for validation purpose only.
+ **/
+ UINT8 TccActivationOffset;
+ UINT8 TccOffsetTimeWindow; ///< @deprecated Tcc Offset Time Window value (0 ~ 128) for Runtime Average Temperature Limit (RATL). Deprecated since revision 2
+ UINT8 S3RestoreMsrSwSmiNumber; ///< SW SMI number to restore the power Mgmt MSRs during S3 resume.
+
+ /**
+ Default power unit for following items changes to MilliWatts.
+ - POWER_MGMT_CONFIG.PowerLimit1
+ - POWER_MGMT_CONFIG.PowerLimit2
+ - POWER_MGMT_CONFIG.PowerLimit3
+ - POWER_MGMT_CONFIG.CustomPowerLimit1
+ - POWER_MGMT_CONFIG.CustomPowerLimit2
+ **/
+ CUSTOM_POWER_UNIT CustomPowerUnit; ///< Power Management Custom Power Limit Unit in milli watts.
+ MAX_PKG_C_STATE PkgCStateLimit; ///< <b>(Test)</b> This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state.
+
+ /**
+ custom processor ratio table desired by the platform
+ **/
+ UINT16 MaxRatio; ///< The maximum ratio of the custom ratio table.
+ UINT8 NumberOfEntries; ///< The number of custom ratio state entries, ranges from 2 to 16 for a valid custom ratio table.
+ UINT8 Rsvd1; ///< Reserved for DWORD alignment.
+ UINT32 Cpuid; ///< The CPU ID for which this custom ratio table applies.
+ UINT16 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The processor ratios in the custom ratio table.
+#if (MAX_CUSTOM_RATIO_TABLE_ENTRIES % 2)
+ UINT16 Rsvd2; ///< If there is an odd number of array entries, add padding for dword alignment.
+#endif
+} POWER_MGMT_CONFIG;
+
+#pragma pack(pop)
+#endif
+
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