diff options
author | Guo Mang <mang.guo@intel.com> | 2017-02-16 11:24:18 +0800 |
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committer | Guo Mang <mang.guo@intel.com> | 2017-05-09 13:03:10 +0800 |
commit | f5e2c28c29be23070b88e71bb1f0acb6a7a4a252 (patch) | |
tree | b96fe870311b6d70eb98c9b591d0056f2384a354 /Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi | |
parent | 61869ceffff6170f31ed002c755ce9fc83d9789e (diff) | |
download | edk2-platforms-f5e2c28c29be23070b88e71bb1f0acb6a7a4a252.tar.xz |
Fix MRC restore issue
MCR parameter restored in the second time of boot, so the boot time is less than the first time of boot.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi')
-rw-r--r-- | Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h index 7eb0e923db..a2da161290 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h @@ -56,10 +56,12 @@ typedef struct { UINT8 RmtMode;
UINT8 RmtCheckRun;
UINT16 RmtMarginCheckScaleHighThreshold;
+ UINT8 Reserved1;
UINT32 MsgLevelMask;
UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];
UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS];
+ UINT8 Reserved2;
UINT8 DebugMsgLevel;
UINT8 reserved[13];
} DRAM_POLICY_PPI;
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