diff options
| author | zwei4 <david.wei@intel.com> | 2018-02-14 10:44:03 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2018-02-14 10:44:03 +0800 |
| commit | a123644d1b1eb4068bc8bb41360ab04515e8a760 (patch) | |
| tree | 2e31ef126fe42273f2113297d773fbe64b56e9dc /Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc | |
| parent | d0adfa023b9d9d2e2b0c4c1e4e60e620bb1d227d (diff) | |
| download | edk2-platforms-a123644d1b1eb4068bc8bb41360ab04515e8a760.tar.xz | |
IDTP9180 PMIC Power Sequence Configuration.
Change Bit 2 (SUSPWRDNACKCFG) of Power Sequence Configuration register (offset 0x2A) to 1.
If SUSPWRDNACKCFG is 0, SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSPWRDNACK goes high in S4 state.
If SUSPWRDNACKCFG is 1, PMIC responses to SUSPWRDNACK signal.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc')
| -rw-r--r-- | Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc index ff36dccd49..935691a295 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc @@ -1,7 +1,7 @@ ## @file
# Component description file for the Broxton RC DXE libraries.
#
-# Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -33,3 +33,7 @@ HeciMsgLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.inf
SeCLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/SeCLib/SeCLib.inf
+#
+# SMBus
+#
+ ScSmbusCommonLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/PeiDxeSmmScSmbusCommonLib.inf
|