diff options
| author | Guo Mang <mang.guo@intel.com> | 2017-05-08 11:01:15 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2017-05-09 13:04:36 +0800 |
| commit | 270c7b132a6a417edff852229d05ca791ed46b7c (patch) | |
| tree | 17d2cd350510757c539226e05af0e9ed5dd85824 /Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library | |
| parent | 640308bb7c88850212810f79611455615ed294b7 (diff) | |
| download | edk2-platforms-270c7b132a6a417edff852229d05ca791ed46b7c.tar.xz | |
Upgrade core
Upgrade core to UDK2017
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library')
| -rw-r--r-- | Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h index 9d20fb6797..a651501a80 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h @@ -1,7 +1,7 @@ /** @file
Header file for PCI Express helps library implementation.
- Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -28,6 +28,9 @@ #include <Library/SteppingLib.h>
#include <Private/Library/PeiDxeSmmScPciExpressHelpersLib.h>
+
+#define DEVICE_ID_NOCARE 0xFFFF
+
#define LTR_VALUE_MASK (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7 + BIT8 + BIT9)
#define LTR_SCALE_MASK (BIT10 + BIT11 + BIT12)
|