diff options
| author | zwei4 <david.wei@intel.com> | 2017-05-11 10:19:38 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2017-05-11 10:24:34 +0800 |
| commit | 96ad5326ae4e0d6bf55100fe6b5b1631f17e5b43 (patch) | |
| tree | b82b4548d41db9442443bbe61b1758613de7cf5d /Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library | |
| parent | 836c825cf64ca43e4a8c1f7a558563a8d46d7471 (diff) | |
| download | edk2-platforms-96ad5326ae4e0d6bf55100fe6b5b1631f17e5b43.tar.xz | |
Fixed some GCC build errors.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library')
2 files changed, 4 insertions, 8 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c index 36dcf53d1c..209d6493dd 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c @@ -3,7 +3,7 @@ All function in this library is available for PEI, DXE, and SMM,
But do not support UEFI RUNTIME environment call.
- Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -214,7 +214,7 @@ ConfigureSerialIoController ( Bar = MmioRead32 (PciCfgBase + R_LPSS_IO_BAR) & 0xFFFFF000;
}
- MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, Bar);
+ MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, (UINT32)Bar);
//
// Set Memory space Enable
@@ -236,7 +236,7 @@ ConfigureSerialIoController ( do {
PchPcrRead32(0xC6, SerialIoPsf3Offsets[Controller].Psf3BaseAddress + 0x001C, &Data32);
- } while (Data32 & BIT18 != BIT18);
+ } while ((Data32 & BIT18) != BIT18);
//
// Assign BAR0 and Set Memory space Enable
@@ -254,7 +254,7 @@ ConfigureSerialIoController ( //
// Update Address Remap Register with Current BAR
//
- MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, Bar);
+ MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, (UINT32)Bar);
///
/// Get controller out of reset
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf index 2e8b9b5bf0..da4f849a13 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf @@ -35,7 +35,3 @@ MmPciLib
ScPlatformLib
-[BuildOptions]
- *_*_IA32_ASM_FLAGS = /w /Od /GL-
- *_*_IA32_CC_FLAGS = /w /Od /GL-
- *_*_X64_CC_FLAGS = /w /Od /GL-
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