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| author | zwei4 <david.wei@intel.com> | 2018-02-14 10:44:03 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2018-02-14 10:44:03 +0800 |
| commit | a123644d1b1eb4068bc8bb41360ab04515e8a760 (patch) | |
| tree | 2e31ef126fe42273f2113297d773fbe64b56e9dc /Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c | |
| parent | d0adfa023b9d9d2e2b0c4c1e4e60e620bb1d227d (diff) | |
| download | edk2-platforms-a123644d1b1eb4068bc8bb41360ab04515e8a760.tar.xz | |
IDTP9180 PMIC Power Sequence Configuration.
Change Bit 2 (SUSPWRDNACKCFG) of Power Sequence Configuration register (offset 0x2A) to 1.
If SUSPWRDNACKCFG is 0, SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSPWRDNACK goes high in S4 state.
If SUSPWRDNACKCFG is 1, PMIC responses to SUSPWRDNACK signal.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c')
| -rw-r--r-- | Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c index 6ae16f3439..021cf26c93 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c @@ -17,6 +17,8 @@ extern EFI_GUID gEfiSmbusArpMapGuid;
+SMBUS_INSTANCE *mSmbusContext;
+
/**
Execute an SMBus operation
|