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authorGuo Mang <mang.guo@intel.com>2017-02-08 18:21:03 +0800
committerGuo Mang <mang.guo@intel.com>2017-05-09 13:03:09 +0800
commit6b9f32df9d318a159493449e6e718d10fa6243e2 (patch)
tree3c28e8bf4bbf87c9f9f670296b79c13377813062 /Silicon/BroxtonSoC/BroxtonSiPkg
parent61a97ff3e685984af81eaf95481820adbd43e15f (diff)
downloadedk2-platforms-6b9f32df9d318a159493449e6e718d10fa6243e2.tar.xz
Change MRC parameter
These code cause HDMI cable of some vendor couldn't work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: lushifex <shifeix.a.lu@intel.com>
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg')
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h5
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h5
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h67
3 files changed, 9 insertions, 68 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
index 6d610a5fdb..7eb0e923db 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
@@ -1,9 +1,8 @@
-
/** @file
Dram Policy PPI is used for specifying platform
related Intel silicon information and policy setting.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -57,12 +56,10 @@ typedef struct {
UINT8 RmtMode;
UINT8 RmtCheckRun;
UINT16 RmtMarginCheckScaleHighThreshold;
- UINT8 Reserved1;
UINT32 MsgLevelMask;
UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];
UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS];
- UINT8 Reserved2;
UINT8 DebugMsgLevel;
UINT8 reserved[13];
} DRAM_POLICY_PPI;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
index 1bf9d0ffec..b19d6a05c6 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
@@ -1,5 +1,5 @@
/** @file
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ - Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -64,12 +64,10 @@ typedef struct {
UINT8 RmtMode;
UINT8 RmtCheckRun;
UINT16 RmtMarginCheckScaleHighThreshold;
- UINT8 Reserved1;
UINT32 MsgLevelMask;
UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];
UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS];
- UINT8 Reserved2;
UINT8 DebugMsgLevel;
UINT8 reserved[13];
} DRAM_POLICY_PPI;
@@ -81,6 +79,7 @@ typedef struct {
typedef enum {
Bxt = 0x00,
Bxt1,
+ BxtX,
BxtP,
BxtSeriesMax = 0xFF
} BXT_SERIES;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
index 5f65ba7c62..0d64528c45 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
@@ -28,9 +28,10 @@
#define UINTX UINT32
#endif
typedef UINT32 MMRC_STATUS;
-///
-/// MRC version description.
-///
+
+//
+// MRC version description.
+//
typedef union {
struct{
UINT8 Major; ///< Major version number
@@ -51,60 +52,6 @@ typedef union {
UINT8 Data8[4];
} MrcVersion;
-typedef union {
- UINT8 Data;
- struct {
- //
- // Rank Select Interleaving Enable. See Address Mapping section for full description.
- // 0 - Rank Select Interleaving disabled
- // 1 - Rank Select Interleaving enabled
- //
- // Bits[0:0]
- //
- UINT8 RankSelectInterleavingEnable : 1;
- //
- // Bank Address Hashing Enable. See Address Mapping section for full description.
- // 0 - Bank Address Hashing disabled
- // 1 - Bank Address Hashing enabled
- //
- // Bits[1:1]
- //
- UINT8 BankAddressHashingEnable : 1;
- //
- // CH1 CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used
- // on board designs where the CH1 CLK is not routed and left floating or stubbed out.
- // 0 = CH1 CLK is enabled
- // 1 = CH1 CLK is disabled
- //
- // Bits[2:2]
- //
- UINT8 Ch1ClkDisable : 1;
- //
- // Reserved
- //
- // Bits[3]
- //
- UINT8 Reserved : 1;
- //
- // Specifies the address mapping to be used.
- // 00b - 1KB,
- // 01b - 2KB,
- // 10b - 4KB,
- // 11b - Reserved
- //
- // Bits[5:4]
- //
- UINT8 AddressMapping : 2;
- //
- // Reserved
- //
- // Bits[7:6]
- //
- UINT8 Reserved0 : 2;
- } Bits;
-} CHANNEL_OPTION;
-
-
#ifndef ABSOLUTE
#define ABSOLUTE 1
#define RELATIVE 2
@@ -157,9 +104,6 @@ typedef enum {
#define BIT31 0x80000000
#endif
-
-#pragma pack(1)
-
typedef enum {
Pfct = 0,
PfctT,
@@ -188,6 +132,7 @@ typedef struct {
/**
Final training values stored on a per blueprint level. Needs to be per blueprint
in case of a system with more than 1 level of memory per channel.
+
**/
typedef struct {
UINT16 Values[MAX_BLUEPRINTS][MAX_NUM_ALGOS][MAX_RANKS][MAX_STROBES];
@@ -267,7 +212,6 @@ typedef struct {
UINT8 OdtHigh;
UINT16 LP4_MR0VALUE;
UINT16 LP4_MR4VALUE;
- CHANNEL_OPTION ChOption;
} CHANNEL;
typedef struct {
@@ -298,6 +242,7 @@ typedef struct {
BOOT_VARIABLE_NV_DATA BootVariableNvData;
} MRC_NV_DATA_FRAME;
+#pragma pack()
#pragma pack(pop)
#endif