diff options
| author | Leif Lindholm <leif.lindholm@linaro.org> | 2017-08-03 12:24:30 +0100 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-08-03 12:24:30 +0100 |
| commit | 600081b52debde8d06585fdaf09fac16d323670f (patch) | |
| tree | fef3287095bb56eba411c0b31c525283978b71fb /Silicon/Hisilicon/Hi1610/Drivers | |
| parent | f4d38e50c0f24eb78eb003a94f583025621c63db (diff) | |
| download | edk2-platforms-600081b52debde8d06585fdaf09fac16d323670f.tar.xz | |
Platform,Silicon: Import Hisilicon D02,D03,D05 and HiKey
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Hisilicon/Hi1610/Drivers')
8 files changed, 2244 insertions, 0 deletions
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c new file mode 100644 index 0000000000..2310ee4d18 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c @@ -0,0 +1,64 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerdesLib.h>
+
+VOID
+EFIAPI
+ExitBootServicesEventSmmu (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ SmmuConfigForOS ();
+ DEBUG((EFI_D_INFO,"SMMU ExitBootServicesEvent\n"));
+}
+
+
+EFI_STATUS
+EFIAPI
+IoInitDxeEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable)
+{
+ EFI_STATUS Status;
+ EFI_EVENT Event = NULL;
+
+ (VOID) EfiSerdesInitWrap ();
+
+ SmmuConfigForBios ();
+
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_CALLBACK,
+ ExitBootServicesEventSmmu,
+ NULL,
+ &Event
+ );
+
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] - CreateEvent failed: %r\n", __FUNCTION__,
+ __LINE__, Status));
+ }
+
+ return Status;
+}
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf new file mode 100644 index 0000000000..174e967b98 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf @@ -0,0 +1,62 @@ +#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IoInitDxe
+ FILE_GUID = e99c606a-5626-11e5-b09e-bb93f4e4c400
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = IoInitDxeEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources.common]
+ IoInitDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ DebugLib
+ BaseLib
+ PcdLib
+ CacheMaintenanceLib
+ SerdesLib
+ PlatformSysCtrlLib
+
+[Guids]
+
+[Protocols]
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+ gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+[Depex]
+ TRUE
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c new file mode 100644 index 0000000000..5fc0ead5c1 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c @@ -0,0 +1,165 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInit.h"
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PlatformPciLib.h>
+
+
+extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
+extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
+extern EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
+
+PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_ROOTBRIDGE] =
+{
+ //Port 0
+ {
+ 0x0, //Portindex
+
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ }, //PortInfo
+
+ },
+
+ //Port 1
+ {
+ 0x1, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+
+ //Port 2
+ {
+ 0x2, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+
+ //Port 3
+ {
+ 0x3, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+ //Port 4
+ {
+ 0x4, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+ //Port 5
+ {
+ 0x5, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+ //Port 6
+ {
+ 0x6, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+ //Port 7
+ {
+ 0x7, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+};
+
+EFI_STATUS
+PcieInitEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+
+{
+ UINT32 Port;
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 HostBridgeNum = 0;
+ UINT32 soctype = 0;
+ UINT32 PcieRootBridgeMask;
+
+
+ if (!OemIsMpBoot())
+ {
+ PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
+ }
+ else
+ {
+ PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
+ }
+
+ soctype = PcdGet32(Pcdsoctype);
+ for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) {
+ for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) {
+ /*
+ Host Bridge may contain lots of root bridges.
+ Each Host bridge have PCIE_MAX_ROOTBRIDGE root bridges
+ PcieRootBridgeMask have PCIE_MAX_ROOTBRIDGE*HostBridgeNum bits,
+ and each bit stands for this PCIe Port is enable or not
+ */
+ if (!(((( PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * HostBridgeNum))) >> Port) & 0x1)) {
+ continue;
+ }
+
+ Status = PciePortInit(soctype, HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
+ }
+
+ }
+ }
+
+
+ return EFI_SUCCESS;
+
+}
+
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h new file mode 100644 index 0000000000..466eb8168c --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h @@ -0,0 +1,92 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_H__
+#define __PCIE_INIT_H__
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+
+extern EFI_GUID gEfiPcieRootBridgeProtocolGuid;
+
+#define PCIE_LOG_ID 1
+
+#define PCIE_CONFIG_SPACE_SIZE 0x1000 //4k
+#define PCIE_MEMORY_SPACE_SIZE 0x800000 //8M
+#define PCIE_IO_SPACE_SIZE 0x800000 //8M
+#define PCIE_TYPE1_MEM_SIZE (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE)
+
+#define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000
+#define CONFIG_SPACE_BASE_ADDR_HIGH 0x0
+#define CONFIG_SPACE_ADDR_LIMIT (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_MEM_BASE_ADDR_LOW (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE)
+#define PCIE_MEM_BASE_ADDR_HIGH 0x0
+#define PCIE_MEM_ADDR_LIMIT (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_IO_BASE_ADDR_LOW (PCIE_MEM_ADDR_LIMIT - 1)
+#define PCIE_IO_BASE_ADDR_HIGH 0x0
+#define PCIE_IO_ADDR_LIMIT (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1)
+
+#define PCIE_INBOUND_BASE 0xD0000000
+
+
+#define PCIE_ALL_DMA_BASE (0x100000000)
+#define PCIE0_ALL_DMA_BASE (PCIE_ALL_DMA_BASE)
+#define PCIE0_ALL_DMA_SIZE (0x8000000)
+#define PCIE0_ALL_BAR01_BASE (0x10000000)
+#define PCIE0_ALL_BAR23_BASE (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE01_BASE 0x2c0000000 //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR)
+#define PCIE0_ALL_TRANSLATE01_SIZE (PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE23_BASE (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE)
+#define PCIE0_ALL_TRANSLATE23_SIZE (PCIE0_ALL_DMA_SIZE)
+
+
+#define PCIE0_REG_BASE (0xb0070000)
+#define PCIE1_REG_BASE (0xb0080000)
+#define PCIE2_REG_BASE (0xb0090000)
+#define PCIE3_REG_BASE (0xb00a0000)
+
+#define PCIE_BASE_BAR (0xf0000000)
+#define PCIE_BAR_SIZE (0x1000000)
+
+
+#define PCIE_AXI_SIZE (0x1000000)
+#define PCIE0_AXI_BASE (0xb3000000)
+#define PCIE1_AXI_BASE (PCIE0_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE2_AXI_BASE (PCIE1_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE3_AXI_BASE (PCIE2_AXI_BASE + PCIE_AXI_SIZE)
+
+#define PCIE0_CONFIG_BASE (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE1_CONFIG_BASE (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE2_CONFIG_BASE (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE3_CONFIG_BASE (PCIE3_AXI_BASE + PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE)
+
+
+#define PCIE0_TRANSLATE_BASE (0x30000000)
+#define PCIE1_TRANSLATE_BASE (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE2_TRANSLATE_BASE (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE3_TRANSLATE_BASE (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+
+#define PCIE0_BAR_BASE (PCIE0_AXI_BASE)
+#define PCIE1_BAR_BASE (PCIE1_AXI_BASE)
+#define PCIE2_BAR_BASE (PCIE2_AXI_BASE)
+#define PCIE3_BAR_BASE (PCIE3_AXI_BASE)
+
+
+#endif
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf new file mode 100644 index 0000000000..686d041cd5 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -0,0 +1,63 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PcieInitDxe
+ FILE_GUID = 2D53A704-A544-4A82-83DF-FFECF4B4AA97
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PcieInitEntry
+
+[Sources]
+ PcieInit.c
+ PcieInitLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiLib
+ BaseLib
+ DebugLib
+ ArmLib
+ TimerLib
+ PcdLib
+ IoLib
+ OemMiscLib
+
+[Protocols]
+ #gEfiPcieRootBridgeProtocolGuid
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P
+ gHisiTokenSpaceGuid.Pcdsoctype
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+
+[FeaturePcd]
+ gHisiTokenSpaceGuid.PcdIsItsSupported
+ gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable
+
+[depex]
+ TRUE
+
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c new file mode 100644 index 0000000000..8ab7fa3532 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -0,0 +1,1207 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Library/TimerLib.h>
+
+#define PCIE_SYS_REG_OFFSET 0x1000
+
+static PCIE_INIT_CFG mPcieIntCfg;
+UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000};
+UINT64 io_sub0_base = 0xa0000000;
+UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000};
+#define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000))
+UINT32 loop_test_flag[4] = {0,0,0,0};
+UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR;
+#define PcieMaxLanNum 8
+#define PCIE_PORT_NUM_IN_SICL 4 //SICL: Super IO Cluster
+
+
+extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
+extern PCIE_IATU gastr_pcie_iatu_cfg;
+extern PCIE_IATU_VA mPcieIatuTable;
+
+EFI_STATUS
+EFIAPI
+PciePortInit (
+ IN UINT32 soctype,
+ IN UINT32 HostBridgeNum,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ );
+
+VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value)
+{
+ RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+
+}
+
+UINT32 PcieRegRead(UINT32 Port, UINTN Offset)
+{
+ UINT32 Value = 0;
+
+ RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+ return Value;
+}
+
+VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
+{
+ RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+}
+
+UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
+{
+ UINT32 Value = 0;
+ RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+ return Value;
+}
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode)
+{
+ u_sc_pcie0_clkreq pcie0;
+ u_sc_pcie1_clkreq pcie1;
+ u_sc_pcie2_clkreq pcie2;
+ u_sc_pcie3_clkreq pcie3;
+
+ switch(Port)
+ {
+ case 0:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+ pcie0.Bits.pcie0_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+ break;
+ case 1:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+ pcie1.Bits.pcie1_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+ break;
+ case 2:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+ pcie2.Bits.pcie2_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+ break;
+ case 3:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+ pcie3.Bits.pcie3_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+ break;
+ default:
+ break;
+ }
+}
+
+VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN On)
+{
+ UINT32 i;
+ UINT32 Lanenum;
+ UINT32 Value;
+ UINT32 Laneid;
+ UINT32 Loopcnt;
+ UINT32 Lockedcnt[PcieMaxLanNum] = {0};
+
+ Lanenum = 8;
+ if (0x1610 == soctype)
+ {
+ if (On) {
+ /*
+ * to valid the RX, firstly, we should check and make
+ * sure the RX lanes have been steadily locked.
+ */
+ for (Loopcnt = 500 * Lanenum; Loopcnt > 0; Loopcnt--) {
+ Laneid = Loopcnt % Lanenum;
+ RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0xf4 + Laneid * 0x4, Value);
+ if (((Value >> 21) & 0x7) >= 4)
+ Lockedcnt[Laneid]++;
+ else
+ Lockedcnt[Laneid] = 0;
+ /*
+ * If we get a locked status above 8 times incessantly
+ * on anyone of the lanes, we get a stable lock.
+ */
+ if (Lockedcnt[Laneid] >= 8)
+ break;
+ if (Laneid == (Lanenum - 1))
+ MicroSecondDelay(500);
+ }
+ if (Loopcnt == 0)
+ DEBUG((EFI_D_ERROR, "pcs locked timeout!\n"));
+ for (i = 0; i < Lanenum; i++) {
+ RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
+ Value &= (~BIT14);
+ RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
+ }
+ } else {
+ for (i = 0; i < Lanenum; i++) {
+ RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
+ Value |= BIT14;
+ Value &= (~BIT15);
+ RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
+ }
+ }
+ }
+}
+/*
+ * The ltssm register is assigned in an asynchronous way, the value
+ * of register may not right in metastable state.
+ * Read the register twice to get stable value.
+ */
+VOID PcieGetLtssmValue (
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN UINT32 *Value
+ )
+{
+ UINT32 ValueA;
+ UINT32 ValueB = 0;
+ UINT32 Count;
+
+ RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueA);
+ ValueA = ValueA & PCIE_LTSSM_STATE_MASK;
+
+ Count = 0;
+ while (Count < 2) {
+
+ RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueB);
+ ValueB = ValueB & PCIE_LTSSM_STATE_MASK;
+
+ /* Get the same state in continuous two times*/
+ if (ValueA == ValueB) {
+ break;
+ }
+
+ //If the second value not equal to the first, we return the second one as the stable
+ ValueA = ValueB;
+ Count++;
+ }
+
+ *Value = ValueB;
+
+ return;
+
+}
+
+/*
+ * In some cases, the PCIe device may close part of lanes in
+ * config state of LTSSM, the hip06 RC should reconfig lane num
+ * and try to linkup again.
+ */
+VOID PcieReconfigLaneNum (
+ IN UINT32 soctype,
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ )
+{
+ EFI_STATUS Status;
+ UINT32 LtssmStatus;
+ UINT32 RegVal;
+ UINT32 LoopCnt = 0;
+ UINT32 LaneNumCnt = 0;
+ PCIE_PORT_WIDTH PortWidth = PcieCfg->PortInfo.PortWidth;
+
+ // 500 * 200us = 100ms, so it takes 100 ms must to reconfig lane numbers
+ while (LoopCnt < 500) {
+
+ /*
+ * The minimum lanenum is 1, no need to try any more.
+ */
+ if (PortWidth <= 1) {
+ DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum PortWidth <= 1 !\n"));
+ return;
+ }
+
+ /*
+ * Check the lane num config state is normal or not.
+ */
+ PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus);
+ if ((LtssmStatus == PCIE_LTSSM_CFG_LANENUM_ACPT) || (LtssmStatus == PCIE_LTSSM_CFG_COMPLETE)) {
+ LaneNumCnt++;
+ } else if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) {
+ PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus);
+ if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) {
+ break;
+ }
+ } else {
+ LaneNumCnt = 0;
+ }
+
+ /*
+ * The lane num config state is abnormal, need to reconfig
+ * the lane num and try to establish link again.
+ */
+ if (LaneNumCnt > MAX_TRY_LINK_NUM) {
+ /* Disable LTSSM */
+ RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal);
+ RegVal &= ~(LTSSM_ENABLE);
+ RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal);
+ /*
+ * Decrease the PortWidth and try to link again,
+ * the value of PortWidth 0xf (X8), 0x7(x4), 0x3(X2), 0x1(X1)
+ */
+ PcieCfg->PortInfo.PortWidth = (PCIE_PORT_WIDTH)((UINT8)PcieCfg->PortInfo.PortWidth >> 1);
+
+ Status = PciePortInit (soctype, HostBridgeNum, PcieCfg);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
+ }
+ return;
+ }
+
+ LoopCnt++;
+ /* Pcie 3.0 Spec,part 4.2.6.3.4.1: the Upstream Lanes are permitted
+ * delay up to 1 ms before transitioning to Configuration.Lanenum.Accept.
+ * So the delay time 200 us * 5(LanNumCnt) = 1ms, not beyond the reasonable range.
+ */
+ MicroSecondDelay (200);
+ }
+
+ return ;
+}
+
+EFI_STATUS
+PcieEnableItssm (
+ IN UINT32 soctype,
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ )
+{
+ PCIE_CTRL_7_U pcie_ctrl7;
+ UINT32 Value = 0;
+
+ if (Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+ Value |= BIT11|BIT30|BIT31;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+ (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
+ PcieReconfigLaneNum (soctype, HostBridgeNum, Port, PcieCfg);
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+ pcie_ctrl7.Bits.pcie_linkdown_auto_rstn_enable = 0x1;
+ pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1;
+ PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+ }
+
+}
+
+STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value;
+ UINTN RegSegmentOffset;
+
+ if (Port >= PCIE_MAX_ROOTBRIDGE) {
+ DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET;
+
+ //Enable SMMU bypass for translation
+ RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
+ //BIT13: controller master read SMMU bypass
+ //BIT12: controller master write SMMU bypass
+ //BIT10: SMMU bypass enable
+ Value |= (BIT13 | BIT12 | BIT10);
+ RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
+
+ //Switch strongly order (SO) to relaxed order (RO) for write transaction
+ RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
+ //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge
+ Value |= (BIT13 | BIT12);
+ //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction
+ Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17);
+ RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
+
+ //Force streamID for controller read operation
+ RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
+ //Force using streamID in PCIE_SYS_CTRL54_REG
+ Value &= ~(BIT30);
+ //Set streamID to 0, bit[0:15] is for request ID and should be kept
+ Value &= ~(0xff << 16);
+ RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
+
+ //Enable read and write snoopy
+ RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
+ Value |= (BIT30 | BIT28);
+ RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ PCIE_CTRL_7_U pcie_ctrl7;
+ UINT32 Value = 0;
+
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return PCIE_ERR_PARAM_INVALID;
+ }
+
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+ Value &= ~(BIT11);
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+ PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+ pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0;
+ PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+ }
+
+}
+
+
+EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)
+{
+ PCIE_EP_PCIE_CAP12_U pcie_cap12;
+
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG);
+ pcie_cap12.Bits.targetlinkspeed = Speed;
+ PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+
+ if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+ mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+ {
+ pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG);
+ pcie_cap12.Bits.targetlinkspeed = Speed;
+ PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+ PCIE_EP_PORT_LOGIC4_U pcie_logic4;
+ PCIE_EP_PORT_LOGIC22_U logic22;
+
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return PCIE_ERR_PARAM_INVALID;
+ }
+
+ pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+ pcie_logic4.Bits.linkmodeenable = Width;
+ pcie_logic4.Bits.crosslinkenable = 0;
+ pcie_logic4.Bits.fastlinkmode = 1;
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+ logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.Bits.n_fts = 0xff;
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else
+ {
+ logic22.Bits.pre_determ_num_of_lane = 3;
+ }
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+ if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+ mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+ {
+ pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG);
+ pcie_logic4.Bits.linkmodeenable = Width;
+ pcie_logic4.Bits.crosslinkenable = 0;
+ pcie_logic4.Bits.fastlinkmode = 1;
+ PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+ logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.Bits.n_fts = 0xff;
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else
+ {
+ logic22.Bits.pre_determ_num_of_lane = 3;
+ }
+ PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+ PCIE_EP_PORT_LOGIC22_U logic22;
+ PCIE_EEP_PCI_CFG_HDR15_U hdr15;
+ UINT32 Value = 0;
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+ Value &= ~(0x3f<<16);
+
+ if(Width == PCIE_WITDH_X1)
+ {
+ Value |= (0x1 << 16);
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ Value |= (0x3 << 16);
+ }
+ else if(Width == PCIE_WITDH_X4)
+ {
+ Value |= (0x7 << 16);
+ }
+ else if(Width == PCIE_WITDH_X8)
+ {
+ Value |= (0xf << 16);
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR,"Width is not valid\n"));
+ }
+
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value);
+
+ logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else if(Width == PCIE_WITDH_X4)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 4;
+ }
+ else if(Width == PCIE_WITDH_X8)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 8;
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR,"Width is not valid\n"));
+ }
+
+ logic22.UInt32 |= (0x100<<8);
+ logic22.UInt32 |= (0x1<<17);
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+ /* setup RC BARs */
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004);
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000);
+
+ /* setup interrupt pins */
+ hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG);
+ hdr15.UInt32 &= 0xffff00ff;
+ hdr15.UInt32 |= 0x00000100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32);
+
+ /* setup bus numbers */
+ Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG);
+ Value &= 0xff000000;
+ Value |= 0x00010100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value);
+
+ /* setup command register */
+ Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG);
+ Value &= 0xffff0000;
+ Value |= 0x1|0x2|0x4|0x100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType)
+{
+ PCIE_CTRL_0_U str_pcie_ctrl_0;
+
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (0x1610 == soctype)
+ {
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28);
+ }
+ else
+ {
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG);
+ if(PcieType == PCIE_END_POINT)
+ {
+ str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE;
+ }
+ else
+ {
+ str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC;
+ }
+ PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+ }
+ return EFI_SUCCESS;
+}
+
+VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT8 i = 0;
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ for (i = 0; i < PcieMaxLanNum; i++) {
+ RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+ Value |= (1 << 20); //bit 20: rxvalid enable
+ RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+ RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \
+ CH_RXTX_STATUS_CFG_EN | CH_RXTX_STATUS_CFG);
+ }
+ PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
+ RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
+ }
+ else
+ {
+ if(Port<=2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0);
+ }
+ else
+
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff);
+ }
+ }
+ return;
+}
+
+VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value;
+
+ if (0x1610 == soctype)
+ {
+ PcieRegWrite(Port, 0x890, 0x1c00);
+ }
+ else
+ PcieRegWrite(Port, 0x890, 0x1400);
+ PcieRegWrite(Port, 0x894, 0xfd7);
+
+ PcieRegWrite(Port, 0x89c, 0x0);
+ PcieRegWrite(Port, 0x898, 0xfc00);
+ PcieRegWrite(Port, 0x89c, 0x1);
+ PcieRegWrite(Port, 0x898, 0xbd00);
+ PcieRegWrite(Port, 0x89c, 0x2);
+ PcieRegWrite(Port, 0x898, 0xccc0);
+ PcieRegWrite(Port, 0x89c, 0x3);
+ PcieRegWrite(Port, 0x898, 0x8dc0);
+ PcieRegWrite(Port, 0x89c, 0x4);
+ PcieRegWrite(Port, 0x898, 0xfc0);
+ PcieRegWrite(Port, 0x89c, 0x5);
+ PcieRegWrite(Port, 0x898, 0xe46);
+ PcieRegWrite(Port, 0x89c, 0x6);
+ PcieRegWrite(Port, 0x898, 0xdc8);
+ PcieRegWrite(Port, 0x89c, 0x7);
+ PcieRegWrite(Port, 0x898, 0xcb46);
+ PcieRegWrite(Port, 0x89c, 0x8);
+ PcieRegWrite(Port, 0x898, 0x8c07);
+ PcieRegWrite(Port, 0x89c, 0x9);
+ PcieRegWrite(Port, 0x898, 0xd0b);
+ PcieRegWrite(Port, 0x8a8, 0x103ff21);
+ if (0x1610 == soctype)
+ {
+ PcieRegWrite(Port, 0x164, 0x44444444);
+ PcieRegWrite(Port, 0x168, 0x44444444);
+ PcieRegWrite(Port, 0x16c, 0x44444444);
+ PcieRegWrite(Port, 0x170, 0x44444444);
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
+ Value &= (~0x3f);
+ Value |= 0x5;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
+
+ }
+ else
+ {
+ Value = PcieRegRead(Port, 0x80);
+ Value |= 0x80;
+ PcieRegWrite(Port, 0x80, Value);
+
+ PcieRegWrite(Port, 0x184, 0x44444444);
+ PcieRegWrite(Port, 0x188, 0x44444444);
+ PcieRegWrite(Port, 0x18c, 0x44444444);
+ PcieRegWrite(Port, 0x190, 0x44444444);
+ }
+}
+
+
+EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 PortIndexInSicl;
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(soctype, HostBridgeNum, Port))
+ {
+ (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
+ }
+
+ if (0x1610 == soctype)
+ {
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ if (PortIndexInSicl <= 2) {
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
+ MicroSecondDelay(0x1000);
+ }
+ }
+ else
+ {
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 PortIndexInSicl;
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(soctype, HostBridgeNum, Port))
+ {
+ (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
+ }
+
+ if (0x1610 == soctype)
+ {
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ if (PortIndexInSicl <= 2) {
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG, 0x3);
+ MicroSecondDelay(0x1000);
+ }
+ }
+ else
+ {
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ u_sc_pcie_hilink_pcs_reset_req reset_req;
+ UINT32 PortIndexInSicl;
+ if (0x1610 == soctype)
+ {
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+ //0x1000 microseconds delay comes from experiment and
+ //should be fairly enough for this operation.
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ if(Port <= 3)
+ {
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+ MicroSecondDelay(0x1000);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ u_sc_pcie_hilink_pcs_reset_req reset_req;
+ UINT32 PortIndexInSicl;
+ if (0x1610 == soctype)
+ {
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32);
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+ //0x1000 microseconds delay comes from experimenti
+ // and should be fairly enough for this operation.
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ if(Port <= 3)
+ {
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+ MicroSecondDelay(0x1000);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock)
+{
+ UINT32 reg_clock_disable;
+ UINT32 reg_clock_enable;
+ UINT32 PortIndexInSicl;
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ if (PortIndexInSicl == 3) {
+ reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG;
+ reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG;
+ } else {
+ reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(PortIndexInSicl);
+ reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(PortIndexInSicl);
+ }
+
+ if (0x1610 == soctype)
+ {
+ if (Clock)
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_enable, 0x7);
+ else
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_disable, 0x7);
+ }
+ else
+ {
+ if (Clock)
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, 0x3);
+ else
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, 0x3);
+ }
+ return EFI_SUCCESS;
+}
+
+VOID PciePortNumSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Num)
+{
+ if (0x1610 == soctype)
+ {
+ UINT32 Value = 0;
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
+ Value &= ~(0xff);
+ Value |= Num;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
+ }
+ return;
+}
+
+VOID PcieLaneReversalSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
+ Value |= BIT16;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
+ }
+ return;
+}
+EFI_STATUS PcieMaskLinkUpInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ Value = PcieRegRead(Port, 0x120);
+ Value |= 1 << 25;
+ PcieRegWrite(Port,0x120, Value);
+ }
+ else
+ {
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ Value = PcieRegRead(Port, 0x1d0);
+ Value |= 1 << 12;
+ PcieRegWrite(Port,0x1d0, Value);
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+ }
+ return EFI_SUCCESS;
+}
+
+BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ U_SC_PCIE0_SYS_STATE4 PcieStat;
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32);
+ Value = PcieStat.UInt32;
+ if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+ return TRUE;
+ return FALSE;
+ }
+ else
+ {
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ Value = PcieStat.UInt32;
+ if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+ return TRUE;
+ return FALSE;
+ }
+}
+
+BOOLEAN PcieClockIsLock(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ RegRead( PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x504, Value);
+ return ((Value & 0x3) == 0x3);
+ }
+ else return TRUE;
+
+}
+
+VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
+{
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value);
+ Value &= ~(0xf);
+ Value |= Spd;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value);
+ return;
+ }
+ return;
+}
+
+VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 Data)
+{
+ UINT32 Value = 0;
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
+ Value &= 0x0000ffff;
+ Value |= 0x06040000;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
+ return;
+ }
+}
+
+VOID SysRegWrite(UINT32 SocType, UINT32 HostBridgeNum, UINT32 Port, UINTN Reg, UINTN Value)
+{
+ if (SocType == 0x1610) {
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value);
+ } else {
+ //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
+ //in the same hostbridge.
+ RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value);
+ }
+}
+
+void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ UINT64 GicdSetSpiReg = PcdGet64 (PcdGicDistributorBase) + 0x40;
+
+ if (FeaturePcdGet (PcdIsItsSupported)) {
+ //PCIE_SYS_CTRL24_REG is MSI Low address register
+ //PCIE_SYS_CTRL28_REG is MSI High addres register
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]);
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32);
+ } else {
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, GicdSetSpiReg);
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, GicdSetSpiReg >> 32);
+ }
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
+ Value |= (1 << 12);
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
+
+ return;
+}
+
+UINT32
+SysRegRead (
+ IN UINT32 SocType,
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN UINTN Reg
+ )
+{
+ UINT32 Value;
+ if (SocType == 0x1610) {
+ RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value);
+ } else {
+ //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
+ //in the same hostbridge.
+ RegRead (PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value);
+ }
+ return Value;
+}
+
+VOID
+DisableRcOptionRom (
+ IN UINT32 Soctype,
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN PCIE_PORT_TYPE PcieType
+)
+{
+ UINT32 Value = 0;
+ if (PcieType == PCIE_ROOT_COMPLEX) {
+ Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG);
+ Value |= BIT2; //cs2 enable
+ SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value);
+
+ Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG);
+ Value &= ~BIT0; //disable option rom
+ SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG, Value);
+
+ Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG);
+ Value &= ~BIT2; //cs2 disable
+ SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value);
+ }
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+PciePortInit (
+ IN UINT32 soctype,
+ IN UINT32 HostBridgeNum,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ )
+{
+ UINT16 Count = 0;
+ UINT32 PortIndex = PcieCfg->PortIndex;
+
+ if (PortIndex >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (0x1610 == soctype)
+ {
+ mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex];
+ DEBUG((DEBUG_INFO, "Soc type is 161x\n"));
+ }
+ else
+ {
+ mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
+ DEBUG((EFI_D_INFO, "Soc type is 660\n"));
+ }
+
+ /* assert reset signals */
+ (VOID)AssertPcieCoreReset(soctype, HostBridgeNum, PortIndex);
+ (VOID)AssertPciePcsReset(soctype, HostBridgeNum, PortIndex);
+ (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 0);
+ (VOID)DeassertPcieCoreReset(soctype, HostBridgeNum, PortIndex);
+ /* de-assert phy reset */
+ (VOID)DeassertPciePcsReset(soctype, HostBridgeNum, PortIndex);
+
+ /* de-assert core reset */
+ (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 1);
+
+ while (!PcieClockIsLock(soctype, HostBridgeNum, PortIndex)) {
+ MicroSecondDelay(1000);
+ Count++;
+ if (Count >= 50) {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d PLL Lock failed\n", HostBridgeNum, PortIndex));
+ return PCIE_ERR_LINK_OVER_TIME;
+ }
+ }
+ /* initialize phy */
+ (VOID)PciePcsInit(soctype, HostBridgeNum, PortIndex);
+
+ (VOID)PcieModeSet(soctype, HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType);
+ (VOID)PcieSpdSet(soctype, HostBridgeNum, PortIndex, 3);
+ (VOID)PciePortNumSet(soctype, HostBridgeNum, PortIndex, 0);
+ /* setup root complex */
+ (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
+
+ /* disable link up interrupt */
+ (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex);
+
+ /* Pcie Equalization*/
+ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
+
+ /* Disable RC Option Rom */
+ DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType);
+ /* assert LTSSM enable */
+ (VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg);
+ if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) {
+ //PCIe will still work even if performance tuning fails,
+ //and there is warning message inside the function to print
+ //detailed error if there is.
+ (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex);
+ }
+
+ PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex);
+ /*
+ * The default size of BAR0 in Hi1610 host bridge is 0x10000000,
+ * which will bring problem when most resource has been allocated
+ * to BAR0 in host bridge.However, we need not use BAR0 in host bridge
+ * in RC mode. Here we just disable it
+ */
+ PcieRegWrite(PortIndex, 0x10, 0);
+ (VOID)PcieWriteOwnConfig(HostBridgeNum, PortIndex, 0xa, 0x0604);
+ /* check if the link is up or not */
+ while (!PcieIsLinkUp(soctype, HostBridgeNum, PortIndex)) {
+ MicroSecondDelay(1000);
+ Count++;
+ if (Count >= 1000) {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex));
+ return PCIE_ERR_LINK_OVER_TIME;
+ }
+ }
+ DEBUG((EFI_D_INFO, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex));
+
+ PcieRegWrite(PortIndex, 0x8BC, 0);
+
+ return EFI_SUCCESS;
+}
+
+
+
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable)
+{
+ PCIE_SYS_CTRL20_U dbi_ro_enable;
+
+ if (Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG);
+ dbi_ro_enable.Bits.ro_sel = Enable;
+ PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32);
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+
+}
+
+VOID PcieDelay(UINT32 dCount)
+{
+ volatile UINT32 *uwCnt = &dCount;
+
+ while(*uwCnt > 0)
+ {
+ *uwCnt = *uwCnt - 1;
+ }
+
+}
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h new file mode 100644 index 0000000000..9a0f636d6c --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -0,0 +1,247 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_LIB_H__
+#define __PCIE_INIT_LIB_H__
+
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+#include "PcieKernelApi.h"
+
+#define PCIE_AXI_SLAVE_BASE (0xb3000000)
+#define PCIE_MAX_AXI_SIZE (0x1000000)
+#define PCIE_AXI_BASE(port) (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE)
+#define PCIE_SMMU_BASE (0xb0040000)
+
+
+#define PCIE_DMA_CHANNEL_NUM (2)
+#define PCIE_DMA_RESOURCE_MODE_SIZE (0x40000)
+#define PCIE_DMA_BURST_SIZE (0x80000000)
+
+#define PCIE_ADDR_BASE_OFFSET 0x46C00000
+#define PCIE_ADDR_BASE_HOST_ADDR (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST)
+#define NP_DDR_BASE_ADDR_HOST 0x236E00000ULL
+
+
+
+#define PCIE_GIC_MSI_ITS_BASE (0xb7010040)
+#define PCIE_INT_BASE (13824)
+#define PCIE_INT_LIMIT (PCIE_INT_BASE + 64)
+
+#define PCIE_NTB_MEM_SIZE (0x1000000)
+#define PCIE_NTB_BAR01_SIZE (0x10000) // 64K
+#define PCIE_NTB_BAR23_SIZE (0x800000) // 8M
+#define PCIE_NTB_BAR45_SIZE (0x800000)
+
+#define PCIE_IATU_END {PCIE_IATU_OUTBOUND,0,0,0}
+#define PCIE_IATU_INBOUND_MASK (0x80000000)
+#define PCIE_IATU_INDEX_MASK (0x7f)
+#define PCIE_IATU_TYPE_MASK (0x1f)
+#define PCIE_IATU_EN (0x1 << 0)
+#define PCIE_IATU_SHIFT_MODE (0x1 << 1)
+#define PCIE_IATU_BAR_MODE (0x1 << 2)
+#define PCIE_IATU_FUNC_MODE (0x1 << 3)
+#define PCIE_IATU_AT_MODE (0x1 << 4) //AT mach mode
+#define PCIE_IATU_ATTR_MODE (0x1 << 5)
+#define PCIE_IATU_TD_MODE (0x1 << 6) //TD
+#define PCIE_IATU_TC_MODE (0x1 << 7) // TC
+#define PCIE_IATU_PREFETCH_MODE (0x1 << 8)
+#define PCIE_IATU_DMA_BY_PASS_MODE (0x1 << 9) //DMA bypass untranslate
+
+#define PCIE_BAR_MASK_SIZE (0x800000)
+#define PCIE_BAR_TYPE_32 (0)
+#define PCIE_BAR_TYPE_64 (2)
+#define PCIE_BAR_PREFETCH_MODE (1)
+
+#define PCS_SDS_CFG_REG 0x204
+#define SDS_CFG_STRIDE 0x4
+#define MUX_LOS_ALOS_REG_OFFSET 0x508
+#define MUX_CFG_STRIDE 0x4
+#define CH_RXTX_STATUS_CFG_EN BIT1
+#define CH_RXTX_STATUS_CFG BIT2
+#define RegWrite(addr,data) MmioWrite32((addr), (data))
+#define RegRead(addr,data) ((data) = MmioRead32 (addr))
+
+
+typedef struct tagPcieDebugInfo
+{
+ UINT32 pcie_rdma_start_cnt;
+ UINT32 pcie_wdma_start_cnt;
+ UINT64 pcie_wdma_transfer_len;
+ UINT64 pcie_rdma_transfer_len;
+ UINT32 pcie_rdma_fail_cnt;
+ UINT32 pcie_wdma_fail_cnt;
+}pcie_debug_info_s;
+
+
+#define bdf_2_b(bdf) ((bdf >> 8) & 0xFF)
+#define bdf_2_d(bdf) ((bdf >> 3) & 0x1F)
+#define bdf_2_f(bdf) ((bdf >> 0) & 0x7)
+#define b_d_f_2_bdf(b,d,f) (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0))
+
+
+
+typedef UINT32 (*pcie_dma_func_int)(UINT32 ulErrno, UINT32 ulReserved);
+
+
+typedef struct {
+ UINT32 ViewPort; //iATU Viewport Register
+ UINT32 RegionCtrl1; //Region Control 1 Register
+ UINT32 RegionCtrl2; //Region Control 2 Register
+ UINT32 BaseLow; //Lower Base Address Register
+ UINT32 BaseHigh; //Upper Base Address Register
+ UINT32 Limit; //Limit Address Register
+ UINT32 TargetLow; //Lower Target Address Register
+ UINT32 TargetHigh; //Upper Target Address Register
+} PCIE_IATU_VA;
+
+typedef enum {
+ PCIE_IATU_OUTBOUND = 0x0,
+ PCIE_IATU_INBOUND = 0x1,
+} PCIE_IATU_DIR;
+
+typedef struct {
+ PCIE_IATU_DIR IatuType;
+ UINT64 IatuBase;
+ UINT64 IatuSize;
+ UINT64 IatuTarget;
+} PCIE_IATU;
+
+typedef struct {
+ UINT32 IatuType;
+ UINT64 IatuBase;
+ UINT32 IatuLimit;
+ UINT64 IatuTarget;
+ UINT32 Valid;
+} PCIE_IATU_HW;
+
+typedef struct {
+ UINT32 PortIndex;
+ PCIE_PORT_INFO PortInfo;
+ PCIE_IATU_HW OutBound[PCIE_MAX_OUTBOUND];
+ PCIE_IATU_HW InBound[PCIE_MAX_INBOUND];
+} PCIE_DRIVER_CFG;
+
+typedef enum {
+ PCIE_CONFIG_REG = 0x0,
+ PCIE_SYS_CONTROL = 0x1,
+} PCIE_RW_MODE;
+
+typedef union {
+ PCIE_DRIVER_CFG PcieDevice;
+ PCIE_NTB_CFG NtbDevice;
+} DRIVER_CFG_U;
+
+typedef struct {
+ VOID *MappedOutbound[PCIE_MAX_OUTBOUND];
+ UINT32 OutboundType[PCIE_MAX_OUTBOUND];
+ UINT32 OutboundEn[PCIE_MAX_OUTBOUND];
+} PCIE_MAPPED_IATU_ADDR;
+
+typedef struct {
+ BOOLEAN PortIsInitilized[PCIE_MAX_ROOTBRIDGE];
+ DRIVER_CFG_U Dev[PCIE_MAX_ROOTBRIDGE];
+ VOID *DmaResource[PCIE_MAX_ROOTBRIDGE];
+ UINT32 DmaChannel[PCIE_MAX_ROOTBRIDGE][PCIE_DMA_CHANNEL_NUM];
+ VOID *RegResource[PCIE_MAX_ROOTBRIDGE];
+ VOID *CfgResource[PCIE_MAX_ROOTBRIDGE];
+} PCIE_INIT_CFG;
+
+typedef enum {
+ PCIE_MMIO_IEP_CFG = 0x1000,
+ PCIE_MMIO_IEP_CTRL = 0x0,
+ PCIE_MMIO_EEP_CFG = 0x9000,
+ PCIE_MMIO_EEP_CTRL = 0x8000,
+} NTB_MMIO_MODE;
+
+typedef struct tagPcieDmaDes
+{
+ UINT32 uwChanCtrl;
+ UINT32 uwLen;
+ UINT32 uwLocalLow;
+ UINT32 uwLocalHigh;
+ UINT32 uwTagetLow;
+ UINT32 uwTagetHigh;
+}pcie_dma_des_s,*pcie_dma_des_ps;
+
+typedef enum {
+ PCIE_IATU_MEM,
+ PCIE_IATU_CFG = 0x4,
+ PCIE_IATU_IO
+} PCIE_IATU_OUT_TYPE;
+
+typedef enum {
+ PCIE_PAYLOAD_128B = 0,
+ PCIE_PAYLOAD_256B,
+ PCIE_PAYLOAD_512B,
+ PCIE_PAYLOAD_1024B,
+ PCIE_PAYLOAD_2048B,
+ PCIE_PAYLOAD_4096B,
+ PCIE_RESERVED_PAYLOAD
+} PCIE_PAYLOAD_SIZE;
+
+typedef struct tagPcieDfxInfo
+{
+ PCIE_EP_AER_CAP0_U aer_cap0;
+ PCIE_EP_AER_CAP1_U aer_cap1;
+ PCIE_EP_AER_CAP2_U aer_cap2;
+ PCIE_EP_AER_CAP3_U aer_cap3;
+ PCIE_EP_AER_CAP4_U aer_cap4;
+ PCIE_EP_AER_CAP5_U aer_cap5;
+ PCIE_EP_AER_CAP6_U aer_cap6;
+ UINT32 hdr_log0;
+ UINT32 hdr_log1;
+ UINT32 hdr_log2;
+ UINT32 hdr_log3;
+ PCIE_EP_AER_CAP11_U aer_cap11;
+ PCIE_EP_AER_CAP12_U aer_cap12;
+ PCIE_EP_AER_CAP13_U aer_cap13;
+
+ PCIE_EP_PORTLOGIC62_U port_logic62;
+ PCIE_EP_PORTLOGIC64_U port_logic64;
+ PCIE_EP_PORTLOGIC66_U port_logic66;
+ PCIE_EP_PORTLOGIC67_U port_logic67;
+ PCIE_EP_PORTLOGIC69_U port_logic69;
+ PCIE_EP_PORTLOGIC75_U port_logic75;
+ PCIE_EP_PORTLOGIC76_U port_logic76;
+ PCIE_EP_PORTLOGIC77_U port_logic77;
+ PCIE_EP_PORTLOGIC79_U port_logic79;
+ PCIE_EP_PORTLOGIC80_U port_logic80;
+ PCIE_EP_PORTLOGIC81_U port_logic81;
+ PCIE_EP_PORTLOGIC87_U port_logic87;
+
+ PCIE_CTRL_10_U pcie_ctrl10;
+ UINT32 slve_rerr_addr_low;
+ UINT32 slve_rerr_addr_up;
+ UINT32 slve_werr_addr_low;
+ UINT32 slve_werr_addr_up;
+ UINT32 pcie_state4;
+ UINT32 pcie_state5;
+}PCIE_DFX_INFO_S;
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode);
+
+UINT32 PcieIsLinkDown(UINT32 Port);
+
+BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port);
+
+EFI_STATUS PcieWaitLinkUp(UINT32 Port);
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
+
+#endif
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h new file mode 100644 index 0000000000..db895973dc --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h @@ -0,0 +1,344 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_KERNEL_API_H__
+#define __PCIE_KERNEL_API_H__
+
+#define PCIE_MAX_OUTBOUND (6)
+#define PCIE_MAX_INBOUND (4)
+#define PCIE3_MAX_OUTBOUND (16)
+#define PCIE3_MAX_INBOUND (16)
+
+#define PCIE_LINK_LOOP_CNT (0x1000)
+#define PCIE_IATU_ADDR_MASK (0xFFFFF000)
+#define PCIE_1M_ALIGN_SHIRFT (20)
+#define PCIE_BDF_MASK (0xF0000FFF)
+#define PCIE_BUS_SHIRFT (20)
+#define PCIE_DEV_SHIRFT (15)
+#define PCIE_FUNC_SHIRFT (12)
+
+#define PCIE_DBI_CS2_ENABLE (0x1)
+#define PCIE_DBI_CS2_DISABLE (0x0)
+
+#define PCIE_DMA_CHANLE_READ (0x1)
+#define PCIE_DMA_CHANLE_WRITE (0x0)
+
+
+#define PCIE_ERR_IATU_TABLE_NULL EFIERR (1)
+#define PCIE_ERR_LINK_OVER_TIME EFIERR (2)
+#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE EFIERR (3)
+#define PCIE_ERR_ALREADY_INIT EFIERR (4)
+#define PCIE_ERR_PARAM_INVALID EFIERR (5)
+#define PCIE_ERR_MEM_OPT_OVER EFIERR (6)
+#define PCIE_ERR_NOT_INIT EFIERR (7)
+#define PCIE_ERR_CFG_OPT_OVER EFIERR (8)
+#define PCIE_ERR_DMA_READ_CHANLE_BUSY EFIERR (9)
+#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY EFIERR (10)
+#define PCIE_ERR_DMAR_NO_RESORCE EFIERR (11)
+#define PCIE_ERR_DMAW_NO_RESORCE EFIERR (12)
+#define PCIE_ERR_DMA_OVER_MAX_RESORCE EFIERR (13)
+#define PCIE_ERR_NO_IATU_WINDOW EFIERR (14)
+#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME EFIERR (15)
+#define PCIE_ERR_DMA_MEM_ALLOC_ERROR EFIERR (16)
+#define PCIE_ERR_DMA_ABORT EFIERR (17)
+#define PCIE_ERR_UNSUPPORT_BAR_TYPE EFIERR (18)
+
+typedef enum {
+ PCIE_ROOT_COMPLEX,
+ PCIE_END_POINT,
+ PCIE_NTB_TO_NTB,
+ PCIE_NTB_TO_RP,
+} PCIE_PORT_TYPE;
+
+typedef enum {
+ PCIE_GEN1_0 = 1, //PCIE 1.0
+ PCIE_GEN2_0 = 2, //PCIE 2.0
+ PCIE_GEN3_0 = 4 //PCIE 3.0
+} PCIE_PORT_GEN;
+
+typedef enum {
+ PCIE_WITDH_X1 = 0x1,
+ PCIE_WITDH_X2 = 0x3,
+ PCIE_WITDH_X4 = 0x7,
+ PCIE_WITDH_X8 = 0xf,
+ PCIE_WITDH_INVALID
+} PCIE_PORT_WIDTH;
+
+
+typedef struct {
+ PCIE_PORT_TYPE PortType;
+ PCIE_PORT_WIDTH PortWidth;
+ PCIE_PORT_GEN PortGen;
+ UINT8 PcieLinkUp;
+} PCIE_PORT_INFO;
+
+typedef struct tagPciecfg_params
+{
+ UINT32 preemphasis;
+ UINT32 deemphasis;
+ UINT32 swing;
+ UINT32 balance;
+}pcie_cfg_params_s;
+
+typedef enum {
+ PCIE_CORRECTABLE_ERROR = 0,
+ PCIE_NON_FATAL_ERROR,
+ PCIE_FATAL_ERROR,
+ PCIE_UNSUPPORTED_REQUEST_ERROR,
+ PCIE_ALL_ERROR
+} PCIE_ERROR_TYPE;
+
+typedef union tagPcieDeviceStatus
+{
+ struct
+ {
+ UINT16 correctable_error : 1;
+ UINT16 non_fatal_error : 1;
+ UINT16 fatal_error : 1;
+ UINT16 unsupported_error : 1;
+ UINT16 aux_power : 1;
+ UINT16 transaction_pending : 1;
+ UINT16 reserved_6_15 : 10;
+ }Bits;
+
+ UINT16 Value;
+}pcie_device_status_u;
+
+
+typedef union tagPcieUcAerStatus
+{
+ struct
+ {
+ UINT32 undefined : 1 ; /* [0] undefined */
+ UINT32 reserved_1_3 : 3 ; /* reserved */
+ UINT32 data_link_proto_error : 1 ; /* Data Link Protocol Error Status */
+ UINT32 reserved_5_11 : 7 ; /* reserved */
+ UINT32 poisoned_tlp_status : 1 ; /* Poisoned TLP Status */
+ UINT32 flow_control_proto_error : 1 ; /* Flow Control Protocol Error Status */
+ UINT32 completion_time_out : 1 ; /* Completion Timeout Status */
+ UINT32 compler_abort_status : 1 ; /* Completer Abort Status */
+ UINT32 unexpect_completion_status : 1 ; /* Unexpected Completion Status */
+ UINT32 receiver_overflow_status : 1 ; /*Receiver Overflow Status */
+ UINT32 malformed_tlp_status : 1 ; /* Malformed TLP Status*/
+ UINT32 ecrc_error_status : 1 ; /* ECRC Error Status */
+ UINT32 unsupport_request_error_status : 1 ; /* Unsupported Request Error Status */
+ UINT32 reserved_21 : 1 ; /* reserved */
+ UINT32 uncorrectable_interal_error : 1 ; /* Uncorrectable Internal Error Status */
+ UINT32 reserved_23 : 1 ; /* reserved*/
+ UINT32 atomicop_egress_blocked_status : 1 ; /* AtomicOp Egress Blocked Status */
+ UINT32 tlp_prefix_blocked_error_status : 1 ; /* TLP Prefix Blocked Error Status */
+ UINT32 reserved_26_31 : 1 ; /* reserved */
+ }Bits;
+
+ UINT32 Value;
+}pcie_uc_aer_status_u;
+
+typedef union tagPcieCoAerStatus
+{
+ struct
+ {
+ UINT32 receiver_error_status : 1 ; /* Receiver Error Status */
+ UINT32 reserved_1_5 : 5 ; /* Reserved */
+ UINT32 bad_tlp_status : 1 ; /* Bad TLP Status */
+ UINT32 bad_dllp_status : 1 ; /* Bad DLLP Status */
+ UINT32 reply_num_rollover_status : 1 ; /* REPLAY_NUM Rollover Status*/
+ UINT32 reserved_9_11 : 3 ; /* Reserved */
+ UINT32 reply_timer_timeout : 1 ; /* Replay Timer Timeout Status */
+ UINT32 advisory_nonfatal_error : 1 ; /* Advisory Non-Fatal Error Status*/
+ UINT32 corrected_internal_error : 1 ; /*Corrected Internal Error Status*/
+ UINT32 reserved_15_31 : 1 ; /* Reserved */
+ }Bits;
+ UINT32 Value;
+}pcie_co_aer_status_u;
+
+typedef struct tagPcieAerStatus
+{
+ pcie_uc_aer_status_u uc_aer_status;
+ pcie_co_aer_status_u co_aer_status;
+}pcie_aer_status_s;
+
+
+
+typedef struct tagPcieLoopTestResult
+{
+ UINT32 tx_pkts_cnt;
+ UINT32 rx_pkts_cnt;
+ UINT32 error_pkts_cnt;
+ UINT32 droped_pkts_cnt;
+ UINT32 push_cnt;
+ pcie_device_status_u device_status;
+ pcie_aer_status_s pcie_aer_status;
+} pcie_loop_test_result_s;
+
+typedef struct tagPcieDmaChannelAttrs {
+ UINT32 dma_chan_en;
+ UINT32 dma_mode;
+ UINT32 channel_status;
+}pcie_dma_channel_attrs_s;
+
+typedef enum tagPcieDmaChannelStatus
+{
+ PCIE_DMA_CS_RESERVED = 0,
+ PCIE_DMA_CS_RUNNING = 1,
+ PCIE_DMA_CS_HALTED = 2,
+ PCIE_DMA_CS_STOPPED = 3
+}pcie_dma_channel_status_e;
+
+typedef enum tagPcieDmaIntType{
+ PCIE_DMA_INT_TYPE_DONE=0,
+ PCIE_DMA_INT_TYPE_ABORT,
+ PCIE_DMA_INT_ALL,
+ PCIE_DMA_INT_NONE
+}pcie_dma_int_type_e;
+
+typedef enum tagPcieMulWinSize
+{
+ WIN_SIZE_4K = 0xc,
+ WIN_SIZE_8K,
+ WIN_SIZE_16K,
+ WIN_SIZE_32K,
+ WIN_SIZE_64K,
+ WIN_SIZE_128K,
+ WIN_SIZE_256K,
+ WIN_SIZE_512K,
+ WIN_SIZE_1M,
+ WIN_SIZE_2M,
+ WIN_SIZE_4M,
+ WIN_SIZE_8M,
+ WIN_SIZE_16M,
+ WIN_SIZE_32M,
+ WIN_SIZE_64M,
+ WIN_SIZE_128M,
+ WIN_SIZE_256M,
+ WIN_SIZE_512M,
+ WIN_SIZE_1G,
+ WIN_SIZE_2G,
+ WIN_SIZE_4G,
+ WIN_SIZE_8G,
+ WIN_SIZE_16G,
+ WIN_SIZE_32G,
+ WIN_SIZE_64G,
+ WIN_SIZE_128G,
+ WIN_SIZE_256G,
+ WIN_SIZE_512G = 0x27,
+}pcie_mul_win_size_e;
+
+typedef struct tagPcieMultiCastCfg
+{
+ UINT64 multicast_base_addr;
+ pcie_mul_win_size_e base_addr_size;
+ UINT64 base_translate_addr;
+}pcie_multicast_cfg_s;
+
+typedef enum tagPcieMode
+{
+ PCIE_EP_DEVICE = 0x0,
+ LEGACY_PCIE_EP_DEVICE = 0x1,
+ RP_OF_PCIE_RC = 0x4,
+ PCIE_INVALID = 0x100
+}pcie_mode_e;
+
+typedef struct{
+ UINT32 PortIndex;
+ PCIE_PORT_INFO PortInfo;
+ UINT64 iep_bar01; /*iep bar 01*/
+ UINT64 iep_bar23;
+ UINT64 iep_bar45;
+ UINT64 iep_bar01_xlat;
+ UINT64 iep_bar23_xlat;
+ UINT64 iep_bar45_xlat;
+ UINT64 iep_bar_lmt23;
+ UINT64 iep_bar_lmt45; /*bar limit*/
+ UINT64 eep_bar01;
+ UINT64 eep_bar23;
+ UINT64 eep_bar45;
+ UINT64 eep_bar23_xlat;
+ UINT64 eep_bar45_xlat;
+ UINT64 eep_bar_lmt23; /*bar limit*/
+ UINT64 eep_bar_lmt45; /*bar limit*/
+} PCIE_NTB_CFG;
+
+extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info);
+
+extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl);
+
+extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed);
+
+extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+
+extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control);
+
+extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute);
+
+extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status);
+
+extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel);
+
+
+extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status);
+
+extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type);
+
+
+extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num);
+
+extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg);
+
+extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell);
+
+extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result);
+extern int pcie_port_reset(UINT32 Port);
+
+extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \
+pcie_device_status_u *pcie_stat);
+extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
+
+extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status);
+extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
+
+extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length);
+
+extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length);
+
+extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length);
+
+extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length);
+
+#endif
|