diff options
| author | Leif Lindholm <leif.lindholm@linaro.org> | 2017-08-03 12:24:30 +0100 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-08-03 12:24:30 +0100 |
| commit | 600081b52debde8d06585fdaf09fac16d323670f (patch) | |
| tree | fef3287095bb56eba411c0b31c525283978b71fb /Silicon/Hisilicon/Hi1610 | |
| parent | f4d38e50c0f24eb78eb003a94f583025621c63db (diff) | |
| download | edk2-platforms-600081b52debde8d06585fdaf09fac16d323670f.tar.xz | |
Platform,Silicon: Import Hisilicon D02,D03,D05 and HiKey
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Hisilicon/Hi1610')
28 files changed, 5547 insertions, 0 deletions
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c new file mode 100644 index 0000000000..2310ee4d18 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c @@ -0,0 +1,64 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerdesLib.h>
+
+VOID
+EFIAPI
+ExitBootServicesEventSmmu (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ SmmuConfigForOS ();
+ DEBUG((EFI_D_INFO,"SMMU ExitBootServicesEvent\n"));
+}
+
+
+EFI_STATUS
+EFIAPI
+IoInitDxeEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable)
+{
+ EFI_STATUS Status;
+ EFI_EVENT Event = NULL;
+
+ (VOID) EfiSerdesInitWrap ();
+
+ SmmuConfigForBios ();
+
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_CALLBACK,
+ ExitBootServicesEventSmmu,
+ NULL,
+ &Event
+ );
+
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] - CreateEvent failed: %r\n", __FUNCTION__,
+ __LINE__, Status));
+ }
+
+ return Status;
+}
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf new file mode 100644 index 0000000000..174e967b98 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf @@ -0,0 +1,62 @@ +#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IoInitDxe
+ FILE_GUID = e99c606a-5626-11e5-b09e-bb93f4e4c400
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = IoInitDxeEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources.common]
+ IoInitDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ DebugLib
+ BaseLib
+ PcdLib
+ CacheMaintenanceLib
+ SerdesLib
+ PlatformSysCtrlLib
+
+[Guids]
+
+[Protocols]
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+ gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+[Depex]
+ TRUE
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c new file mode 100644 index 0000000000..5fc0ead5c1 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c @@ -0,0 +1,165 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInit.h"
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PlatformPciLib.h>
+
+
+extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
+extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
+extern EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
+
+PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_ROOTBRIDGE] =
+{
+ //Port 0
+ {
+ 0x0, //Portindex
+
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ }, //PortInfo
+
+ },
+
+ //Port 1
+ {
+ 0x1, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+
+ //Port 2
+ {
+ 0x2, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+
+ //Port 3
+ {
+ 0x3, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+ //Port 4
+ {
+ 0x4, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+ //Port 5
+ {
+ 0x5, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+ //Port 6
+ {
+ 0x6, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+ //Port 7
+ {
+ 0x7, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+};
+
+EFI_STATUS
+PcieInitEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+
+{
+ UINT32 Port;
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 HostBridgeNum = 0;
+ UINT32 soctype = 0;
+ UINT32 PcieRootBridgeMask;
+
+
+ if (!OemIsMpBoot())
+ {
+ PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
+ }
+ else
+ {
+ PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
+ }
+
+ soctype = PcdGet32(Pcdsoctype);
+ for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) {
+ for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) {
+ /*
+ Host Bridge may contain lots of root bridges.
+ Each Host bridge have PCIE_MAX_ROOTBRIDGE root bridges
+ PcieRootBridgeMask have PCIE_MAX_ROOTBRIDGE*HostBridgeNum bits,
+ and each bit stands for this PCIe Port is enable or not
+ */
+ if (!(((( PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * HostBridgeNum))) >> Port) & 0x1)) {
+ continue;
+ }
+
+ Status = PciePortInit(soctype, HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
+ }
+
+ }
+ }
+
+
+ return EFI_SUCCESS;
+
+}
+
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h new file mode 100644 index 0000000000..466eb8168c --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h @@ -0,0 +1,92 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_H__
+#define __PCIE_INIT_H__
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+
+extern EFI_GUID gEfiPcieRootBridgeProtocolGuid;
+
+#define PCIE_LOG_ID 1
+
+#define PCIE_CONFIG_SPACE_SIZE 0x1000 //4k
+#define PCIE_MEMORY_SPACE_SIZE 0x800000 //8M
+#define PCIE_IO_SPACE_SIZE 0x800000 //8M
+#define PCIE_TYPE1_MEM_SIZE (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE)
+
+#define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000
+#define CONFIG_SPACE_BASE_ADDR_HIGH 0x0
+#define CONFIG_SPACE_ADDR_LIMIT (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_MEM_BASE_ADDR_LOW (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE)
+#define PCIE_MEM_BASE_ADDR_HIGH 0x0
+#define PCIE_MEM_ADDR_LIMIT (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_IO_BASE_ADDR_LOW (PCIE_MEM_ADDR_LIMIT - 1)
+#define PCIE_IO_BASE_ADDR_HIGH 0x0
+#define PCIE_IO_ADDR_LIMIT (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1)
+
+#define PCIE_INBOUND_BASE 0xD0000000
+
+
+#define PCIE_ALL_DMA_BASE (0x100000000)
+#define PCIE0_ALL_DMA_BASE (PCIE_ALL_DMA_BASE)
+#define PCIE0_ALL_DMA_SIZE (0x8000000)
+#define PCIE0_ALL_BAR01_BASE (0x10000000)
+#define PCIE0_ALL_BAR23_BASE (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE01_BASE 0x2c0000000 //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR)
+#define PCIE0_ALL_TRANSLATE01_SIZE (PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE23_BASE (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE)
+#define PCIE0_ALL_TRANSLATE23_SIZE (PCIE0_ALL_DMA_SIZE)
+
+
+#define PCIE0_REG_BASE (0xb0070000)
+#define PCIE1_REG_BASE (0xb0080000)
+#define PCIE2_REG_BASE (0xb0090000)
+#define PCIE3_REG_BASE (0xb00a0000)
+
+#define PCIE_BASE_BAR (0xf0000000)
+#define PCIE_BAR_SIZE (0x1000000)
+
+
+#define PCIE_AXI_SIZE (0x1000000)
+#define PCIE0_AXI_BASE (0xb3000000)
+#define PCIE1_AXI_BASE (PCIE0_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE2_AXI_BASE (PCIE1_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE3_AXI_BASE (PCIE2_AXI_BASE + PCIE_AXI_SIZE)
+
+#define PCIE0_CONFIG_BASE (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE1_CONFIG_BASE (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE2_CONFIG_BASE (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE3_CONFIG_BASE (PCIE3_AXI_BASE + PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE)
+
+
+#define PCIE0_TRANSLATE_BASE (0x30000000)
+#define PCIE1_TRANSLATE_BASE (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE2_TRANSLATE_BASE (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE3_TRANSLATE_BASE (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+
+#define PCIE0_BAR_BASE (PCIE0_AXI_BASE)
+#define PCIE1_BAR_BASE (PCIE1_AXI_BASE)
+#define PCIE2_BAR_BASE (PCIE2_AXI_BASE)
+#define PCIE3_BAR_BASE (PCIE3_AXI_BASE)
+
+
+#endif
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf new file mode 100644 index 0000000000..686d041cd5 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -0,0 +1,63 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PcieInitDxe
+ FILE_GUID = 2D53A704-A544-4A82-83DF-FFECF4B4AA97
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PcieInitEntry
+
+[Sources]
+ PcieInit.c
+ PcieInitLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiLib
+ BaseLib
+ DebugLib
+ ArmLib
+ TimerLib
+ PcdLib
+ IoLib
+ OemMiscLib
+
+[Protocols]
+ #gEfiPcieRootBridgeProtocolGuid
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P
+ gHisiTokenSpaceGuid.Pcdsoctype
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+
+[FeaturePcd]
+ gHisiTokenSpaceGuid.PcdIsItsSupported
+ gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable
+
+[depex]
+ TRUE
+
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c new file mode 100644 index 0000000000..8ab7fa3532 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -0,0 +1,1207 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Library/TimerLib.h>
+
+#define PCIE_SYS_REG_OFFSET 0x1000
+
+static PCIE_INIT_CFG mPcieIntCfg;
+UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000};
+UINT64 io_sub0_base = 0xa0000000;
+UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000};
+#define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000))
+UINT32 loop_test_flag[4] = {0,0,0,0};
+UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR;
+#define PcieMaxLanNum 8
+#define PCIE_PORT_NUM_IN_SICL 4 //SICL: Super IO Cluster
+
+
+extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
+extern PCIE_IATU gastr_pcie_iatu_cfg;
+extern PCIE_IATU_VA mPcieIatuTable;
+
+EFI_STATUS
+EFIAPI
+PciePortInit (
+ IN UINT32 soctype,
+ IN UINT32 HostBridgeNum,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ );
+
+VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value)
+{
+ RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+
+}
+
+UINT32 PcieRegRead(UINT32 Port, UINTN Offset)
+{
+ UINT32 Value = 0;
+
+ RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+ return Value;
+}
+
+VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
+{
+ RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+}
+
+UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
+{
+ UINT32 Value = 0;
+ RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+ return Value;
+}
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode)
+{
+ u_sc_pcie0_clkreq pcie0;
+ u_sc_pcie1_clkreq pcie1;
+ u_sc_pcie2_clkreq pcie2;
+ u_sc_pcie3_clkreq pcie3;
+
+ switch(Port)
+ {
+ case 0:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+ pcie0.Bits.pcie0_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+ break;
+ case 1:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+ pcie1.Bits.pcie1_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+ break;
+ case 2:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+ pcie2.Bits.pcie2_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+ break;
+ case 3:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+ pcie3.Bits.pcie3_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+ break;
+ default:
+ break;
+ }
+}
+
+VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN On)
+{
+ UINT32 i;
+ UINT32 Lanenum;
+ UINT32 Value;
+ UINT32 Laneid;
+ UINT32 Loopcnt;
+ UINT32 Lockedcnt[PcieMaxLanNum] = {0};
+
+ Lanenum = 8;
+ if (0x1610 == soctype)
+ {
+ if (On) {
+ /*
+ * to valid the RX, firstly, we should check and make
+ * sure the RX lanes have been steadily locked.
+ */
+ for (Loopcnt = 500 * Lanenum; Loopcnt > 0; Loopcnt--) {
+ Laneid = Loopcnt % Lanenum;
+ RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0xf4 + Laneid * 0x4, Value);
+ if (((Value >> 21) & 0x7) >= 4)
+ Lockedcnt[Laneid]++;
+ else
+ Lockedcnt[Laneid] = 0;
+ /*
+ * If we get a locked status above 8 times incessantly
+ * on anyone of the lanes, we get a stable lock.
+ */
+ if (Lockedcnt[Laneid] >= 8)
+ break;
+ if (Laneid == (Lanenum - 1))
+ MicroSecondDelay(500);
+ }
+ if (Loopcnt == 0)
+ DEBUG((EFI_D_ERROR, "pcs locked timeout!\n"));
+ for (i = 0; i < Lanenum; i++) {
+ RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
+ Value &= (~BIT14);
+ RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
+ }
+ } else {
+ for (i = 0; i < Lanenum; i++) {
+ RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
+ Value |= BIT14;
+ Value &= (~BIT15);
+ RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
+ }
+ }
+ }
+}
+/*
+ * The ltssm register is assigned in an asynchronous way, the value
+ * of register may not right in metastable state.
+ * Read the register twice to get stable value.
+ */
+VOID PcieGetLtssmValue (
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN UINT32 *Value
+ )
+{
+ UINT32 ValueA;
+ UINT32 ValueB = 0;
+ UINT32 Count;
+
+ RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueA);
+ ValueA = ValueA & PCIE_LTSSM_STATE_MASK;
+
+ Count = 0;
+ while (Count < 2) {
+
+ RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueB);
+ ValueB = ValueB & PCIE_LTSSM_STATE_MASK;
+
+ /* Get the same state in continuous two times*/
+ if (ValueA == ValueB) {
+ break;
+ }
+
+ //If the second value not equal to the first, we return the second one as the stable
+ ValueA = ValueB;
+ Count++;
+ }
+
+ *Value = ValueB;
+
+ return;
+
+}
+
+/*
+ * In some cases, the PCIe device may close part of lanes in
+ * config state of LTSSM, the hip06 RC should reconfig lane num
+ * and try to linkup again.
+ */
+VOID PcieReconfigLaneNum (
+ IN UINT32 soctype,
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ )
+{
+ EFI_STATUS Status;
+ UINT32 LtssmStatus;
+ UINT32 RegVal;
+ UINT32 LoopCnt = 0;
+ UINT32 LaneNumCnt = 0;
+ PCIE_PORT_WIDTH PortWidth = PcieCfg->PortInfo.PortWidth;
+
+ // 500 * 200us = 100ms, so it takes 100 ms must to reconfig lane numbers
+ while (LoopCnt < 500) {
+
+ /*
+ * The minimum lanenum is 1, no need to try any more.
+ */
+ if (PortWidth <= 1) {
+ DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum PortWidth <= 1 !\n"));
+ return;
+ }
+
+ /*
+ * Check the lane num config state is normal or not.
+ */
+ PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus);
+ if ((LtssmStatus == PCIE_LTSSM_CFG_LANENUM_ACPT) || (LtssmStatus == PCIE_LTSSM_CFG_COMPLETE)) {
+ LaneNumCnt++;
+ } else if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) {
+ PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus);
+ if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) {
+ break;
+ }
+ } else {
+ LaneNumCnt = 0;
+ }
+
+ /*
+ * The lane num config state is abnormal, need to reconfig
+ * the lane num and try to establish link again.
+ */
+ if (LaneNumCnt > MAX_TRY_LINK_NUM) {
+ /* Disable LTSSM */
+ RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal);
+ RegVal &= ~(LTSSM_ENABLE);
+ RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal);
+ /*
+ * Decrease the PortWidth and try to link again,
+ * the value of PortWidth 0xf (X8), 0x7(x4), 0x3(X2), 0x1(X1)
+ */
+ PcieCfg->PortInfo.PortWidth = (PCIE_PORT_WIDTH)((UINT8)PcieCfg->PortInfo.PortWidth >> 1);
+
+ Status = PciePortInit (soctype, HostBridgeNum, PcieCfg);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
+ }
+ return;
+ }
+
+ LoopCnt++;
+ /* Pcie 3.0 Spec,part 4.2.6.3.4.1: the Upstream Lanes are permitted
+ * delay up to 1 ms before transitioning to Configuration.Lanenum.Accept.
+ * So the delay time 200 us * 5(LanNumCnt) = 1ms, not beyond the reasonable range.
+ */
+ MicroSecondDelay (200);
+ }
+
+ return ;
+}
+
+EFI_STATUS
+PcieEnableItssm (
+ IN UINT32 soctype,
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ )
+{
+ PCIE_CTRL_7_U pcie_ctrl7;
+ UINT32 Value = 0;
+
+ if (Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+ Value |= BIT11|BIT30|BIT31;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+ (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
+ PcieReconfigLaneNum (soctype, HostBridgeNum, Port, PcieCfg);
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+ pcie_ctrl7.Bits.pcie_linkdown_auto_rstn_enable = 0x1;
+ pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1;
+ PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+ }
+
+}
+
+STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value;
+ UINTN RegSegmentOffset;
+
+ if (Port >= PCIE_MAX_ROOTBRIDGE) {
+ DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET;
+
+ //Enable SMMU bypass for translation
+ RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
+ //BIT13: controller master read SMMU bypass
+ //BIT12: controller master write SMMU bypass
+ //BIT10: SMMU bypass enable
+ Value |= (BIT13 | BIT12 | BIT10);
+ RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
+
+ //Switch strongly order (SO) to relaxed order (RO) for write transaction
+ RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
+ //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge
+ Value |= (BIT13 | BIT12);
+ //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction
+ Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17);
+ RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
+
+ //Force streamID for controller read operation
+ RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
+ //Force using streamID in PCIE_SYS_CTRL54_REG
+ Value &= ~(BIT30);
+ //Set streamID to 0, bit[0:15] is for request ID and should be kept
+ Value &= ~(0xff << 16);
+ RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
+
+ //Enable read and write snoopy
+ RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
+ Value |= (BIT30 | BIT28);
+ RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ PCIE_CTRL_7_U pcie_ctrl7;
+ UINT32 Value = 0;
+
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return PCIE_ERR_PARAM_INVALID;
+ }
+
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+ Value &= ~(BIT11);
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+ PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+ pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0;
+ PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+ }
+
+}
+
+
+EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)
+{
+ PCIE_EP_PCIE_CAP12_U pcie_cap12;
+
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG);
+ pcie_cap12.Bits.targetlinkspeed = Speed;
+ PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+
+ if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+ mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+ {
+ pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG);
+ pcie_cap12.Bits.targetlinkspeed = Speed;
+ PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+ PCIE_EP_PORT_LOGIC4_U pcie_logic4;
+ PCIE_EP_PORT_LOGIC22_U logic22;
+
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return PCIE_ERR_PARAM_INVALID;
+ }
+
+ pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+ pcie_logic4.Bits.linkmodeenable = Width;
+ pcie_logic4.Bits.crosslinkenable = 0;
+ pcie_logic4.Bits.fastlinkmode = 1;
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+ logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.Bits.n_fts = 0xff;
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else
+ {
+ logic22.Bits.pre_determ_num_of_lane = 3;
+ }
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+ if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+ mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+ {
+ pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG);
+ pcie_logic4.Bits.linkmodeenable = Width;
+ pcie_logic4.Bits.crosslinkenable = 0;
+ pcie_logic4.Bits.fastlinkmode = 1;
+ PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+ logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.Bits.n_fts = 0xff;
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else
+ {
+ logic22.Bits.pre_determ_num_of_lane = 3;
+ }
+ PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+ PCIE_EP_PORT_LOGIC22_U logic22;
+ PCIE_EEP_PCI_CFG_HDR15_U hdr15;
+ UINT32 Value = 0;
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+ Value &= ~(0x3f<<16);
+
+ if(Width == PCIE_WITDH_X1)
+ {
+ Value |= (0x1 << 16);
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ Value |= (0x3 << 16);
+ }
+ else if(Width == PCIE_WITDH_X4)
+ {
+ Value |= (0x7 << 16);
+ }
+ else if(Width == PCIE_WITDH_X8)
+ {
+ Value |= (0xf << 16);
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR,"Width is not valid\n"));
+ }
+
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value);
+
+ logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else if(Width == PCIE_WITDH_X4)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 4;
+ }
+ else if(Width == PCIE_WITDH_X8)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 8;
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR,"Width is not valid\n"));
+ }
+
+ logic22.UInt32 |= (0x100<<8);
+ logic22.UInt32 |= (0x1<<17);
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+ /* setup RC BARs */
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004);
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000);
+
+ /* setup interrupt pins */
+ hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG);
+ hdr15.UInt32 &= 0xffff00ff;
+ hdr15.UInt32 |= 0x00000100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32);
+
+ /* setup bus numbers */
+ Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG);
+ Value &= 0xff000000;
+ Value |= 0x00010100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value);
+
+ /* setup command register */
+ Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG);
+ Value &= 0xffff0000;
+ Value |= 0x1|0x2|0x4|0x100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType)
+{
+ PCIE_CTRL_0_U str_pcie_ctrl_0;
+
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (0x1610 == soctype)
+ {
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28);
+ }
+ else
+ {
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG);
+ if(PcieType == PCIE_END_POINT)
+ {
+ str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE;
+ }
+ else
+ {
+ str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC;
+ }
+ PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+ }
+ return EFI_SUCCESS;
+}
+
+VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT8 i = 0;
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ for (i = 0; i < PcieMaxLanNum; i++) {
+ RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+ Value |= (1 << 20); //bit 20: rxvalid enable
+ RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+ RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \
+ CH_RXTX_STATUS_CFG_EN | CH_RXTX_STATUS_CFG);
+ }
+ PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
+ RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
+ }
+ else
+ {
+ if(Port<=2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0);
+ }
+ else
+
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff);
+ }
+ }
+ return;
+}
+
+VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value;
+
+ if (0x1610 == soctype)
+ {
+ PcieRegWrite(Port, 0x890, 0x1c00);
+ }
+ else
+ PcieRegWrite(Port, 0x890, 0x1400);
+ PcieRegWrite(Port, 0x894, 0xfd7);
+
+ PcieRegWrite(Port, 0x89c, 0x0);
+ PcieRegWrite(Port, 0x898, 0xfc00);
+ PcieRegWrite(Port, 0x89c, 0x1);
+ PcieRegWrite(Port, 0x898, 0xbd00);
+ PcieRegWrite(Port, 0x89c, 0x2);
+ PcieRegWrite(Port, 0x898, 0xccc0);
+ PcieRegWrite(Port, 0x89c, 0x3);
+ PcieRegWrite(Port, 0x898, 0x8dc0);
+ PcieRegWrite(Port, 0x89c, 0x4);
+ PcieRegWrite(Port, 0x898, 0xfc0);
+ PcieRegWrite(Port, 0x89c, 0x5);
+ PcieRegWrite(Port, 0x898, 0xe46);
+ PcieRegWrite(Port, 0x89c, 0x6);
+ PcieRegWrite(Port, 0x898, 0xdc8);
+ PcieRegWrite(Port, 0x89c, 0x7);
+ PcieRegWrite(Port, 0x898, 0xcb46);
+ PcieRegWrite(Port, 0x89c, 0x8);
+ PcieRegWrite(Port, 0x898, 0x8c07);
+ PcieRegWrite(Port, 0x89c, 0x9);
+ PcieRegWrite(Port, 0x898, 0xd0b);
+ PcieRegWrite(Port, 0x8a8, 0x103ff21);
+ if (0x1610 == soctype)
+ {
+ PcieRegWrite(Port, 0x164, 0x44444444);
+ PcieRegWrite(Port, 0x168, 0x44444444);
+ PcieRegWrite(Port, 0x16c, 0x44444444);
+ PcieRegWrite(Port, 0x170, 0x44444444);
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
+ Value &= (~0x3f);
+ Value |= 0x5;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
+
+ }
+ else
+ {
+ Value = PcieRegRead(Port, 0x80);
+ Value |= 0x80;
+ PcieRegWrite(Port, 0x80, Value);
+
+ PcieRegWrite(Port, 0x184, 0x44444444);
+ PcieRegWrite(Port, 0x188, 0x44444444);
+ PcieRegWrite(Port, 0x18c, 0x44444444);
+ PcieRegWrite(Port, 0x190, 0x44444444);
+ }
+}
+
+
+EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 PortIndexInSicl;
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(soctype, HostBridgeNum, Port))
+ {
+ (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
+ }
+
+ if (0x1610 == soctype)
+ {
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ if (PortIndexInSicl <= 2) {
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
+ MicroSecondDelay(0x1000);
+ }
+ }
+ else
+ {
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 PortIndexInSicl;
+ if(Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(soctype, HostBridgeNum, Port))
+ {
+ (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
+ }
+
+ if (0x1610 == soctype)
+ {
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ if (PortIndexInSicl <= 2) {
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG, 0x3);
+ MicroSecondDelay(0x1000);
+ }
+ }
+ else
+ {
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ u_sc_pcie_hilink_pcs_reset_req reset_req;
+ UINT32 PortIndexInSicl;
+ if (0x1610 == soctype)
+ {
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+ //0x1000 microseconds delay comes from experiment and
+ //should be fairly enough for this operation.
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ if(Port <= 3)
+ {
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+ MicroSecondDelay(0x1000);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ u_sc_pcie_hilink_pcs_reset_req reset_req;
+ UINT32 PortIndexInSicl;
+ if (0x1610 == soctype)
+ {
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32);
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+ //0x1000 microseconds delay comes from experimenti
+ // and should be fairly enough for this operation.
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ if(Port <= 3)
+ {
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+ MicroSecondDelay(0x1000);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock)
+{
+ UINT32 reg_clock_disable;
+ UINT32 reg_clock_enable;
+ UINT32 PortIndexInSicl;
+ PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+ if (PortIndexInSicl == 3) {
+ reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG;
+ reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG;
+ } else {
+ reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(PortIndexInSicl);
+ reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(PortIndexInSicl);
+ }
+
+ if (0x1610 == soctype)
+ {
+ if (Clock)
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_enable, 0x7);
+ else
+ RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_disable, 0x7);
+ }
+ else
+ {
+ if (Clock)
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, 0x3);
+ else
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, 0x3);
+ }
+ return EFI_SUCCESS;
+}
+
+VOID PciePortNumSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Num)
+{
+ if (0x1610 == soctype)
+ {
+ UINT32 Value = 0;
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
+ Value &= ~(0xff);
+ Value |= Num;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
+ }
+ return;
+}
+
+VOID PcieLaneReversalSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
+ Value |= BIT16;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
+ }
+ return;
+}
+EFI_STATUS PcieMaskLinkUpInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ Value = PcieRegRead(Port, 0x120);
+ Value |= 1 << 25;
+ PcieRegWrite(Port,0x120, Value);
+ }
+ else
+ {
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ Value = PcieRegRead(Port, 0x1d0);
+ Value |= 1 << 12;
+ PcieRegWrite(Port,0x1d0, Value);
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+ }
+ return EFI_SUCCESS;
+}
+
+BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ U_SC_PCIE0_SYS_STATE4 PcieStat;
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32);
+ Value = PcieStat.UInt32;
+ if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+ return TRUE;
+ return FALSE;
+ }
+ else
+ {
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ Value = PcieStat.UInt32;
+ if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+ return TRUE;
+ return FALSE;
+ }
+}
+
+BOOLEAN PcieClockIsLock(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ RegRead( PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x504, Value);
+ return ((Value & 0x3) == 0x3);
+ }
+ else return TRUE;
+
+}
+
+VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
+{
+ UINT32 Value = 0;
+ if (0x1610 == soctype)
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value);
+ Value &= ~(0xf);
+ Value |= Spd;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value);
+ return;
+ }
+ return;
+}
+
+VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 Data)
+{
+ UINT32 Value = 0;
+ {
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
+ Value &= 0x0000ffff;
+ Value |= 0x06040000;
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
+ return;
+ }
+}
+
+VOID SysRegWrite(UINT32 SocType, UINT32 HostBridgeNum, UINT32 Port, UINTN Reg, UINTN Value)
+{
+ if (SocType == 0x1610) {
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value);
+ } else {
+ //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
+ //in the same hostbridge.
+ RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value);
+ }
+}
+
+void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ UINT64 GicdSetSpiReg = PcdGet64 (PcdGicDistributorBase) + 0x40;
+
+ if (FeaturePcdGet (PcdIsItsSupported)) {
+ //PCIE_SYS_CTRL24_REG is MSI Low address register
+ //PCIE_SYS_CTRL28_REG is MSI High addres register
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]);
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32);
+ } else {
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, GicdSetSpiReg);
+ SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, GicdSetSpiReg >> 32);
+ }
+ RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
+ Value |= (1 << 12);
+ RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
+
+ return;
+}
+
+UINT32
+SysRegRead (
+ IN UINT32 SocType,
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN UINTN Reg
+ )
+{
+ UINT32 Value;
+ if (SocType == 0x1610) {
+ RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value);
+ } else {
+ //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
+ //in the same hostbridge.
+ RegRead (PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value);
+ }
+ return Value;
+}
+
+VOID
+DisableRcOptionRom (
+ IN UINT32 Soctype,
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN PCIE_PORT_TYPE PcieType
+)
+{
+ UINT32 Value = 0;
+ if (PcieType == PCIE_ROOT_COMPLEX) {
+ Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG);
+ Value |= BIT2; //cs2 enable
+ SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value);
+
+ Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG);
+ Value &= ~BIT0; //disable option rom
+ SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG, Value);
+
+ Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG);
+ Value &= ~BIT2; //cs2 disable
+ SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value);
+ }
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+PciePortInit (
+ IN UINT32 soctype,
+ IN UINT32 HostBridgeNum,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ )
+{
+ UINT16 Count = 0;
+ UINT32 PortIndex = PcieCfg->PortIndex;
+
+ if (PortIndex >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (0x1610 == soctype)
+ {
+ mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex];
+ DEBUG((DEBUG_INFO, "Soc type is 161x\n"));
+ }
+ else
+ {
+ mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
+ DEBUG((EFI_D_INFO, "Soc type is 660\n"));
+ }
+
+ /* assert reset signals */
+ (VOID)AssertPcieCoreReset(soctype, HostBridgeNum, PortIndex);
+ (VOID)AssertPciePcsReset(soctype, HostBridgeNum, PortIndex);
+ (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 0);
+ (VOID)DeassertPcieCoreReset(soctype, HostBridgeNum, PortIndex);
+ /* de-assert phy reset */
+ (VOID)DeassertPciePcsReset(soctype, HostBridgeNum, PortIndex);
+
+ /* de-assert core reset */
+ (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 1);
+
+ while (!PcieClockIsLock(soctype, HostBridgeNum, PortIndex)) {
+ MicroSecondDelay(1000);
+ Count++;
+ if (Count >= 50) {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d PLL Lock failed\n", HostBridgeNum, PortIndex));
+ return PCIE_ERR_LINK_OVER_TIME;
+ }
+ }
+ /* initialize phy */
+ (VOID)PciePcsInit(soctype, HostBridgeNum, PortIndex);
+
+ (VOID)PcieModeSet(soctype, HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType);
+ (VOID)PcieSpdSet(soctype, HostBridgeNum, PortIndex, 3);
+ (VOID)PciePortNumSet(soctype, HostBridgeNum, PortIndex, 0);
+ /* setup root complex */
+ (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
+
+ /* disable link up interrupt */
+ (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex);
+
+ /* Pcie Equalization*/
+ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
+
+ /* Disable RC Option Rom */
+ DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType);
+ /* assert LTSSM enable */
+ (VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg);
+ if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) {
+ //PCIe will still work even if performance tuning fails,
+ //and there is warning message inside the function to print
+ //detailed error if there is.
+ (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex);
+ }
+
+ PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex);
+ /*
+ * The default size of BAR0 in Hi1610 host bridge is 0x10000000,
+ * which will bring problem when most resource has been allocated
+ * to BAR0 in host bridge.However, we need not use BAR0 in host bridge
+ * in RC mode. Here we just disable it
+ */
+ PcieRegWrite(PortIndex, 0x10, 0);
+ (VOID)PcieWriteOwnConfig(HostBridgeNum, PortIndex, 0xa, 0x0604);
+ /* check if the link is up or not */
+ while (!PcieIsLinkUp(soctype, HostBridgeNum, PortIndex)) {
+ MicroSecondDelay(1000);
+ Count++;
+ if (Count >= 1000) {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex));
+ return PCIE_ERR_LINK_OVER_TIME;
+ }
+ }
+ DEBUG((EFI_D_INFO, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex));
+
+ PcieRegWrite(PortIndex, 0x8BC, 0);
+
+ return EFI_SUCCESS;
+}
+
+
+
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable)
+{
+ PCIE_SYS_CTRL20_U dbi_ro_enable;
+
+ if (Port >= PCIE_MAX_ROOTBRIDGE) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG);
+ dbi_ro_enable.Bits.ro_sel = Enable;
+ PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32);
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+
+}
+
+VOID PcieDelay(UINT32 dCount)
+{
+ volatile UINT32 *uwCnt = &dCount;
+
+ while(*uwCnt > 0)
+ {
+ *uwCnt = *uwCnt - 1;
+ }
+
+}
+
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h new file mode 100644 index 0000000000..9a0f636d6c --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -0,0 +1,247 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_LIB_H__
+#define __PCIE_INIT_LIB_H__
+
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+#include "PcieKernelApi.h"
+
+#define PCIE_AXI_SLAVE_BASE (0xb3000000)
+#define PCIE_MAX_AXI_SIZE (0x1000000)
+#define PCIE_AXI_BASE(port) (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE)
+#define PCIE_SMMU_BASE (0xb0040000)
+
+
+#define PCIE_DMA_CHANNEL_NUM (2)
+#define PCIE_DMA_RESOURCE_MODE_SIZE (0x40000)
+#define PCIE_DMA_BURST_SIZE (0x80000000)
+
+#define PCIE_ADDR_BASE_OFFSET 0x46C00000
+#define PCIE_ADDR_BASE_HOST_ADDR (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST)
+#define NP_DDR_BASE_ADDR_HOST 0x236E00000ULL
+
+
+
+#define PCIE_GIC_MSI_ITS_BASE (0xb7010040)
+#define PCIE_INT_BASE (13824)
+#define PCIE_INT_LIMIT (PCIE_INT_BASE + 64)
+
+#define PCIE_NTB_MEM_SIZE (0x1000000)
+#define PCIE_NTB_BAR01_SIZE (0x10000) // 64K
+#define PCIE_NTB_BAR23_SIZE (0x800000) // 8M
+#define PCIE_NTB_BAR45_SIZE (0x800000)
+
+#define PCIE_IATU_END {PCIE_IATU_OUTBOUND,0,0,0}
+#define PCIE_IATU_INBOUND_MASK (0x80000000)
+#define PCIE_IATU_INDEX_MASK (0x7f)
+#define PCIE_IATU_TYPE_MASK (0x1f)
+#define PCIE_IATU_EN (0x1 << 0)
+#define PCIE_IATU_SHIFT_MODE (0x1 << 1)
+#define PCIE_IATU_BAR_MODE (0x1 << 2)
+#define PCIE_IATU_FUNC_MODE (0x1 << 3)
+#define PCIE_IATU_AT_MODE (0x1 << 4) //AT mach mode
+#define PCIE_IATU_ATTR_MODE (0x1 << 5)
+#define PCIE_IATU_TD_MODE (0x1 << 6) //TD
+#define PCIE_IATU_TC_MODE (0x1 << 7) // TC
+#define PCIE_IATU_PREFETCH_MODE (0x1 << 8)
+#define PCIE_IATU_DMA_BY_PASS_MODE (0x1 << 9) //DMA bypass untranslate
+
+#define PCIE_BAR_MASK_SIZE (0x800000)
+#define PCIE_BAR_TYPE_32 (0)
+#define PCIE_BAR_TYPE_64 (2)
+#define PCIE_BAR_PREFETCH_MODE (1)
+
+#define PCS_SDS_CFG_REG 0x204
+#define SDS_CFG_STRIDE 0x4
+#define MUX_LOS_ALOS_REG_OFFSET 0x508
+#define MUX_CFG_STRIDE 0x4
+#define CH_RXTX_STATUS_CFG_EN BIT1
+#define CH_RXTX_STATUS_CFG BIT2
+#define RegWrite(addr,data) MmioWrite32((addr), (data))
+#define RegRead(addr,data) ((data) = MmioRead32 (addr))
+
+
+typedef struct tagPcieDebugInfo
+{
+ UINT32 pcie_rdma_start_cnt;
+ UINT32 pcie_wdma_start_cnt;
+ UINT64 pcie_wdma_transfer_len;
+ UINT64 pcie_rdma_transfer_len;
+ UINT32 pcie_rdma_fail_cnt;
+ UINT32 pcie_wdma_fail_cnt;
+}pcie_debug_info_s;
+
+
+#define bdf_2_b(bdf) ((bdf >> 8) & 0xFF)
+#define bdf_2_d(bdf) ((bdf >> 3) & 0x1F)
+#define bdf_2_f(bdf) ((bdf >> 0) & 0x7)
+#define b_d_f_2_bdf(b,d,f) (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0))
+
+
+
+typedef UINT32 (*pcie_dma_func_int)(UINT32 ulErrno, UINT32 ulReserved);
+
+
+typedef struct {
+ UINT32 ViewPort; //iATU Viewport Register
+ UINT32 RegionCtrl1; //Region Control 1 Register
+ UINT32 RegionCtrl2; //Region Control 2 Register
+ UINT32 BaseLow; //Lower Base Address Register
+ UINT32 BaseHigh; //Upper Base Address Register
+ UINT32 Limit; //Limit Address Register
+ UINT32 TargetLow; //Lower Target Address Register
+ UINT32 TargetHigh; //Upper Target Address Register
+} PCIE_IATU_VA;
+
+typedef enum {
+ PCIE_IATU_OUTBOUND = 0x0,
+ PCIE_IATU_INBOUND = 0x1,
+} PCIE_IATU_DIR;
+
+typedef struct {
+ PCIE_IATU_DIR IatuType;
+ UINT64 IatuBase;
+ UINT64 IatuSize;
+ UINT64 IatuTarget;
+} PCIE_IATU;
+
+typedef struct {
+ UINT32 IatuType;
+ UINT64 IatuBase;
+ UINT32 IatuLimit;
+ UINT64 IatuTarget;
+ UINT32 Valid;
+} PCIE_IATU_HW;
+
+typedef struct {
+ UINT32 PortIndex;
+ PCIE_PORT_INFO PortInfo;
+ PCIE_IATU_HW OutBound[PCIE_MAX_OUTBOUND];
+ PCIE_IATU_HW InBound[PCIE_MAX_INBOUND];
+} PCIE_DRIVER_CFG;
+
+typedef enum {
+ PCIE_CONFIG_REG = 0x0,
+ PCIE_SYS_CONTROL = 0x1,
+} PCIE_RW_MODE;
+
+typedef union {
+ PCIE_DRIVER_CFG PcieDevice;
+ PCIE_NTB_CFG NtbDevice;
+} DRIVER_CFG_U;
+
+typedef struct {
+ VOID *MappedOutbound[PCIE_MAX_OUTBOUND];
+ UINT32 OutboundType[PCIE_MAX_OUTBOUND];
+ UINT32 OutboundEn[PCIE_MAX_OUTBOUND];
+} PCIE_MAPPED_IATU_ADDR;
+
+typedef struct {
+ BOOLEAN PortIsInitilized[PCIE_MAX_ROOTBRIDGE];
+ DRIVER_CFG_U Dev[PCIE_MAX_ROOTBRIDGE];
+ VOID *DmaResource[PCIE_MAX_ROOTBRIDGE];
+ UINT32 DmaChannel[PCIE_MAX_ROOTBRIDGE][PCIE_DMA_CHANNEL_NUM];
+ VOID *RegResource[PCIE_MAX_ROOTBRIDGE];
+ VOID *CfgResource[PCIE_MAX_ROOTBRIDGE];
+} PCIE_INIT_CFG;
+
+typedef enum {
+ PCIE_MMIO_IEP_CFG = 0x1000,
+ PCIE_MMIO_IEP_CTRL = 0x0,
+ PCIE_MMIO_EEP_CFG = 0x9000,
+ PCIE_MMIO_EEP_CTRL = 0x8000,
+} NTB_MMIO_MODE;
+
+typedef struct tagPcieDmaDes
+{
+ UINT32 uwChanCtrl;
+ UINT32 uwLen;
+ UINT32 uwLocalLow;
+ UINT32 uwLocalHigh;
+ UINT32 uwTagetLow;
+ UINT32 uwTagetHigh;
+}pcie_dma_des_s,*pcie_dma_des_ps;
+
+typedef enum {
+ PCIE_IATU_MEM,
+ PCIE_IATU_CFG = 0x4,
+ PCIE_IATU_IO
+} PCIE_IATU_OUT_TYPE;
+
+typedef enum {
+ PCIE_PAYLOAD_128B = 0,
+ PCIE_PAYLOAD_256B,
+ PCIE_PAYLOAD_512B,
+ PCIE_PAYLOAD_1024B,
+ PCIE_PAYLOAD_2048B,
+ PCIE_PAYLOAD_4096B,
+ PCIE_RESERVED_PAYLOAD
+} PCIE_PAYLOAD_SIZE;
+
+typedef struct tagPcieDfxInfo
+{
+ PCIE_EP_AER_CAP0_U aer_cap0;
+ PCIE_EP_AER_CAP1_U aer_cap1;
+ PCIE_EP_AER_CAP2_U aer_cap2;
+ PCIE_EP_AER_CAP3_U aer_cap3;
+ PCIE_EP_AER_CAP4_U aer_cap4;
+ PCIE_EP_AER_CAP5_U aer_cap5;
+ PCIE_EP_AER_CAP6_U aer_cap6;
+ UINT32 hdr_log0;
+ UINT32 hdr_log1;
+ UINT32 hdr_log2;
+ UINT32 hdr_log3;
+ PCIE_EP_AER_CAP11_U aer_cap11;
+ PCIE_EP_AER_CAP12_U aer_cap12;
+ PCIE_EP_AER_CAP13_U aer_cap13;
+
+ PCIE_EP_PORTLOGIC62_U port_logic62;
+ PCIE_EP_PORTLOGIC64_U port_logic64;
+ PCIE_EP_PORTLOGIC66_U port_logic66;
+ PCIE_EP_PORTLOGIC67_U port_logic67;
+ PCIE_EP_PORTLOGIC69_U port_logic69;
+ PCIE_EP_PORTLOGIC75_U port_logic75;
+ PCIE_EP_PORTLOGIC76_U port_logic76;
+ PCIE_EP_PORTLOGIC77_U port_logic77;
+ PCIE_EP_PORTLOGIC79_U port_logic79;
+ PCIE_EP_PORTLOGIC80_U port_logic80;
+ PCIE_EP_PORTLOGIC81_U port_logic81;
+ PCIE_EP_PORTLOGIC87_U port_logic87;
+
+ PCIE_CTRL_10_U pcie_ctrl10;
+ UINT32 slve_rerr_addr_low;
+ UINT32 slve_rerr_addr_up;
+ UINT32 slve_werr_addr_low;
+ UINT32 slve_werr_addr_up;
+ UINT32 pcie_state4;
+ UINT32 pcie_state5;
+}PCIE_DFX_INFO_S;
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode);
+
+UINT32 PcieIsLinkDown(UINT32 Port);
+
+BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port);
+
+EFI_STATUS PcieWaitLinkUp(UINT32 Port);
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
+
+#endif
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h new file mode 100644 index 0000000000..db895973dc --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h @@ -0,0 +1,344 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_KERNEL_API_H__
+#define __PCIE_KERNEL_API_H__
+
+#define PCIE_MAX_OUTBOUND (6)
+#define PCIE_MAX_INBOUND (4)
+#define PCIE3_MAX_OUTBOUND (16)
+#define PCIE3_MAX_INBOUND (16)
+
+#define PCIE_LINK_LOOP_CNT (0x1000)
+#define PCIE_IATU_ADDR_MASK (0xFFFFF000)
+#define PCIE_1M_ALIGN_SHIRFT (20)
+#define PCIE_BDF_MASK (0xF0000FFF)
+#define PCIE_BUS_SHIRFT (20)
+#define PCIE_DEV_SHIRFT (15)
+#define PCIE_FUNC_SHIRFT (12)
+
+#define PCIE_DBI_CS2_ENABLE (0x1)
+#define PCIE_DBI_CS2_DISABLE (0x0)
+
+#define PCIE_DMA_CHANLE_READ (0x1)
+#define PCIE_DMA_CHANLE_WRITE (0x0)
+
+
+#define PCIE_ERR_IATU_TABLE_NULL EFIERR (1)
+#define PCIE_ERR_LINK_OVER_TIME EFIERR (2)
+#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE EFIERR (3)
+#define PCIE_ERR_ALREADY_INIT EFIERR (4)
+#define PCIE_ERR_PARAM_INVALID EFIERR (5)
+#define PCIE_ERR_MEM_OPT_OVER EFIERR (6)
+#define PCIE_ERR_NOT_INIT EFIERR (7)
+#define PCIE_ERR_CFG_OPT_OVER EFIERR (8)
+#define PCIE_ERR_DMA_READ_CHANLE_BUSY EFIERR (9)
+#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY EFIERR (10)
+#define PCIE_ERR_DMAR_NO_RESORCE EFIERR (11)
+#define PCIE_ERR_DMAW_NO_RESORCE EFIERR (12)
+#define PCIE_ERR_DMA_OVER_MAX_RESORCE EFIERR (13)
+#define PCIE_ERR_NO_IATU_WINDOW EFIERR (14)
+#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME EFIERR (15)
+#define PCIE_ERR_DMA_MEM_ALLOC_ERROR EFIERR (16)
+#define PCIE_ERR_DMA_ABORT EFIERR (17)
+#define PCIE_ERR_UNSUPPORT_BAR_TYPE EFIERR (18)
+
+typedef enum {
+ PCIE_ROOT_COMPLEX,
+ PCIE_END_POINT,
+ PCIE_NTB_TO_NTB,
+ PCIE_NTB_TO_RP,
+} PCIE_PORT_TYPE;
+
+typedef enum {
+ PCIE_GEN1_0 = 1, //PCIE 1.0
+ PCIE_GEN2_0 = 2, //PCIE 2.0
+ PCIE_GEN3_0 = 4 //PCIE 3.0
+} PCIE_PORT_GEN;
+
+typedef enum {
+ PCIE_WITDH_X1 = 0x1,
+ PCIE_WITDH_X2 = 0x3,
+ PCIE_WITDH_X4 = 0x7,
+ PCIE_WITDH_X8 = 0xf,
+ PCIE_WITDH_INVALID
+} PCIE_PORT_WIDTH;
+
+
+typedef struct {
+ PCIE_PORT_TYPE PortType;
+ PCIE_PORT_WIDTH PortWidth;
+ PCIE_PORT_GEN PortGen;
+ UINT8 PcieLinkUp;
+} PCIE_PORT_INFO;
+
+typedef struct tagPciecfg_params
+{
+ UINT32 preemphasis;
+ UINT32 deemphasis;
+ UINT32 swing;
+ UINT32 balance;
+}pcie_cfg_params_s;
+
+typedef enum {
+ PCIE_CORRECTABLE_ERROR = 0,
+ PCIE_NON_FATAL_ERROR,
+ PCIE_FATAL_ERROR,
+ PCIE_UNSUPPORTED_REQUEST_ERROR,
+ PCIE_ALL_ERROR
+} PCIE_ERROR_TYPE;
+
+typedef union tagPcieDeviceStatus
+{
+ struct
+ {
+ UINT16 correctable_error : 1;
+ UINT16 non_fatal_error : 1;
+ UINT16 fatal_error : 1;
+ UINT16 unsupported_error : 1;
+ UINT16 aux_power : 1;
+ UINT16 transaction_pending : 1;
+ UINT16 reserved_6_15 : 10;
+ }Bits;
+
+ UINT16 Value;
+}pcie_device_status_u;
+
+
+typedef union tagPcieUcAerStatus
+{
+ struct
+ {
+ UINT32 undefined : 1 ; /* [0] undefined */
+ UINT32 reserved_1_3 : 3 ; /* reserved */
+ UINT32 data_link_proto_error : 1 ; /* Data Link Protocol Error Status */
+ UINT32 reserved_5_11 : 7 ; /* reserved */
+ UINT32 poisoned_tlp_status : 1 ; /* Poisoned TLP Status */
+ UINT32 flow_control_proto_error : 1 ; /* Flow Control Protocol Error Status */
+ UINT32 completion_time_out : 1 ; /* Completion Timeout Status */
+ UINT32 compler_abort_status : 1 ; /* Completer Abort Status */
+ UINT32 unexpect_completion_status : 1 ; /* Unexpected Completion Status */
+ UINT32 receiver_overflow_status : 1 ; /*Receiver Overflow Status */
+ UINT32 malformed_tlp_status : 1 ; /* Malformed TLP Status*/
+ UINT32 ecrc_error_status : 1 ; /* ECRC Error Status */
+ UINT32 unsupport_request_error_status : 1 ; /* Unsupported Request Error Status */
+ UINT32 reserved_21 : 1 ; /* reserved */
+ UINT32 uncorrectable_interal_error : 1 ; /* Uncorrectable Internal Error Status */
+ UINT32 reserved_23 : 1 ; /* reserved*/
+ UINT32 atomicop_egress_blocked_status : 1 ; /* AtomicOp Egress Blocked Status */
+ UINT32 tlp_prefix_blocked_error_status : 1 ; /* TLP Prefix Blocked Error Status */
+ UINT32 reserved_26_31 : 1 ; /* reserved */
+ }Bits;
+
+ UINT32 Value;
+}pcie_uc_aer_status_u;
+
+typedef union tagPcieCoAerStatus
+{
+ struct
+ {
+ UINT32 receiver_error_status : 1 ; /* Receiver Error Status */
+ UINT32 reserved_1_5 : 5 ; /* Reserved */
+ UINT32 bad_tlp_status : 1 ; /* Bad TLP Status */
+ UINT32 bad_dllp_status : 1 ; /* Bad DLLP Status */
+ UINT32 reply_num_rollover_status : 1 ; /* REPLAY_NUM Rollover Status*/
+ UINT32 reserved_9_11 : 3 ; /* Reserved */
+ UINT32 reply_timer_timeout : 1 ; /* Replay Timer Timeout Status */
+ UINT32 advisory_nonfatal_error : 1 ; /* Advisory Non-Fatal Error Status*/
+ UINT32 corrected_internal_error : 1 ; /*Corrected Internal Error Status*/
+ UINT32 reserved_15_31 : 1 ; /* Reserved */
+ }Bits;
+ UINT32 Value;
+}pcie_co_aer_status_u;
+
+typedef struct tagPcieAerStatus
+{
+ pcie_uc_aer_status_u uc_aer_status;
+ pcie_co_aer_status_u co_aer_status;
+}pcie_aer_status_s;
+
+
+
+typedef struct tagPcieLoopTestResult
+{
+ UINT32 tx_pkts_cnt;
+ UINT32 rx_pkts_cnt;
+ UINT32 error_pkts_cnt;
+ UINT32 droped_pkts_cnt;
+ UINT32 push_cnt;
+ pcie_device_status_u device_status;
+ pcie_aer_status_s pcie_aer_status;
+} pcie_loop_test_result_s;
+
+typedef struct tagPcieDmaChannelAttrs {
+ UINT32 dma_chan_en;
+ UINT32 dma_mode;
+ UINT32 channel_status;
+}pcie_dma_channel_attrs_s;
+
+typedef enum tagPcieDmaChannelStatus
+{
+ PCIE_DMA_CS_RESERVED = 0,
+ PCIE_DMA_CS_RUNNING = 1,
+ PCIE_DMA_CS_HALTED = 2,
+ PCIE_DMA_CS_STOPPED = 3
+}pcie_dma_channel_status_e;
+
+typedef enum tagPcieDmaIntType{
+ PCIE_DMA_INT_TYPE_DONE=0,
+ PCIE_DMA_INT_TYPE_ABORT,
+ PCIE_DMA_INT_ALL,
+ PCIE_DMA_INT_NONE
+}pcie_dma_int_type_e;
+
+typedef enum tagPcieMulWinSize
+{
+ WIN_SIZE_4K = 0xc,
+ WIN_SIZE_8K,
+ WIN_SIZE_16K,
+ WIN_SIZE_32K,
+ WIN_SIZE_64K,
+ WIN_SIZE_128K,
+ WIN_SIZE_256K,
+ WIN_SIZE_512K,
+ WIN_SIZE_1M,
+ WIN_SIZE_2M,
+ WIN_SIZE_4M,
+ WIN_SIZE_8M,
+ WIN_SIZE_16M,
+ WIN_SIZE_32M,
+ WIN_SIZE_64M,
+ WIN_SIZE_128M,
+ WIN_SIZE_256M,
+ WIN_SIZE_512M,
+ WIN_SIZE_1G,
+ WIN_SIZE_2G,
+ WIN_SIZE_4G,
+ WIN_SIZE_8G,
+ WIN_SIZE_16G,
+ WIN_SIZE_32G,
+ WIN_SIZE_64G,
+ WIN_SIZE_128G,
+ WIN_SIZE_256G,
+ WIN_SIZE_512G = 0x27,
+}pcie_mul_win_size_e;
+
+typedef struct tagPcieMultiCastCfg
+{
+ UINT64 multicast_base_addr;
+ pcie_mul_win_size_e base_addr_size;
+ UINT64 base_translate_addr;
+}pcie_multicast_cfg_s;
+
+typedef enum tagPcieMode
+{
+ PCIE_EP_DEVICE = 0x0,
+ LEGACY_PCIE_EP_DEVICE = 0x1,
+ RP_OF_PCIE_RC = 0x4,
+ PCIE_INVALID = 0x100
+}pcie_mode_e;
+
+typedef struct{
+ UINT32 PortIndex;
+ PCIE_PORT_INFO PortInfo;
+ UINT64 iep_bar01; /*iep bar 01*/
+ UINT64 iep_bar23;
+ UINT64 iep_bar45;
+ UINT64 iep_bar01_xlat;
+ UINT64 iep_bar23_xlat;
+ UINT64 iep_bar45_xlat;
+ UINT64 iep_bar_lmt23;
+ UINT64 iep_bar_lmt45; /*bar limit*/
+ UINT64 eep_bar01;
+ UINT64 eep_bar23;
+ UINT64 eep_bar45;
+ UINT64 eep_bar23_xlat;
+ UINT64 eep_bar45_xlat;
+ UINT64 eep_bar_lmt23; /*bar limit*/
+ UINT64 eep_bar_lmt45; /*bar limit*/
+} PCIE_NTB_CFG;
+
+extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info);
+
+extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl);
+
+extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed);
+
+extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+
+extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control);
+
+extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute);
+
+extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status);
+
+extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel);
+
+
+extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status);
+
+extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type);
+
+
+extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num);
+
+extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg);
+
+extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell);
+
+extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result);
+extern int pcie_port_reset(UINT32 Port);
+
+extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \
+pcie_device_status_u *pcie_stat);
+extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
+
+extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status);
+extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
+
+extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length);
+
+extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length);
+
+extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length);
+
+extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length);
+
+#endif
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf new file mode 100644 index 0000000000..9577d96b23 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf @@ -0,0 +1,56 @@ +## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Hi1610AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt/DsdtHi1610.asl
+ Facs.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ MadtHi1610.aslc
+ D03Mcfg.aslc
+ D03Iort.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+ Silicon/Hisilicon/HisiPkg.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl new file mode 100644 index 0000000000..9295485149 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -0,0 +1,368 @@ +/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+[0004] Signature : "IORT" [IO Remapping Table]
+[0004] Table Length : 000002e4
+[0001] Revision : 00
+[0001] Checksum : BC
+[0006] Oem ID : "HISI "
+[0008] Oem Table ID : "HIP06 "
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20151124
+
+[0004] Node Count : 00000008
+[0004] Node Offset : 00000034
+[0004] Reserved : 00000000
+[0004] Optional Padding : 00 00 00 00
+
+/* ITS 0, for dsa */
+[0001] Type : 00
+[0002] Length : 0018
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000
+[0004] Mapping Offset : 00000000
+
+[0004] ItsCount : 00000001
+[0004] Identifiers : 00000000
+
+/* mbi-gen dsa mbi0 - usb, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0017] Device Name : "\_SB_.MBI0"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00040080 // device id
+[0004] Output Reference : 00000034 // point to its dsa
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen dsa mbi1 - sas1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI1"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00040000
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen dsa mbi2 - sas2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI2"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00040040
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen dsa mbi3 - dsa0, srv named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI3"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00040800
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI4"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00040b1c
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI5"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00040b1d
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen dsa mbi6 - dsa sas0 named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI6"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00040900
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen mbi7 - RoCE named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI7"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00040b1e
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* RC 0 */
+[0001] Type : 02
+[0002] Length : 0034
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000020
+
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000001
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 01
+ Coherency : 1
+ Device Attribute : 0
+[0004] ATS Attribute : 00000000
+[0004] PCI Segment Number : 00000000
+
+[0004] Input base : 00000000
+[0004] ID Count : 00002000
+[0004] Output Base : 00000000
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* RC 1 */
+[0001] Type : 02
+[0002] Length : 0034
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000020
+
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000001
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 01
+ Coherency : 1
+ Device Attribute : 0
+[0004] ATS Attribute : 00000000
+[0004] PCI Segment Number : 00000001
+
+[0004] Input base : 0000e000
+[0004] ID Count : 00002000
+[0004] Output Base : 0000e000
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* RC 2 */
+[0001] Type : 02
+[0002] Length : 0034
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000020
+
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000001
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 01
+ Coherency : 1
+ Device Attribute : 0
+[0004] ATS Attribute : 00000000
+[0004] PCI Segment Number : 00000002
+
+[0004] Input base : 00008000
+[0004] ID Count : 00002000
+[0004] Output Base : 00008000
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc new file mode 100644 index 0000000000..7e5c8efa2f --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc @@ -0,0 +1,85 @@ +/*
+ * Copyright (c) 2016 Hisilicon Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ */
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1610Platform.h"
+
+#define ACPI_6_1_MCFG_VERSION 0x1
+
+#pragma pack(1)
+typedef struct
+{
+ UINT64 ullBaseAddress;
+ UINT16 usSegGroupNum;
+ UINT8 ucStartBusNum;
+ UINT8 ucEndBusNum;
+ UINT32 Reserved2;
+}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved1;
+}EFI_ACPI_6_1_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+ EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+ EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[3];
+}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+ {
+ {
+ EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+ ACPI_6_1_MCFG_VERSION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION
+ },
+ 0x0000000000000000, //Reserved
+ },
+ {
+
+ {
+ 0xb0000000, //Base Address
+ 0x0, //Segment Group Number
+ 0x0, //Start Bus Number
+ 0x1f, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ {
+ 0xb0000000, //Base Address
+ 0x1, //Segment Group Number
+ 0xe0, //Start Bus Number
+ 0xff, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ {
+ 0xa0000000, //Base Address
+ 0x2, //Segment Group Number
+ 0x80, //Start Bus Number
+ 0x9f, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000000..e995295747 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,88 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ //
+ // A57x16 Processor declaration
+ //
+ Device(CPU0) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ Device(CPU1) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ }
+ Device(CPU2) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ }
+ Device(CPU3) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ }
+ Device(CPU4) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 4)
+ }
+ Device(CPU5) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 5)
+ }
+ Device(CPU6) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 6)
+ }
+ Device(CPU7) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 7)
+ }
+ Device(CPU8) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 8)
+ }
+ Device(CPU9) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 9)
+ }
+ Device(CP10) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 10)
+ }
+ Device(CP11) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 11)
+ }
+ Device(CP12) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 12)
+ }
+ Device(CP13) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 13)
+ }
+ Device(CP14) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 14)
+ }
+ Device(CP15) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 15)
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000000..3bcc5fb964 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl @@ -0,0 +1,36 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ Device(COM0) {
+ Name(_HID, "HISI0031") //it is not 16550 compatible
+ Name(_CID, "8250dw")
+ Name(_UID, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x80300000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-frequency", 200000000},
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl new file mode 100644 index 0000000000..765ca19fb3 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -0,0 +1,691 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ Device (MDIO)
+ {
+ OperationRegion(CLKR, SystemMemory, 0x60000338, 8)
+ Field(CLKR, DWordAcc, NoLock, Preserve) {
+ CLKE, 1, // clock enable
+ , 31,
+ CLKD, 1, // clode disable
+ , 31,
+ }
+ OperationRegion(RSTR, SystemMemory, 0x60000A38, 8)
+ Field(RSTR, DWordAcc, NoLock, Preserve) {
+ RSTE, 1, // reset
+ , 31,
+ RSTD, 1, // de-reset
+ , 31,
+ }
+
+ Name(_HID, "HISI0141")
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)
+ })
+
+ Method(_RST, 0, Serialized) {
+ Store (0x1, RSTE)
+ Sleep (10)
+ Store (0x1, CLKD)
+ Sleep (10)
+ Store (0x1, RSTD)
+ Sleep (10)
+ Store (0x1, CLKE)
+ Sleep (10)
+ }
+ }
+
+ Device (DSF0)
+ {
+ OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+ OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
+ Field(H4SR, DWordAcc, NoLock, Preserve) {
+ H4ST, 1,
+ , 31, //RESERVED
+ }
+ // DSAF RESET
+ OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
+ Field(DRER, DWordAcc, NoLock, Preserve) {
+ DRTE, 1,
+ , 31, //RESERVED
+ DRTD, 1,
+ , 31, //RESERVED
+ }
+ // NT RESET
+ OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
+ Field(NRER, DWordAcc, NoLock, Preserve) {
+ NRTE, 1,
+ , 31, //RESERVED
+ NRTD, 1,
+ , 31, //RESERVED
+ }
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // RCB PPE COM RESET
+ OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
+ Field(RRTR, DWordAcc, NoLock, Preserve) {
+ RRTE, 1,
+ , 31, //RESERVED
+ RRTD, 1,
+ , 31, //RESERVED
+ }
+
+ // DSAF Channel RESET
+ OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8)
+ Field(DCRR, DWordAcc, NoLock, Preserve) {
+ DCRE, 1,
+ , 31, //RESERVED
+ DCRD, 1,
+ , 31, //RESERVED
+ }
+
+ // RoCE RESET
+ OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8)
+ Field(RKRR, DWordAcc, NoLock, Preserve) {
+ RKRE, 1,
+ , 31, //RESERVED
+ RKRD, 1,
+ , 31, //RESERVED
+ }
+
+ // RoCE Clock enable/disable
+ OperationRegion(RKCR, SystemMemory, 0xC0000328, 8)
+ Field(RKCR, DWordAcc, NoLock, Preserve) {
+ RCLE, 1,
+ , 31, //RESERVED
+ RCLD, 1,
+ , 31, //RESERVED
+ }
+
+ // Hilink access sel cfg reg
+ OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
+ Field(HSER, DWordAcc, NoLock, Preserve) {
+ HSEL, 2, // hilink_access_sel & hilink_access_wr_pul
+ , 30, // RESERVED
+ }
+
+ // Serdes
+ OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
+ Field(H4LR, DWordAcc, NoLock, Preserve) {
+ H4L0, 16, // port0
+ , 16, //RESERVED
+ Offset (0x400),
+ H4L1, 16, // port1
+ , 16, //RESERVED
+ Offset (0x800),
+ H4L2, 16, // port2
+ , 16, //RESERVED
+ Offset (0xc00),
+ H4L3, 16, // port3
+ , 16, //RESERVED
+ }
+ OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L2, 16, // port4
+ , 16, //RESERVED
+ Offset (0x400),
+ H3L3, 16, // port5
+ , 16, //RESERVED
+ }
+ Name (_HID, "HISI00B2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
+ Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+ {
+ 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+ 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+ {
+ 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+ 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+ 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+ 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+ 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+ 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+ 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+ 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+ 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+ 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+ 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+ 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+ {
+ 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+ 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+ 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+ 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+ 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+ 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+ 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+ 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+ 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+ 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+ 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+ 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "6port-16rss"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ Package () {"interrupt-parent", Package() {\_SB.MBI3}},
+ }
+ })
+
+ //reset XGE port
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XRST, 2, Serialized) {
+ ShiftLeft (0x2082082, Arg0, Local0)
+ Or (Local0, 0x1, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset XGE core
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XCRT, 2, Serialized) {
+ ShiftLeft (0x2080, Arg0, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset GE port
+ //Arg0 : GE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(GRST, 2, Serialized) {
+ If (LLessEqual (Arg0, 5)) {
+ //Service port
+ ShiftLeft (0x2082082, Arg0, Local0)
+ ShiftLeft (0x1, Arg0, Local1)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local1, GR1E)
+ Store(Local0, GR0E)
+ } Else {
+ Store(Local0, GR0D)
+ Store(Local1, GR1D)
+ }
+ }
+ }
+
+ //reset PPE port
+ //Arg0 : PPE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(PRST, 2, Serialized) {
+ ShiftLeft (0x1, Arg0, Local0)
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, PRTE)
+ } Else {
+ Store(Local0, PRTD)
+ }
+ }
+
+ //reset DSAF channels
+ //Arg0 : mask
+ //Arg1 : 0 reset, 1 de-reset
+ Method(DCRT, 2, Serialized) {
+ If (LEqual (Arg1, 0)) {
+ Store(Arg0, DCRE)
+ } Else {
+ Store(Arg0, DCRD)
+ }
+ }
+
+ //reset RoCE
+ //Arg0 : 0 reset, 1 de-reset
+ Method(RRST, 1, Serialized) {
+ If (LEqual (Arg0, 0)) {
+ Store(0x1, RKRE)
+ } Else {
+ Store(0x1, RCLD)
+ Store(0x1, RKRD)
+ sleep(20)
+ Store(0x1, RCLE)
+ }
+ }
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 2, Serialized) {
+ ShiftLeft (Arg1, 10, Local0)
+ Switch (ToInteger(Arg0))
+ {
+ case (0x0){
+ Store (0, HSEL)
+ Store (H4L0, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L0)
+ }
+ case (0x1){
+ Store (0, HSEL)
+ Store (H4L1, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L1)
+ }
+ case (0x2){
+ Store (0, HSEL)
+ Store (H4L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L2)
+ }
+ case (0x3){
+ Store (0, HSEL)
+ Store (H4L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L3)
+ }
+ case (0x4){
+ Store (3, HSEL)
+ Store (H3L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H3L2)
+ }
+ case (0x5){
+ Store (3, HSEL)
+ Store (H3L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H3L3)
+ }
+ }
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce)
+ //Arg1 : port
+ //Arg2 : 0 disable, 1 enable
+ Method(DRST, 3, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ Store (Arg2, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Store (0x1, DRTE)
+ Store (0x1, NRTE)
+ Sleep (10)
+ Store (0x1, RRTE)
+ }
+ Else
+ {
+ Store (0x1, DRTD)
+ Store (0x1, NRTD)
+ Sleep (10)
+ Store (0x1, RRTD)
+ }
+ }
+ //Reset PPE port
+ case (0x2)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ PRST (Local0, Local1)
+ }
+
+ //Reset XGE core
+ case (0x3)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XCRT (Local0, Local1)
+ }
+ //Reset XGE port
+ case (0x4)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XRST (Local0, Local1)
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ GRST (Local0, Local1)
+ }
+
+ //Reset DSAF Channels
+ case (0x6)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ DCRT (Local0, Local1)
+ }
+
+ //Reset RoCE
+ case (0x7)
+ {
+ // Discarding Arg1 as it is always 0
+ Store (Arg2, Local0)
+ RRST (Local0)
+ }
+ }
+ }
+
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset Sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce)
+ // Arg3[1] : port index in dsaf
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : port
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : port
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : port index in dsaf
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : port index in dsaf
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local1, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ SRLP (Local0, Local1)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (0, Local1)
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ If (LLessEqual (Local0, 3))
+ {
+ // mac0: Hilink4 Lane0
+ // mac1: Hilink4 Lane1
+ // mac2: Hilink4 Lane2
+ // mac3: Hilink4 Lane3
+ Store (H4ST, Local1)
+ }
+ ElseIf (LLessEqual (Local0, 5))
+ {
+ // mac4: Hilink3 Lane2
+ // mac5: Hilink3 Lane3
+ Store (H3ST, Local1)
+ }
+
+ Return (Local1)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+ Device (PRT0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+ Device (PRT1)
+ {
+ Name (_ADR, 0x1)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 1},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+ Device (PRT4)
+ {
+ Name (_ADR, 0x4)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 4},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 0},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ Package () {"media-type", "copper"},
+ }
+ })
+ }
+ Device (PRT5)
+ {
+ Name (_ADR, 0x5)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 5},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 1},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ Package () {"media-type", "copper"},
+ }
+ })
+ }
+ }
+ Device (ETH4) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 4},
+ }
+ })
+ }
+ Device (ETH5) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 5},
+ }
+ })
+ }
+ Device (ETH0) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 0},
+ }
+ })
+ }
+ Device (ETH1) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 1},
+ }
+ })
+ }
+ Device (ROCE) {
+ Name(_HID, "HISI00D1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}},
+ Package () {"dsaf-handle", Package (){\_SB.DSF0}},
+ Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes
+ Package () {"interrupt-names", Package() {"hns-roce-comp-0",
+ "hns-roce-comp-1",
+ "hns-roce-comp-2",
+ "hns-roce-comp-3",
+ "hns-roce-comp-4",
+ "hns-roce-comp-5",
+ "hns-roce-comp-6",
+ "hns-roce-comp-7",
+ "hns-roce-comp-8",
+ "hns-roce-comp-9",
+ "hns-roce-comp-10",
+ "hns-roce-comp-11",
+ "hns-roce-comp-12",
+ "hns-roce-comp-13",
+ "hns-roce-comp-14",
+ "hns-roce-comp-15",
+ "hns-roce-comp-16",
+ "hns-roce-comp-17",
+ "hns-roce-comp-18",
+ "hns-roce-comp-19",
+ "hns-roce-comp-20",
+ "hns-roce-comp-21",
+ "hns-roce-comp-22",
+ "hns-roce-comp-23",
+ "hns-roce-comp-24",
+ "hns-roce-comp-25",
+ "hns-roce-comp-26",
+ "hns-roce-comp-27",
+ "hns-roce-comp-28",
+ "hns-roce-comp-29",
+ "hns-roce-comp-30",
+ "hns-roce-comp-31",
+ "hns-roce-async",
+ "hns-roce-common"}},
+ }
+ })
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000)
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI7")
+ {
+ 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+ 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+ 746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+ }
+ })
+ Name (_PRS, ResourceTemplate (){
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+ 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+ 746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl new file mode 100644 index 0000000000..46b8db0f70 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -0,0 +1,305 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ // Mbi-gen pcie subsys
+ Device(MBI0) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {640, 641} //OHCI: 640, EHCI 641
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 2}
+ }
+ })
+ }
+
+ // Mbi-gen sas1 intc
+ Device(MBI1) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 64,65,66,67,68,
+ 69,70,71,72,73,
+ 74,75,76,77,78,
+ 79,80,81,82,83,
+ 84,85,86,87,88,
+ 89,90,91,92,93,
+ 94,95,96,97,98,
+ 99,100,101,102,103,
+ 104,105,106,107,108,
+ 109,110,111,112,113,
+ 114,115,116,117,118,
+ 119,120,121,122,123,
+ 124,125,126,127,128,
+ 129,130,131,132,133,
+ 134,135,136,137,138,
+ 139,140,141,142,143,
+ 144,145,146,147,148,
+ 149,150,151,152,153,
+ 154,155,156,157,158,
+ 159,
+ }
+
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 576,577,578,579,580,
+ 581,582,583,584,585,
+ 586,587,588,589,590,
+ 591,592,593,594,595,
+ 596,597,598,599,600,
+ 601,602,603,604,605,
+ 606,607,
+ }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 128}
+ }
+ })
+ }
+
+ Device(MBI2) { // Mbi-gen sas2 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 192,193,194,195,196,
+ 197,198,199,200,201,
+ 202,203,204,205,206,
+ 207,208,209,210,211,
+ 212,213,214,215,216,
+ 217,218,219,220,221,
+ 222,223,224,225,226,
+ 227,228,229,230,231,
+ 232,233,234,235,236,
+ 237,238,239,240,241,
+ 242,243,244,245,246,
+ 247,248,249,250,251,
+ 252,253,254,255,256,
+ 257,258,259,260,261,
+ 262,263,264,265,266,
+ 267,268,269,270,271,
+ 272,273,274,275,276,
+ 277,278,279,280,281,
+ 282,283,284,285,286,
+ 287,
+ }
+
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 608,609,610,611,
+ 612,613,614,615,616,
+ 617,618,619,620,621,
+ 622,623,624,625,626,
+ 627,628,629,630,631,
+ 632,633,634,635,636,
+ 637,638,639,
+ }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 128}
+ }
+ })
+ }
+
+ Device(MBI3) { // Mbi-gen dsa0 srv intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+
+Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+ 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+ }
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+ 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+ 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+ 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+ 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+ 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+ 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+ 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+ 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+ 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+ 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+ 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+ }
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+ 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+ 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+ 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+ 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+ 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+ 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+ 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+ 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+ 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+ 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+ 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+ }
+})
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 409}
+ }
+ })
+ }
+/*
+ Device(MBI4) { // Mbi-gen dsa1 dbg0 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 9}
+ }
+ })
+ }
+
+ Device(MBI5) { // Mbi-gen dsa2 dbg1 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 9}
+ }
+ })
+ }
+*/
+ Device(MBI6) { // Mbi-gen dsa sas0 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 64,65,66,67,68,
+ 69,70,71,72,73,
+ 74,75,76,77,78,
+ 79,80,81,82,83,
+ 84,85,86,87,88,
+ 89,90,91,92,93,
+ 94,95,96,97,98,
+ 99,100,101,102,103,
+ 104,105,106,107,108,
+ 109,110,111,112,113,
+ 114,115,116,117,118,
+ 119,120,121,122,123,
+ 124,125,126,127,128,
+ 129,130,131,132,133,
+ 134,135,136,137,138,
+ 139,140,141,142,143,
+ 144,145,146,147,148,
+ 149,150,151,152,153,
+ 154,155,156,157,158,
+ 159,
+ }
+
+ Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 601,602,603,604,
+ 605,606,607,608,609,
+ 610,611,612,613,614,
+ 615,616,617,618,619,
+ 620,621,622,623,624,
+ 625,626,627,628,629,
+ 630,631,632,
+ }
+ })
+
+
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 128}
+ }
+ })
+ }
+ Device(MBI7) { // Mbi-gen roce intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+ Name (_PRS, ResourceTemplate (){
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+ 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+ 746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+ }
+ })
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 34}
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl new file mode 100644 index 0000000000..5b0134552c --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl @@ -0,0 +1,280 @@ +/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//#include "ArmPlatform.h"
+/*
+ See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
+*/
+#define PCI_OSC_SUPPORT() \
+ Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
+ Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
+ Method(_OSC,4) { \
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
+ /* Create DWord-adressable fields from the Capabilities Buffer */ \
+ CreateDWordField(Arg3,0,CDW1) \
+ CreateDWordField(Arg3,4,CDW2) \
+ CreateDWordField(Arg3,8,CDW3) \
+ /* Save Capabilities DWord2 & 3 */ \
+ Store(CDW2,SUPP) \
+ Store(CDW3,CTRL) \
+ /* Only allow native hot plug control if OS supports: */ \
+ /* ASPM */ \
+ /* Clock PM */ \
+ /* MSI/MSI-X */ \
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) { \
+ And(CTRL,0x1E,CTRL) \
+ }\
+ \
+ /* Do not allow native PME, AER */ \
+ /* Never allow SHPC (no SHPC controller in this system)*/ \
+ And(CTRL,0x10,CTRL) \
+ If(LNotEqual(Arg1,One)) { /* Unknown revision */ \
+ Or(CDW1,0x08,CDW1) \
+ } \
+ \
+ If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \
+ Or(CDW1,0x10,CDW1) \
+ } \
+ \
+ /* Update DWORD3 in the buffer */ \
+ Store(CTRL,CDW3) \
+ Return(Arg3) \
+ } Else { \
+ Or(CDW1,4,CDW1) /* Unrecognized UUID */ \
+ Return(Arg3) \
+ } \
+ } // End _OSC
+
+Scope(_SB)
+{
+ // PCIe Root bus
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x0, // AddressMinimum - Minimum Bus Number
+ 0x1f, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x20 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xb2000000, // Min Base Address pci address
+ 0xb7feffff, // Max Base Address
+ 0x0, // Translate
+ 0x5ff0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0xb7ff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ PCI_OSC_SUPPORT()
+
+ Device (RES0)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)
+ })
+ }
+
+ } // Device(PCI0)
+
+ Device (RES0)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0x0) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)
+ })
+ }
+
+ // PCIe Root bus
+ Device (PCI1)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 1) // Segment of this Root complex
+ Name(_BBN, 0xe0) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0xe0, // AddressMinimum - Minimum Bus Number
+ 0xff, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x20 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xb8000000, // Min Base Address pci address
+ 0xbdfeffff, // Max Base Address
+ 0x0, // Translate
+ 0x5ff0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0xbdff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ PCI_OSC_SUPPORT()
+
+ Device (RES1)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0x1) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)
+ })
+ }
+
+
+ } // Device(PCI1)
+
+ Device (RES1)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)
+ })
+ }
+
+ // PCIe Root bus
+ Device (PCI2)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 2) // Segment of this Root complex
+ Name(_BBN, 0x80) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x80, // AddressMinimum - Minimum Bus Number
+ 0x9f, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x20 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xaa000000, // Min Base Address
+ 0xaffeffff, // Max Base Address
+ 0x0, // Translate
+ 0x5ff0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0xafff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ PCI_OSC_SUPPORT()
+
+ Device (RES2)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)
+ })
+ }
+
+ } // Device(PCI2)
+
+ Device (RES2)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0x2) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)
+ })
+ }
+
+ Device (RESP) //reserve for ecam resource
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xb0000000, 0x2000000) //ECAM space for PCI0 [bus 00-1f]
+ Memory32Fixed (ReadWrite, 0xbe000000, 0x2000000) //ECAM space for PCI1 [bus e0-ff]
+ Memory32Fixed (ReadWrite, 0xa8000000, 0x2000000) //ECAM space for PCI2 [bus 80-9f]
+ })
+ }
+}
+
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl new file mode 100644 index 0000000000..7b5d4ded70 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -0,0 +1,367 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ Device(SAS0) {
+ Name(_HID, "HISI0162")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6")
+ {
+ 64,65,66,67,68,
+ 69,70,71,72,73,
+ 74,75,76,77,78,
+ 79,80,81,82,83,
+ 84,85,86,87,88,
+ 89,90,91,92,93,
+ 94,95,96,97,98,
+ 99,100,101,102,103,
+ 104,105,106,107,108,
+ 109,110,111,112,113,
+ 114,115,116,117,118,
+ 119,120,121,122,123,
+ 124,125,126,127,128,
+ 129,130,131,132,133,
+ 134,135,136,137,138,
+ 139,140,141,142,143,
+ 144,145,146,147,148,
+ 149,150,151,152,153,
+ 154,155,156,157,158,
+ 159,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI6" )
+ {
+ 601,602,603,604,
+ 605,606,607,608,609,
+ 610,611,612,613,614,
+ 615,616,617,618,619,
+ 620,621,622,623,624,
+ 625,626,627,628,629,
+ 630,631,632,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI6}},
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},
+ Package () {"queue-count", 16},
+ Package () {"phy-count", 8},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x338),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xa60),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a30),
+ STS, 32,
+ }
+
+ OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000)
+ Field (PHYS, DWordAcc, NoLock, Preserve) {
+ Offset (0x0014),
+ PHY0, 32,
+ Offset (0x0414),
+ PHY1, 32,
+ Offset (0x0814),
+ PHY2, 32,
+ Offset (0x0c14),
+ PHY3, 32,
+ Offset (0x1014),
+ PHY4, 32,
+ Offset (0x1414),
+ PHY5, 32,
+ Offset (0x1814),
+ PHY6, 32,
+ Offset (0x1c14),
+ PHY7, 32,
+ }
+
+ OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+ Field (SYSR, DWordAcc, NoLock, Preserve) {
+ Offset (0xe014),
+ DIE4, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ Store(DIE4, local0)
+ If (LEqual (local0, 0)) {
+ /* 66MHZ */
+ Store(0x0199B694, Local1)
+ Store(Local1, PHY0)
+ Store(Local1, PHY1)
+ Store(Local1, PHY2)
+ Store(Local1, PHY3)
+ Store(Local1, PHY4)
+ Store(Local1, PHY5)
+ Store(Local1, PHY6)
+ Store(Local1, PHY7)
+ }
+ }
+ }
+
+ Device(SAS1) {
+ Name(_HID, "HISI0162")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+ {
+ 64,65,66,67,68,
+ 69,70,71,72,73,
+ 74,75,76,77,78,
+ 79,80,81,82,83,
+ 84,85,86,87,88,
+ 89,90,91,92,93,
+ 94,95,96,97,98,
+ 99,100,101,102,103,
+ 104,105,106,107,108,
+ 109,110,111,112,113,
+ 114,115,116,117,118,
+ 119,120,121,122,123,
+ 124,125,126,127,128,
+ 129,130,131,132,133,
+ 134,135,136,137,138,
+ 139,140,141,142,143,
+ 144,145,146,147,148,
+ 149,150,151,152,153,
+ 154,155,156,157,158,
+ 159,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+ {
+ 576,577,578,579,580,
+ 581,582,583,584,585,
+ 586,587,588,589,590,
+ 591,592,593,594,595,
+ 596,597,598,599,600,
+ 601,602,603,604,605,
+ 606,607,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI1}},
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+ Package () {"queue-count", 16},
+ Package () {"phy-count", 8},
+ Package () {"hip06-sas-v2-quirk-amt", 1},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x318),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xa18),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a0c),
+ STS, 32,
+ }
+
+ OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000)
+ Field (PHYS, DWordAcc, NoLock, Preserve) {
+ Offset (0x0014),
+ PHY0, 32,
+ Offset (0x0414),
+ PHY1, 32,
+ Offset (0x0814),
+ PHY2, 32,
+ Offset (0x0c14),
+ PHY3, 32,
+ Offset (0x1014),
+ PHY4, 32,
+ Offset (0x1414),
+ PHY5, 32,
+ Offset (0x1814),
+ PHY6, 32,
+ Offset (0x1c14),
+ PHY7, 32,
+ }
+
+ OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+ Field (SYSR, DWordAcc, NoLock, Preserve) {
+ Offset (0xe014),
+ DIE4, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ Store(DIE4, local0)
+ If (LEqual (local0, 0)) {
+ /* 66MHZ */
+ Store(0x0199B694, Local1)
+ Store(Local1, PHY0)
+ Store(Local1, PHY1)
+ Store(Local1, PHY2)
+ Store(Local1, PHY3)
+ Store(Local1, PHY4)
+ Store(Local1, PHY5)
+ Store(Local1, PHY6)
+ Store(Local1, PHY7)
+ }
+ }
+ }
+
+ Device(SAS2) {
+ Name(_HID, "HISI0162")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+ {
+ 192,193,194,195,196,
+ 197,198,199,200,201,
+ 202,203,204,205,206,
+ 207,208,209,210,211,
+ 212,213,214,215,216,
+ 217,218,219,220,221,
+ 222,223,224,225,226,
+ 227,228,229,230,231,
+ 232,233,234,235,236,
+ 237,238,239,240,241,
+ 242,243,244,245,246,
+ 247,248,249,250,251,
+ 252,253,254,255,256,
+ 257,258,259,260,261,
+ 262,263,264,265,266,
+ 267,268,269,270,271,
+ 272,273,274,275,276,
+ 277,278,279,280,281,
+ 282,283,284,285,286,
+ 287,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+ {
+ 608,609,610,611,
+ 612,613,614,615,616,
+ 617,618,619,620,621,
+ 622,623,624,625,626,
+ 627,628,629,630,631,
+ 632,633,634,635,636,
+ 637,638,639,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI2}},
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+ Package () {"queue-count", 16},
+ Package () {"phy-count", 9},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x3a8),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xae0),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a70),
+ STS, 32,
+ }
+
+ OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400)
+ Field (PHYS, DWordAcc, NoLock, Preserve) {
+ Offset (0x0014),
+ PHY0, 32,
+ Offset (0x0414),
+ PHY1, 32,
+ Offset (0x0814),
+ PHY2, 32,
+ Offset (0x0c14),
+ PHY3, 32,
+ Offset (0x1014),
+ PHY4, 32,
+ Offset (0x1414),
+ PHY5, 32,
+ Offset (0x1814),
+ PHY6, 32,
+ Offset (0x1c14),
+ PHY7, 32,
+ offset (0x2014),
+ PHY8, 32,
+ }
+
+ OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+ Field (SYSR, DWordAcc, NoLock, Preserve) {
+ Offset (0xe014),
+ DIE4, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ Store(DIE4, local0)
+ If (LEqual (local0, 0)) {
+ /* 66MHZ */
+ Store(0x0199B694, Local1)
+ Store(Local1, PHY0)
+ Store(Local1, PHY1)
+ Store(Local1, PHY2)
+ Store(Local1, PHY3)
+ Store(Local1, PHY4)
+ Store(Local1, PHY5)
+ Store(Local1, PHY6)
+ Store(Local1, PHY7)
+ Store(Local1, PHY8)
+ }
+ }
+ }
+
+}
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl new file mode 100644 index 0000000000..9132965ef7 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -0,0 +1,136 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+ Device (USB0)
+ {
+ Name (_HID, "PNP0D20") // _HID: Hardware ID
+ Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xa7020000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0")
+ {
+ 641, //EHCI
+ }
+ })
+ Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
+ }
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"interrupt-parent",Package() {\_SB.MBI0}}
+ }
+ })
+
+ Device (RHUB)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Device (PRT1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ 0xFF,
+ Zero,
+ Zero,
+ Zero
+ })
+ Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
+ {
+ ToPLD (
+ PLD_Revision = 0x1,
+ PLD_IgnoreColor = 0x1,
+ PLD_Red = 0x0,
+ PLD_Green = 0x0,
+ PLD_Blue = 0x0,
+ PLD_Width = 0x0,
+ PLD_Height = 0x0,
+ PLD_UserVisible = 0x1,
+ PLD_Dock = 0x0,
+ PLD_Lid = 0x0,
+ PLD_Panel = "UNKNOWN",
+ PLD_VerticalPosition = "UPPER",
+ PLD_HorizontalPosition = "LEFT",
+ PLD_Shape = "UNKNOWN",
+ PLD_GroupOrientation = 0x0,
+ PLD_GroupToken = 0x0,
+ PLD_GroupPosition = 0x0,
+ PLD_Bay = 0x0,
+ PLD_Ejectable = 0x0,
+ PLD_EjectRequired = 0x0,
+ PLD_CabinetNumber = 0x0,
+ PLD_CardCageNumber = 0x0,
+ PLD_Reference = 0x0,
+ PLD_Rotation = 0x0,
+ PLD_Order = 0x0,
+ PLD_VerticalOffset = 0x0,
+ PLD_HorizontalOffset = 0x0)
+
+ })
+ }
+
+ Device (PRT2)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+
+ Device (PRT3)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+
+ Device (PRT4)
+ {
+ Name (_ADR, 0x04) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+ }
+ }
+}
+
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl new file mode 100644 index 0000000000..4185f8017b --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -0,0 +1,29 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Hi1610Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP06 ", EFI_ACPI_ARM_OEM_REVISION) {
+ include ("Lpc.asl")
+ include ("D03Mbig.asl")
+ include ("CPU.asl")
+ include ("D03Usb.asl")
+ include ("D03Hns.asl")
+ include ("D03Sas.asl")
+ include ("D03Pci.asl")
+}
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl new file mode 100644 index 0000000000..d4b2372578 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl @@ -0,0 +1,104 @@ +/** @file
+*
+* Copyright (c) 2016 Hisilicon Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// LPC
+//
+
+Scope(_SB) {
+ Device (LPC0) {
+ Name (_HID, "HISI0191") // HiSi LPC
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
+ })
+ }
+
+ Device (LPC0.IPMI) {
+ Name (_HID, "IPI0001")
+ Method (_IFT) {
+ Return (0x03)
+ }
+ Name (LORS, ResourceTemplate() {
+ QWordIO (
+ ResourceConsumer,
+ MinNotFixed, // _MIF
+ MaxNotFixed, // _MAF
+ PosDecode,
+ EntireRange,
+ 0x0, // _GRA
+ 0xe4, // _MIN
+ 0x3fff, // _MAX
+ 0x0, // _TRA
+ 0x04, // _LEN
+ , ,
+ BTIO
+ )
+ })
+ CreateQWordField (LORS, BTIO._MIN, CMIN)
+ CreateQWordField (LORS, BTIO._MAX, CMAX)
+ CreateQWordField (LORS, BTIO._LEN, CLEN)
+
+ Method (_PRS, 0) {
+ Return (LORS)
+ }
+
+ Method (_CRS, 0) {
+ Return (LORS)
+ }
+ Method (_SRS, 1) {
+ CreateQWordField (Arg0, \_SB.LPC0.IPMI.BTIO._MIN, IMIN)
+ Store (IMIN, CMIN)
+ CreateQWordField (Arg0, \_SB.LPC0.IPMI.BTIO._MAX, IMAX)
+ Store (IMAX, CMAX)
+ }
+ }
+
+ Device (LPC0.CON0) {
+ Name (_HID, "HISI1031")
+ Name (_CID, "PNP0501")
+ Name (LORS, ResourceTemplate() {
+ QWordIO (
+ ResourceConsumer,
+ MinNotFixed, // _MIF
+ MaxNotFixed, // _MAF
+ PosDecode,
+ EntireRange,
+ 0x0, // _GRA
+ 0x2F8, // _MIN
+ 0x3fff, // _MAX
+ 0x0, // _TRA
+ 0x08, // _LEN
+ , ,
+ IO02
+ )
+ })
+ CreateQWordField (LORS, IO02._MIN, CMIN)
+ CreateQWordField (LORS, IO02._MAX, CMAX)
+ CreateQWordField (LORS, IO02._LEN, CLEN)
+
+ Method (_PRS, 0) {
+ Return (LORS)
+ }
+
+ Method (_CRS, 0) {
+ Return (LORS)
+ }
+ Method (_SRS, 1) {
+ CreateQWordField (Arg0, \_SB.LPC0.CON0.IO02._MIN, IMIN)
+ Store (IMIN, CMIN)
+ CreateQWordField (Arg0, \_SB.LPC0.CON0.IO02._MAX, IMAX)
+ Store (IMAX, CMAX)
+ }
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc new file mode 100644 index 0000000000..d5bc299cea --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc @@ -0,0 +1,67 @@ +/** @file
+* Firmware ACPI Control Structure (FACS)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+ EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
+ sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
+ 0xA152, // UINT32 HardwareSignature
+ 0, // UINT32 FirmwareWakingVector
+ 0, // UINT32 GlobalLock
+ 0, // UINT32 Flags
+ 0, // UINT64 XFirmwareWakingVector
+ EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
+ { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]
+ EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]
+ 0, // UINT32 OspmFlags "Platform firmware must
+ // initialize this field to zero."
+ { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]
+ EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Facs;
+
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc new file mode 100644 index 0000000000..025b42cadd --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc @@ -0,0 +1,92 @@ +/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1610Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+ 0 // UINT64 Hypervisor Vendor Identify
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc new file mode 100644 index 0000000000..4c1050ae83 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -0,0 +1,96 @@ +/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1610Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT];
+} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+ {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES,
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+#ifdef notyet
+ PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
+ sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+ },
+ {
+ EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+ //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
+ 0, 0, 0, 0),
+ EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+ //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
+ 0, 0, 0, 0)
+ }
+#else /* !notyet */
+ 0, 0
+ }
+#endif
+ };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
+
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h new file mode 100644 index 0000000000..5a95b02055 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h @@ -0,0 +1,48 @@ +/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#ifndef _HI1610_PLATFORM_H_
+#define _HI1610_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION 0x00000000
+#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#define HI1610_WATCHDOG_COUNT 2
+
+#endif
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc new file mode 100644 index 0000000000..f302dd6f5c --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc @@ -0,0 +1,128 @@ +/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1610Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiNextLib.h>
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+// 0x20000 is only for socket 0
+#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId))
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16];
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1];
+} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+ // GsivId, GicRBase, Mpidr)
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+ // ACPI v5.1).
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0),
+ },
+
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4),
+ {
+ EFI_ACPI_6_1_GIC_ITS_INIT(0,0xC6000000),
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc new file mode 100644 index 0000000000..8b7aee4d9d --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc @@ -0,0 +1,81 @@ +/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1610Platform.h"
+
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+
+typedef struct {
+ EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header;
+ EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+
+} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE;
+#pragma pack()
+
+//
+// System Locality Information Table
+// Please modify all values in Slit.h only.
+//
+EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
+ {
+ {
+ EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE),
+ EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION,
+ },
+ //
+ // Beginning of SLIT specific fields
+ //
+ EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
+ },
+ {
+ {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality 0
+ {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality 1
+ {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality 2
+ {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality 3
+ {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality 4
+ {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality 5
+ {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality 6
+ {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality 7
+ {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality 8
+ {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality 9
+ {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality 10
+ {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality 11
+ {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality 12
+ {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality 13
+ {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality 14
+ {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality 15
+ {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality 16
+ {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality 17
+ {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality 18
+ {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality 19
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Slit;
+
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc new file mode 100644 index 0000000000..99df1a4d94 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc @@ -0,0 +1,115 @@ +/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+ *
+ * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1610Platform.h"
+#include <Library/AcpiLib.h>
+#include <Library/AcpiNextLib.h>
+
+
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT 4
+#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 4
+
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE Apic;
+ EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE Memory[2];
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE GICC[16];
+} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE;
+
+#pragma pack()
+
+
+//
+// Static Resource Affinity Table definition
+//
+EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = {
+ {
+ {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE),
+ EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION},
+ /*Reserved*/
+ 0x00000001, // Reserved to be 1 for backward compatibility
+ EFI_ACPI_RESERVED_QWORD
+ },
+ /**/
+ {
+ 0x00, // Subtable Type:Processor Local APIC/SAPIC Affinity
+ sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE), //Length
+ 0x00, //Proximity Domain Low(8)
+ 0x00, //Apic ID
+ 0x00000001, //Flags
+ 0x00, //Local Sapic EID
+ {0,0,0}, //Proximity Domain High(24)
+ 0x00000000, //ClockDomain
+ },
+ //
+ //
+ // Memory Affinity
+ //
+ {
+ EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001),
+ EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001),
+ },
+
+ /*Processor Local x2APIC Affinity*/
+ //{
+ // 0x02, // Subtable Type:Processor Local x2APIC Affinity
+ // sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE),
+ // {0,0}, //Reserved1
+ // 0x00000000, //Proximity Domain
+ // 0x00000000, //Apic ID
+ // 0x00000001, //Flags
+ // 0x00000000, //Clock Domain
+ // {0,0,0,0}, //Reserved2
+ //},
+
+ {
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000) //GICC Affinity Processor 15
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Srat;
+
diff --git a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h new file mode 100755 index 0000000000..077dd5edc8 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -0,0 +1,131 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_
+
+typedef enum {
+ EmHilink0Hccs1X8 = 0,
+ EmHilink0Pcie1X8 = 2,
+ EmHilink0Pcie1X4Pcie2X4 = 3,
+ EmHilink0Sas2X8 = 4,
+ EmHilink0Hccs1X8Width16,
+ EmHilink0Hccs1X8Width32,
+} HILINK0_MODE_TYPE;
+
+typedef enum {
+ EmHilink1Sas2X1 = 0,
+ EmHilink1Hccs0X8 = 1,
+ EmHilink1Pcie0X8 = 2,
+ EmHilink1Hccs0X8Width16,
+ EmHilink1Hccs0X8Width32,
+} HILINK1_MODE_TYPE;
+
+typedef enum {
+ EmHilink2Pcie2X8 = 0,
+ EmHilink2Sas0X8 = 2,
+} HILINK2_MODE_TYPE;
+
+typedef enum {
+ EmHilink5Pcie3X4 = 0,
+ EmHilink5Pcie2X2Pcie3X2 = 1,
+ EmHilink5Sas1X4 = 2,
+} HILINK5_MODE_TYPE;
+
+typedef enum {
+ Em32coreEvbBoard = 0,
+ Em16coreEvbBoard = 1,
+ EmV2R1CO5Borad = 2,
+ EmOtherBorad
+} BOARD_TYPE;
+
+
+typedef struct {
+ HILINK0_MODE_TYPE Hilink0Mode;
+ HILINK1_MODE_TYPE Hilink1Mode;
+ HILINK2_MODE_TYPE Hilink2Mode;
+ UINT32 Hilink3Mode;
+ UINT32 Hilink4Mode;
+ HILINK5_MODE_TYPE Hilink5Mode;
+ UINT32 Hilink6Mode;
+ UINT32 UseSsc;
+} SERDES_PARAM;
+
+
+#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF
+#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF
+#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF
+
+typedef struct {
+ UINT32 MacroId;
+ UINT32 DsNum;
+ UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
+extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
+extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
+UINT32 GetEthType(UINT8 EthChannel);
+
+EFI_STATUS
+EfiSerdesInitWrap (VOID);
+
+void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg);
+
+//EYE test
+UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData);
+
+UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum);
+
+//PRBS test
+int serdes_prbs_test(UINT8 macro, UINT8 lane, UINT8 prbstype);
+
+int serdes_prbs_test_cancle(UINT8 macro,UINT8 lane);
+
+//CTLE/DFE
+void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane);
+
+void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane);
+
+void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane);
+
+void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane);
+
+void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane);
+//int serdes_reset(UINT32 macro);
+//int serdes_release_reset(UINT32 macro);
+void Custom_Wave(UINT32 macro,UINT32 lane,UINT32 mode);
+void serdes_ffe_show(UINT32 macro,UINT32 lane);
+void serdes_dfe_show(UINT32 macro,UINT32 lane);
+int serdes_read_bert(UINT8 macro, UINT8 lane);
+void serdes_clean_bert(UINT8 macro, UINT8 lane);
+int serdes_get_four_point_eye_diagram(UINT32 macro, UINT32 lane,UINT32 eyemode, UINT32 data_rate);
+void serdes_release_mcu(UINT32 macro,UINT32 val);
+int hilink_write(UINT32 macro, UINT32 reg, UINT32 value);
+int hilink_read(UINT32 macro, UINT32 reg, UINT32 *value);
+int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);//TXRXPARLPBKEN
+int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+void serdes_ctle_show(UINT32 macro,UINT32 lane);
+int serdes_cs_write(UINT32 macro,UINT32 cs_num,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value);
+UINT32 serdes_cs_read(UINT32 macro,UINT32 cs_num,UINT32 reg_num);
+int serdes_ds_write(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value);
+int serdes_ds_read(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num);
+int report_serdes_mux(void);
+int serdes_key_reg_show(UINT32 macro);
+void serdes_state_show(UINT32 macro);
+UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum);
+
+#endif
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