diff options
| author | Ming Huang <huangming23@huawei.com> | 2017-06-29 17:27:46 +0800 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-10-05 13:53:16 +0100 |
| commit | a8aef961723b43cf7373d6e522fe47d13486ccf3 (patch) | |
| tree | bbfc2bef2c11d2a12428e30f0afb9dab6e7dc6ec /Silicon/Hisilicon | |
| parent | c2904471fdba7b56ef61ef5d04d2fcedb0d444c1 (diff) | |
| download | edk2-platforms-a8aef961723b43cf7373d6e522fe47d13486ccf3.tar.xz | |
D05/ACPI: Disable D05 SAS0 and SAS2
There is no interface from SAS0 or SAS2 controller on D05,
so SAS0 and SAS2 can't be used.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Hisilicon')
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl index 93beb952c9..6455130d1d 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -88,6 +88,11 @@ Scope(_SB) Store(0x7ffff, CLK)
Sleep(1)
}
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0)
+ }
}
Device(SAS1) {
@@ -239,6 +244,11 @@ Scope(_SB) Store(0x7ffff, CLK)
Sleep(1)
}
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0)
+ }
}
}
|