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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-01-25 12:08:56 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-01-25 18:01:03 +0000 |
| commit | c76bf98bc8f988ea2f3953563f94fab8268ec3bd (patch) | |
| tree | f447b43d63de6d653b74239d56a4aa4d151fbf62 /Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | |
| parent | 43467f4ee926acdadc1c6481a3d3407044ccc56d (diff) | |
| download | edk2-platforms-c76bf98bc8f988ea2f3953563f94fab8268ec3bd.tar.xz | |
Silicon/Socionext/SynQuacer: implement menu option to set max PCIe speed
Add menu options to the SynQuacer Platform menu screen to limit the
maximum PCIe link speed for each slot individually. This may be useful
to work around potential PCIe issues.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h index d2a3f9acbf..ee2357be9a 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -60,4 +60,9 @@ #define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff
#define SYNQUACER_PCI_SEG1_MMIO64_SIZE 0x100000000
+#define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d))
+#define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0)
+#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7)
+#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3)
+
#endif
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