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author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-07 13:34:49 +0000 |
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committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-07 13:36:01 +0000 |
commit | ce95ec196da05885844afb79bd2570c5cd9f6b27 (patch) | |
tree | 7d1a2553bb54a57a7129a2576f343fe78e0d42c2 /Silicon/Socionext/SynQuacer/Include | |
parent | 23488946946f9cfb6296b4cf591ef6b86498921f (diff) | |
download | edk2-platforms-ce95ec196da05885844afb79bd2570c5cd9f6b27.tar.xz |
Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC
As it turns out, it is surprisingly easy to configure both the NETSEC
and eMMC devices as cache coherent for DMA, given that they are both
behind the same SMMU which is already configured in passthrough mode
by the firmware running on the SCP.
So update the static SMMU configuration to make memory accesses performed
by these devices inner shareable inner/outer writeback cacheable, which
makes them cache coherent with the CPUs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Include')
-rw-r--r-- | Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index 3c7bd58866..f43adcc860 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -65,4 +65,8 @@ #define SYNQUACER_PCIE_BASE 0x58200000
#define SYNQUACER_PCIE_SIZE 0x00200000
+// SCB SMMU
+#define SYNQUACER_SCB_SMMU_BASE 0x52E00000
+#define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB
+
#endif
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