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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-02-27 13:39:02 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-02-28 08:14:31 +0000 |
| commit | 8e55eaa4c69f28509f3e801cfdb1e8275a579ccf (patch) | |
| tree | 92421c54671b06267116d895223862b974636274 /Silicon/Socionext/SynQuacer/Stage2Tables/GNUmakefile | |
| parent | f90743b8813518fd7111c272ea4a3483a94ed462 (diff) | |
| download | edk2-platforms-8e55eaa4c69f28509f3e801cfdb1e8275a579ccf.tar.xz | |
Silicon/SynQuacer: add stage 2 override translation tables for PCIe
The Designware PCIe IP in the SynQuacer SoC needs a little help to
appear sane to the OS. Not only does it lack a true root port, and
therefore does not perform any filtering whatsoever of type 0 config
TLPs that are not intended for the link peer, it also has trouble
issuing 64-bit wide MMIO accesses, which are often used on MMIO BARs
with memory semantics (e.g., frame buffers).
So let's create a stage 2 mapping covering the entire physical address
space, and remap some ECAM regions and demote write combine attributes
to device/strongly ordered. This is not a water tight fix, but it does
work around the issues in the majority of cases.
(Note that the ECAM remapping can also be addressed in the SMMU mapping
of the PCIe IP exposed to the CPU, but this is currently under
development, and it does not hurt to have it in two places)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Stage2Tables/GNUmakefile')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/Stage2Tables/GNUmakefile | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/GNUmakefile b/Silicon/Socionext/SynQuacer/Stage2Tables/GNUmakefile new file mode 100644 index 0000000000..45ba4b4d8d --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/GNUmakefile @@ -0,0 +1,22 @@ +## @file +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +.PHONY: all +all: $(OUTPUT_DIR)/Stage2Tables.bin + +$(OUTPUT_DIR)/Stage2Tables.bin: $(OUTPUT_DIR)/Stage2Tables.elf + $(OBJCOPY) $(OBJCOPY_FLAGS) $(^) $(@) + +$(OUTPUT_DIR)/Stage2Tables.elf: $(MODULE_DIR)/Stage2Tables.S + $(ASM) $(ASM_FLAGS) -o $(@) $(^) |