BroxtonSiPkg: Add BroxtonSiPkg .dsc and .dec files

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>

7 files changed, 615 insertions, 0 deletions

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec b/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec
new file mode 100644
index 0000000000..eaf8fb9741
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec
@@ -0,0 +1,352 @@
+## @file

+#  Module describe the entire platform configuration.

+#

+#  The DEC files are used by the EDK II utilities that parse EDK II

+#  DSC and EDK II INF files to generate AutoGen.c and AutoGen.h files

+#  for the EDK II build infrastructure.

+#

+#  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+[Defines]

+  DEC_SPECIFICATION              = 0x00010005

+  PACKAGE_NAME                   = BxtSocRefCodePkg

+  PACKAGE_GUID                   = E4FA0DCA-91A3-4957-9344-C10BAA0BFE5F

+  PACKAGE_VERSION                = 0.1

+

+[Ppis]

+  gVariableStoragePpiGuid                     = { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7, 0x6f, 0x9,  0xe5, 0x78, 0x91, 0x65, 0x48}}

+  gPeiSmmAccessPpiGuid                        = { 0x268f33a9, 0xcccd, 0x48be, {0x88, 0x17, 0x86, 0x05, 0x3a, 0xc3, 0x2e, 0xd6}}

+  gSaPlatformPolicyPpiGuid                    = { 0x7D84B2C2, 0x22A1, 0x4372, {0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3}}

+  gSiSaPolicyPpiGuid                          = { 0x65289ae5, 0x1589, 0x484c, {0xa6, 0x10, 0x90, 0xe1, 0x0a, 0xc2, 0xdb, 0x28}}

+  gSiSaPreMemPolicyPpiGuid                    = { 0xcfe5ec91, 0x31ed, 0x47e9, {0xbe, 0x7d, 0x9c, 0xcb, 0x59, 0x13, 0x4b, 0x71}}

+  gSaPolicyPpiGuid                            = { 0xf6435590, 0x2402, 0x4e02, {0x99, 0xfd, 0xab, 0xdd, 0x9d, 0xd4, 0x0a, 0x6a}}

+  gScPolicyPpiGuid                            = { 0x10164673, 0xD365, 0x4BE2, {0x85, 0x13, 0x14, 0x97, 0xCC, 0x07, 0x61, 0x1D}}

+  gScPreMemPolicyPpiGuid                      = { 0x820695b0, 0xc2f2, 0x4ec7, { 0xa2, 0x52, 0xdb, 0xd, 0xbe, 0xe8, 0x38, 0xa3}}

+  gPeiSpiPpiGuid                              = { 0xA38C6898, 0x2B5C, 0x4FF6, {0x93, 0x26, 0x2E, 0x63, 0x21, 0x2E, 0x56, 0xC2}}

+  gSaPeiInitPpiGuid                           = { 0x09ea8911, 0xbe0d, 0x4230, {0xa0, 0x03, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11}}

+  gSeCUmaPpiGuid                              = { 0xcbd86677, 0x362f, 0x4c04, {0x94, 0x59, 0xa7, 0x41, 0x32, 0x6e, 0x05, 0xcf}}

+  gPeiSeCPlatformPolicyPpiGuid                = { 0x7ae3ceb7, 0x2ee2, 0x48fa, {0xaa, 0x49, 0x35, 0x10, 0xbc, 0x83, 0xca, 0xbf}}

+  gPlatformSeCHookPpiGuid                     = { 0xe806424f, 0xd425, 0x4b1a, {0xbc, 0x26, 0x5f, 0x69, 0x03, 0x89, 0xa1, 0x5a}}

+  gPeiHeciPpiGuid                             = { 0xEE0EA811, 0xFBD9, 0x4777, {0xB9, 0x5A, 0xBA, 0x4F, 0x71, 0x10, 0x1F, 0x74}}

+  gPeiSdhcPpiGuid                             = { 0xf4ef9d7a, 0x98c5, 0x4c1a, {0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0x0c}}

+  gPeiBlockIoPpiGuid                          = { 0xbc5fa650, 0xedbb, 0x4d0d, {0xb3, 0xa3, 0xd9, 0x89, 0x07, 0xf8, 0x47, 0xdf}}

+  gSeCfTPMPolicyPpiGuid                       = { 0x4fd1ba49, 0x8f90, 0x471a, {0xa2, 0xc9, 0x17, 0x3c, 0x7a, 0x73, 0x2f, 0xd0}}

+  gEfiHeciPpiGuid                             = { 0x21d56275, 0xf984, 0x405f, {0x9f, 0x0b, 0xea, 0x08, 0x4d, 0xef, 0x0a, 0x7e}}

+  gCseEmmcSelectPpiGuid                       = { 0x1e30e33d, 0x1854, 0x437a, {0xbd, 0x68, 0xfc, 0x15, 0x53, 0xaa, 0x8b, 0xe4}}

+  gCseUfsSelectPpiGuid                        = { 0xc5a6189e, 0x8c33, 0x4ac6, {0xae, 0x9a, 0xae, 0xd1, 0x8c, 0xab, 0xe2, 0x6d}}

+  gCseSpiSelectPpiGuid                        = { 0xd35eda81, 0x07d0, 0x4142, {0x94, 0x9,  0xb0, 0x72, 0x33, 0xed, 0x2d, 0x7 }}

+  gDramPolicyPpiGuid                          = { 0x563f8ede, 0x1fa5, 0x45a2, {0xbe, 0x23, 0xb0, 0xb6, 0xa0, 0x7d, 0xe2, 0x39}}

+  gBiosReservedMemoryPolicyPpiGuid            = { 0x1f642910, 0x3d7b, 0x4627, {0x8d, 0x18, 0xdc, 0x62, 0x67, 0x1e, 0x05, 0x54}}

+  gReadOnlyVariablePreMemoryDescriptorPpiGuid = { 0xbe136fc9, 0xc277, 0x4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}}

+

+  #

+  # Common

+  #

+  gSiPolicyPpiGuid                      = { 0xaebffa01, 0x7edc, 0x49ff, { 0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}}

+  gScPcieDeviceTablePpiGuid             = { 0xaf4a1998, 0x4949, 0x4545, { 0x9c, 0x4c, 0xc1, 0xe7, 0xc0, 0x42, 0xe0, 0x56}}

+  gScSpiPpiGuid                         = { 0x21EA1481, 0xAA3D, 0x42AD, { 0xAB, 0xA3, 0xFA, 0xF3, 0x33, 0x41, 0x7E, 0xB3}}

+  #

+  # Cpu

+  #

+  gSiCpuPolicyPpiGuid                   = { 0xf8d5438e, 0x26e1, 0x481d, {0xb6, 0x3c, 0x30, 0xd6, 0xef, 0xf4, 0xa4, 0x20}}

+  #

+  # CPU Config Block IP GUID

+  #

+  gCpuConfigPreMemGuid                  = { 0xac74ec70, 0xce7f, 0x4ac5, { 0x90, 0xfd, 0xe6, 0x22, 0x42, 0x67, 0xf8, 0x9f}}

+  gCpuConfigGuid                        = { 0xb326872a, 0x4dc2, 0x4db3, { 0x88, 0xb2, 0xf6, 0xc4, 0x47, 0x5f, 0x8c, 0x91}}

+  gTxtConfigGuid                        = { 0xf98f3432, 0x4f68, 0x4920, { 0xa8, 0x2, 0xcb, 0x4b, 0x8c, 0x1f, 0x76, 0x6c }}

+  gPowerMgmtConfigGuid                  = { 0xdb73174e, 0xe46a, 0x4927, { 0x99, 0x47, 0xcf, 0x2d, 0xbe, 0xaf, 0x16, 0x81}}

+  gSoftwareGuardConfigGuid              = { 0x4e509696, 0xe33f, 0x408e, { 0x9a, 0xf5, 0xcc, 0x8c, 0x20, 0x6, 0x53, 0x85 }}

+  gBiosGuardConfigGuid                  = { 0x10db0a54, 0xf6f9, 0x4ca2, { 0xa7, 0x5e, 0xf9, 0xaa, 0xca, 0xe7, 0x9, 0x70 }}

+  gCpuOverclockingConfigGuid            = { 0x3b3ee27e, 0x9bef, 0x463f, { 0xb0, 0x3a, 0xa5, 0xc9, 0xa0, 0x98, 0xb7, 0xb5}}

+  #

+  # NC Config Block IP GUID

+  #

+  gSaMiscConfigGuid                     = { 0xc5c9145f, 0x61fb, 0x4abe, { 0x88, 0x0a, 0xf2, 0x56, 0x89, 0x9f, 0x40, 0xb0}}

+  gGraphicsConfigGuid                   = { 0x0319c56b, 0xc43a, 0x42f1, { 0x80, 0xbe, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}}

+  gMemoryConfigGuid                     = { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1, 0x97, 0xb8, 0xa1, 0xe4, 0xbf}}

+  gIpuConfigGuid                        = { 0x67eeefd0, 0x9e42, 0x48c8, { 0xbd, 0xab, 0xfd, 0x0d, 0x23, 0x69, 0x88, 0x0b}}

+  gHybridGraphicsConfigGuid             = { 0x0b7e694d, 0xb909, 0x4097, { 0x9c, 0x03, 0x5e, 0x72, 0x84, 0x89, 0xf7, 0x09}}

+  gSaPreMemConfigGuid                   = { 0x7200eef0, 0xbe7f, 0x4061, { 0x93, 0xe3, 0x3c, 0xd0, 0x36, 0x7c, 0xe1, 0x51}}

+

+[Protocols]

+  gVariableStorageProtocolGuid          = { 0xa073a3a6, 0x96ec, 0x4173, {0xa9, 0xbc, 0x39, 0x95, 0x06, 0xcd, 0xea, 0xc6}}

+  gEfiGlobalNvsAreaProtocolGuid         = { 0x074e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc}}

+  gPpmPlatformPolicyProtocolGuid        = { 0xddabfeac, 0xef63, 0x452c, {0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}}

+  gScSpiProtocolGuid                    = { 0x1156efc6, 0xea32, 0x4396, {0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13}}

+  gMemInfoProtocolGuid                  = { 0x6f20f7c8, 0xe5ef, 0x4f21, {0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae}}

+  gEfiMmcHostIoProtocolGuid             = { 0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51}}

+  gEfiSdHostIoProtocolGuid              = { 0xe7202b43, 0xb3c1, 0x41d8, {0xba, 0xa2, 0xfb, 0x71, 0x9e, 0xc5, 0xd5, 0xe6}}

+  gDxePlatformTdtPolicyGuid             = { 0x20daf0fc, 0x5548, 0x44dc, {0xa4, 0x2a, 0x60, 0xea, 0xf0, 0xa2, 0x2e, 0x47}}

+  gScSmmSpiProtocolGuid                 = { 0xD9072C35, 0xEB8F, 0x43AD, {0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85}}

+  gEfiSmmIchnDispatchExProtocolGuid     = { 0x3920405B, 0xC897, 0x44DA, {0x88, 0xF3, 0x4C, 0x49, 0x8A, 0x6F, 0xF7, 0x36}}

+  gEfiScS3SupportProtocolGuid           = { 0xE287D20B, 0xD897, 0x4E1E, {0xA5, 0xD9, 0x97, 0x77, 0x63, 0x93, 0x6A, 0x04}}

+  gScResetProtocolGuid                  = { 0xDB63592C, 0xB8CC, 0x44C8, {0x91, 0x8C, 0x51, 0xF5, 0x34, 0x59, 0x8A, 0x5A}}

+  gScResetCallbackProtocolGuid          = { 0x3A3300AB, 0xC929, 0x487D, {0xAB, 0x34, 0x15, 0x9B, 0xC1, 0x35, 0x62, 0xC0}}

+  gEfiInfoProtocolGuid                  = { 0xD31F0400, 0x7D16, 0x4316, {0xBF, 0x88, 0x60, 0x65, 0x88, 0x3B, 0x40, 0x2B}}

+  gEfiExtendedResetProtocolGuid         = { 0xF0BBFCA0, 0x684E, 0x48B3, {0xBA, 0xE2, 0x6C, 0x84, 0xB8, 0x9E, 0x53, 0x39}}

+  gEfiActiveBiosProtocolGuid            = { 0xEBBE2D1B, 0x1647, 0x4BDA, {0xAB, 0x9A, 0x78, 0x63, 0xE3, 0x96, 0xD4, 0x1A}}

+  gDxeIchPlatformPolicyProtocolGuid     = { 0xf617b358, 0x12cf, 0x414a, {0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb3}}

+  gEfiIchInfoProtocolGuid               = { 0xd31f0400, 0x7d16, 0x4316, {0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b}}

+  gEfiSmmIoTrapDispatchProtocolGuid     = { 0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0x0e, 0x29, 0x41, 0x8d, 0xf9, 0x30}}

+  gSaPolicyProtocolGuid                 = { 0xd5649aca, 0xda40, 0x4c58, {0xa4, 0xdf, 0x8e, 0x42, 0xeb, 0x40, 0xa1, 0x80}}

+  gIgdOpRegionProtocolGuid              = { 0xcdc5dddf, 0xe79d, 0x41ec, {0xa9, 0xb0, 0x65, 0x65, 0x49, 0x0d, 0xb9, 0xd3}}

+  gEfiHeciProtocolGuid                  = { 0x3c7bc880, 0x41f8, 0x4869, {0xae, 0xfc, 0x87, 0x0a, 0x3e, 0xd2, 0x82, 0x99}}

+  gEfiHeci2PmProtocolGuid               = { 0x35169d2c, 0x2426, 0x45cc, {0x8a, 0xf4, 0x5b, 0x61, 0x8b, 0xc9, 0xa0, 0x0a}}

+  gEfiHeciSmmRuntimeProtocolGuid        = { 0x6572045f, 0xb1bf, 0x458e, {0xbc, 0x02, 0x70, 0x67, 0x62, 0xc6, 0x09, 0xae}}

+  gEfiHeciSmmProtocolGuid               = { 0xFC53F573, 0x17DD, 0x454C, {0xB0, 0x67, 0xEC, 0xB1, 0x0B, 0x7D, 0x7F, 0xC7}}

+  gPlatformSeCHookProtocolGuid          = { 0xbc52476e, 0xf67e, 0x4301, {0xb2, 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2}}

+  gEfiSeCRcInfoProtocolGuid             = { 0x11fbfdfb, 0x10d2, 0x43e6, {0xb5, 0xb1, 0xb4, 0x38, 0x6e, 0xdc, 0xcb, 0x9a}}

+  gEfiTdtProtocolGuid                   = { 0x0bf70067, 0xd53b, 0x42df, {0xb7, 0x70, 0xe9, 0x2c, 0x91, 0xc6, 0x14, 0x11}}

+  gDxePlatformSeCPolicyGuid             = { 0xf8bff014, 0x18fb, 0x4ef9, {0xb1, 0x0c, 0xae, 0x22, 0x73, 0x8d, 0xbe, 0xed}}

+  gEfiEmmcCardInfoProtocolGuid          = { 0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd}}

+  gScPcieSmiDispatchProtocolGuid        = { 0x3E7D2B56, 0x3F47, 0x42AA, {0x8F, 0x6B, 0x22, 0xF5, 0x19, 0x81, 0x8D, 0xAB}}

+  gScNvsAreaProtocolGuid                = { 0x2E058B2B, 0xEDC1, 0x4431, {0x87, 0xD9, 0xC6, 0xC4, 0xEA, 0x10, 0x2B, 0xE3}}

+  gScSmmIoTrapControlGuid               = { 0x514D2AFD, 0x2096, 0x4283, {0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5}}

+  gEfiSmmSmbusProtocolGuid              = { 0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}

+  gPchEmmcTuningProtocolGuid            = { 0x10fe7e3b, 0xdbe5, 0x4cfa, {0x90, 0x25, 0x40, 0x02, 0xcf, 0xdd, 0xbb, 0x89}}

+  gEfiEmmcBootPartitionProtocolGuid     = { 0xea7d60a6, 0x1050, 0x45e4, {0xbe, 0xdf, 0xbf, 0x17, 0x72, 0x90, 0xd4, 0xb2}}

+  gCpuInfoProtocolGuid                  = { 0xe223cf65, 0xf6ce, 0x4122, {0xb3, 0xaf, 0x4b, 0xd1, 0x8a, 0xff, 0x40, 0xa1}}

+  gCpuGlobalNvsAreaProtocolGuid         = { 0xab5a4df4, 0xf0d7, 0x49a8, {0xbf, 0x5c, 0xf2, 0x5d, 0xa0, 0x4c, 0x25, 0x33}}

+  gEfiLegacyBiosProtocolGuid            = { 0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}

+  gPowerMgmtInitDoneProtocolGuid        = { 0xd71db106, 0xe32d, 0x4225, {0xbf, 0xf4, 0xde, 0x6d, 0x77, 0x87, 0x17, 0x61}}

+  gEfiAcpiSupportProtocolGuid           = { 0xdbff9d55, 0x89b7, 0x46da, {0xbd, 0xdf, 0x67, 0x7d, 0x3d, 0xc0, 0x24, 0x1d}}

+  gIntegratedTouchHidProtocolGuid       = { 0x3d0479c1, 0x6b19, 0x4191, {0xb8, 0x09, 0x60, 0x08, 0xdd, 0x07, 0x97, 0xa0}}

+  gIgdPanelConfigGuid                   = { 0x5fd88b4c, 0xb658, 0x4650, {0xb3, 0xce, 0xa5, 0x9b, 0xb9, 0x91, 0xbf, 0xd4}}

+  gSaDxeMiscConfigGuid                  = { 0xc7715fbc, 0xe2ab, 0x4a33, {0x84, 0x0f, 0x5d, 0xcd, 0x01, 0x98, 0xe5, 0x52}}

+  gEfiSpiAcpiProtocolGuid               = { 0x9f49a879, 0x3d71, 0x42b3, {0xa0, 0xad, 0xdd, 0xb1, 0xf3, 0x30, 0x10, 0xa3}}

+  gEfiSpiHostProtocolGuid               = { 0x951b65e5, 0x8872, 0x41ed, {0xad, 0x1d, 0xd5, 0x68, 0x1f, 0x4a, 0xf0, 0x33}}

+  gEfiSpiBusProtocolGuid                = { 0x137b3044, 0xf6d7, 0x473e, {0xa6, 0x25, 0x9f, 0xb9, 0x25, 0x05, 0xc1, 0x80}}

+  gEfiMmioDeviceProtocolGuid            = { 0x24486226, 0xf8c2, 0x41f5, {0xb9, 0xdd, 0x78, 0x3e, 0x9e, 0x56, 0xde, 0xa0}}

+  gEfiDataHubProtocolGuid               = { 0xae80d021, 0x618e, 0x11d4, {0xbc, 0xd7, 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81}}

+  gEfiLegacyInterruptProtocolGuid       = { 0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}

+  gEfiSmmIchnDispatchProtocolGuid       = { 0xc50b323e, 0x9075, 0x4f2a, {0xac, 0x8e, 0xd2, 0x59, 0x6a, 0x10, 0x85, 0xcc}}

+  gExitPmAuthProtocolGuid               = { 0xd088a413, 0xa70 , 0x4217, {0xba, 0x55, 0x9a, 0x3c, 0xb6, 0x5c, 0x41, 0xb3}}

+  ##

+  ## Hsti

+  ##

+  gHstiProtocolGuid                     = { 0x1b05de41, 0xc93b, 0x4bb4, {0xad, 0x47, 0x2a, 0x78, 0xac, 0xf , 0xc9, 0xe4}}

+  gHstiPublishCompleteProtocolGuid      = { 0x0f500be6, 0xece4, 0x4ed8, {0x90, 0x81, 0x9a, 0xa9, 0xa5, 0x23, 0xfb, 0x7b}}

+  gEfiAdapterInformationProtocolGuid    = { 0xE5DD1403, 0xD622, 0xC24E, {0x84, 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02}}

+

+  ##

+  ## Silicon Policy

+  ##

+  gDxeSiPolicyProtocolGuid              = { 0xeca27516, 0x306c, 0x4e28, {0x8c, 0x94, 0x4e, 0x52, 0x10, 0x96, 0x69, 0x5e}}

+

+[Guids]

+  ##

+  ## Common

+  ##

+  gSiPkgTokenSpaceGuid                    = { 0x977c97c1, 0x47e1, 0x4b6b, { 0x96, 0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b}}

+  gEfiCPTokenSpaceGuid                    = { 0x918211ce, 0xa1d2, 0x43a0, { 0xa0, 0x4e, 0x75, 0xb5, 0xbf, 0x44, 0x50, 0x0E}}

+  gEfiMemoryConfigDataGuid                = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31}}

+  gEfiBxtTokenSpaceGuid                   = { 0x84da4361, 0xee8a, 0x4769, { 0x93, 0x68, 0x4f, 0x28, 0xa1, 0xc9, 0x20, 0x32}}

+  gSataControllerDriverGuid               = { 0xbb929da9, 0x68f7, 0x4035, { 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55}}

+  gNvmVariableStoreHeaderGuid             = { 0x8f4a7ecb, 0xbd65, 0x4bf7, { 0x9d, 0xed, 0xfa, 0xd7, 0x49, 0xbe, 0xfa, 0xd0}}

+  gCseVariableStoragePpiInstanceGuid      = { 0x9513730d, 0x06ce, 0x4cf6, { 0x9d, 0x95, 0xb0, 0x76, 0x31, 0xbc, 0xd5, 0xa9}}

+  gSpiVariableStoragePpiInstanceGuid      = { 0x5067b88a, 0xaa37, 0x414d, { 0xa3, 0xca, 0xc8, 0x37, 0xfc, 0xec, 0xd6, 0xf3}}

+  gCseVariableStorageProtocolInstanceGuid = { 0x5d5ede0b, 0x5d93, 0x4aae, { 0xa8, 0xec, 0x08, 0x41, 0xd0, 0x53, 0x85, 0xc4}}

+  gSpiVariableStorageProtocolInstanceGuid = { 0xe98252e8, 0xf209, 0x4ef5, { 0xab, 0x7e, 0x12, 0x69, 0x45, 0x14, 0x47, 0xbe}}

+  gCseVariableFileInfoHobGuid             = { 0xb9150dd9, 0x0085, 0x431d, { 0x88, 0xfd, 0x2d, 0xb9, 0xe6, 0x33, 0x69, 0x21}}

+  gCsePreMemoryIndexFileDataHobGuid       = { 0x19c2541a, 0xd0e0, 0x460a, { 0x92, 0x66, 0x23, 0xd9, 0x8b, 0xb2, 0x77, 0xc6}}

+  gCsePrimaryIndexFileDataHobGuid         = { 0x8d97b52d, 0x2805, 0x46a1, { 0x97, 0xd4, 0x07, 0xd4, 0x82, 0x7a, 0xa1, 0x5e}}

+  gFdoModeEnabledHobGuid                  = { 0x7e4b2acb, 0x7391, 0x408f, { 0xb1, 0x43, 0x3a, 0x0b, 0x07, 0xc6, 0xe1, 0x65}}

+  gEfiMemoryConfigVariableGuid            = { 0xb0767cbc, 0x4705, 0x4d35, { 0x88, 0x66, 0x17, 0xa9, 0xb8, 0x5e, 0x38, 0x43}}

+  #

+  # Reset type GUID for S5 charging

+  #

+  gResetTypeGuid                        = { 0x4EDD3DD3, 0x07C6, 0x4557, { 0xB4, 0xE3, 0x2E, 0x12, 0x7E, 0x5B, 0x3B, 0x78}}

+  gDxePolicyUpdateProtocolGuid          = { 0x1a819e49, 0xd8ee, 0x48cb, { 0x9a, 0x9c, 0x0a, 0xa0, 0xd2, 0x81, 0x0a, 0x38}}

+  gPowerManagementAcpiTableStorageGuid  = { 0x161be597, 0xe9c5, 0x49db, { 0xae, 0x50, 0xc4, 0x62, 0xab, 0x54, 0xee, 0xda}}

+  gEfiSetupVariableGuid                 = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9}}

+  gPeiVariableCacheHobGuid              = { 0x35212b29, 0x128a, 0x4754, { 0xb9, 0x96, 0x62, 0x45, 0xcc, 0xa8, 0xa0, 0x66}}

+  gPreMemoryVariableLocationHobGuid     = { 0x3dbe20ba, 0x393e, 0x41d3, { 0x95, 0xa0, 0xdf, 0x47, 0x0f, 0x40, 0x30, 0xb3}}

+  gVbtInfoGuid                          = { 0xa0337044, 0x949c, 0x423e, { 0xb5, 0x81, 0xda, 0xe2, 0xad, 0x43, 0x55, 0x34}}

+  gScInitVariableGuid                   = { 0xe6c2f70a, 0xb604, 0x4877, { 0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb}}

+  gBxtRefCodePkgTokenSpaceGuid          = { 0xb4e58f43, 0x730a, 0x46d7, { 0xb1, 0x5f, 0x1e, 0x6,  0x20, 0x3e, 0xfc, 0x28}}

+  gSeCPlatformReadyToBootGuid           = { 0x03fdf171, 0x1d67, 0x4ace, { 0xa9, 0x04, 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74}}

+  gAmtReadyToBootGuid                   = { 0x40b09b5a, 0xf0ef, 0x4627, { 0x93, 0xd5, 0x27, 0xf0, 0x4b, 0x75, 0x4d, 0x05}}

+  gSaDataHobGuid                        = { 0x29d02ce2, 0x4a2c, 0x45e1, { 0x9d, 0xc1, 0xe7, 0x04, 0x9b, 0x7d, 0xb3, 0x21}}

+  gSiPolicyHobGuid                      = { 0xb3903068, 0x7482, 0x4424, { 0xba, 0x4b, 0x40, 0x5f, 0x8f, 0xd7, 0x65, 0x4e}}

+  gEfiSmbusArpMapGuid                   = { 0x707be83e, 0x0bf6, 0x40a5, { 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2}}

+  gEfiNorthPeakGuid                     = { 0x1e2acc41, 0xe26a, 0x483d, { 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7c}}

+  gEfiBxtVariableGuid                   = { 0x19ad5244, 0xfd6b, 0x4e5c, { 0x82, 0x6a, 0x41, 0x46, 0x46, 0xd6, 0xda, 0x6a}}

+  gProcessorProducerGuid                = { 0x1bf06aea, 0x5bec, 0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30}}

+  gSmramCpuDataHeaderGuid               = { 0x5848fd2d, 0xd6af, 0x474b, { 0x82, 0x75, 0x95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23}}

+  gSmramCpuDataVariableGuid             = { 0x429501d9, 0xe447, 0x40f4, { 0x86, 0x7b, 0x75, 0xc9, 0x3a, 0x1d, 0xb5, 0x4e}}

+  gHtBistHobGuid                        = { 0xbe644001, 0xe7d4, 0x48b1, { 0xb0, 0x96, 0x8b, 0xa0, 0x47, 0xbc, 0x7a, 0xe7}}

+  gCpuInitDataHobGuid                   = { 0x266e31cc, 0x13c5, 0x4807, { 0xb9, 0xdc, 0x39, 0xa6, 0xba, 0x88, 0xff, 0x1a}}

+  gCpuAcpiTableStorageGuid              = { 0xc38fb0e2, 0x0c43, 0x49c9, { 0xb5, 0x44, 0x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}}

+  gBiosGuardHobGuid                     = { 0x66f0c42d, 0x0d0e, 0x4c23, { 0x93, 0xc0, 0x2d, 0x52, 0x95, 0xdc, 0x5e, 0x21}}

+  gBiosGuardModuleGuid                  = { 0x7934156d, 0xcfce, 0x460e, { 0x92, 0xf5, 0xa0, 0x79, 0x09, 0xa5, 0x9e, 0xca}}

+  gEfiBootMediaHobGuid                  = { 0x79e5f681, 0x59f4, 0x4415, { 0x8e, 0x46, 0x8c, 0x22, 0x3c, 0xf5, 0x17, 0xe6}}

+  gEfiPramConfGuid                      = { 0xecb54cd9, 0xe5ae, 0x4fdc, { 0xa9, 0x71, 0xe8, 0x77, 0x75, 0x60, 0x68, 0xf7}}

+  gBiosReserveMemoryHobGuid             = { 0x18ea1142, 0x2d6b, 0x4401, { 0xbd, 0x9e, 0x69, 0xf8, 0x41, 0x12, 0xac, 0x88}}

+  gUfsPhyOverrideHobGuid                = { 0xe2f66ea2, 0x313, 0x4b7e,  { 0xa7, 0x4f, 0x8e, 0x23, 0xa6, 0xfe, 0xb4, 0x49}}

+  gEfiIfwiDnxRequestHobGuid             = { 0xA27E59D5, 0x52F3, 0x4D66, { 0xA8, 0x94, 0x1,  0xD6, 0x93, 0x28, 0x7,  0x35}}

+  gEfiHeciMbpDataHobGuid                = { 0x5AA0697D, 0x7FCC, 0x4ADD, { 0xAA, 0x29, 0x4E, 0xC5, 0x81, 0xA6, 0xC,  0xD0}}

+  gEfiCseEndofPostGuid                  = { 0x16b6109e, 0x194c, 0x440f, { 0x94, 0xf8, 0xc7, 0xcc, 0xcc, 0xc3, 0x2d, 0xeb}}

+  gEfiCseEndofServicesGuid              = { 0xf3009649, 0x36d6, 0x4164, { 0xaa, 0x05, 0xe7, 0x2d, 0xee, 0xa3, 0x72, 0x2f}}

+  gEfiUnbootablePartitionGuid           = { 0x02337e07, 0x2cf2, 0x46be, { 0xbc, 0xf7, 0x83, 0x49, 0x45, 0xfc, 0xce, 0xb9}}

+  gEfiTouchPanelGuid                    = { 0x91b1d27b, 0xe126, 0x48d1, { 0x82, 0x34, 0xd2, 0x8b, 0x81, 0xc8, 0x83, 0x62}}

+  gSaSsdtAcpiTableStorageGuid           = { 0xca89914d, 0x2317, 0x452e, { 0xb2, 0x45, 0x36, 0xc6, 0xfb, 0x77, 0xa9, 0xc6}}

+  gHgAcpiTableStorageGuid               = { 0xcacb3817, 0x81e6, 0x497e, { 0x87, 0xff, 0xc8, 0xfa, 0x8f, 0x24, 0xec, 0x28}}

+  gMicroCodepointerGuid                 = { 0x37d43b2a, 0x43a0, 0x4aea, { 0xab, 0x79, 0xe4, 0xfe, 0xf5, 0x3c, 0xf, 0x12}}

+  gPramAddrDataGuid                     = { 0x454DB25C, 0xE506, 0x4F90, { 0xA6, 0xDF, 0x69, 0xE0, 0x22, 0x3E, 0x3F, 0x2B}}

+  gPrmrrAddrDataGuid                    = { 0x9f813a38, 0x6fb0, 0x4fa7, { 0xaf, 0x79, 0x8a, 0x4e, 0x74, 0xdd, 0x48, 0x33}}

+  gPrmrrSizeHobGuid                     = { 0x990bed44, 0x9b4e, 0x4226, { 0xa5, 0x97, 0x28, 0x36, 0x76, 0x6b, 0x5c, 0x41}}

+  gEfiEmmcWpHobGuid                     = { 0xa8021f3b, 0xb649, 0x4c18, { 0x82, 0x70, 0xa7, 0x96, 0xac, 0xcf, 0x32, 0xe1}}

+  gEfiMdeModulePkgTokenSpaceGuid        = { 0xA1AFF049, 0xFDEB, 0x442a, { 0xB3, 0x20, 0x13, 0xAB, 0x4C, 0xB7, 0x2B, 0xBC}}

+  gEfiSmmPeiSmramMemoryReserveGuid      = { 0x6dadf1d1, 0xd4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}}

+  gEfiMemorySubClassGuid                = { 0x4E8F4EBB, 0x64B9, 0x4e05, { 0x9b, 0x18, 0x4c, 0xfe, 0x49, 0x23, 0x50, 0x97}}

+  gEfiCrashDumpAddrGuid                 = { 0x29aeaf18, 0x893a, 0x4d84, { 0xab, 0x58, 0x42, 0xec, 0xa5, 0xe6, 0x68, 0xc0}}

+  gSsaResultGuid                        = { 0x8f4e928 , 0xf5f , 0x46d4, { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6}}

+  gUfsBootLunIdHobGuid                  = { 0xaa506a03, 0x4a54, 0x492b, { 0x8f, 0x2b, 0x9a, 0xd9, 0xa9, 0x49, 0x35, 0x8a}}

+  gReservedMemoryResourceHobTsegGuid  =  { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}}

+

+  #

+  # SC Config Block IP GUID

+  #

+  gLpcPreMemConfigGuid                  = { 0xf28a9e1b, 0x9d1b, 0x4299, { 0x99, 0xa7, 0xe1, 0x47, 0x51, 0x86, 0x70, 0xfe } }

+  gPcieRpPreMemConfigGuid               = { 0xd5403298, 0x1bca, 0x46bc, { 0x97, 0x6c, 0x87, 0x5c, 0x26, 0x5, 0x6, 0x2c } }

+  gScGeneralConfigGuid                  = { 0x9d445be,  0x3c89, 0x4e4f, { 0xab, 0xe0, 0x51, 0xfa, 0x84, 0xc2, 0xe4, 0xff } }

+  gSataConfigGuid                       = { 0xF5F87B4F, 0xCC3C, 0x408D, { 0x89, 0xE3, 0x61, 0xC5, 0x9C, 0x54, 0x07, 0xC4 } }

+  gPcieRpConfigGuid                     = { 0xc46accbc, 0x5765, 0x40e3, { 0x87, 0xd2, 0x82, 0xa5, 0x68, 0xac, 0x99, 0x1b } }

+  gHpetConfigGuid                       = { 0x5d7b44db, 0x13de, 0x4c8f, { 0x9a, 0xcc, 0xd, 0xd9, 0xe8, 0x5, 0xff, 0xcc } }

+  gSmbusConfigGuid                      = { 0x768007ef, 0xe607, 0x4417, { 0x8f, 0x5d, 0xbc, 0xfe, 0x16, 0xda, 0xe3, 0x36 } }

+  gUsbConfigGuid                        = { 0x5041a6b , 0x4dee, 0x47bb, { 0x9e, 0x58, 0x59, 0x44, 0xd1, 0x87, 0xe, 0xe5 } }

+  gIoApicConfigGuid                     = { 0x106736ba, 0xae07, 0x42c4, { 0x8d, 0x40, 0x45, 0x68, 0xc3, 0x90, 0x6f, 0x5d } }

+  gHdAudioConfigGuid                    = { 0x407868f3, 0xd1a7, 0x46c6, { 0x9f, 0xcb, 0x6f, 0x67, 0xa5, 0xe3, 0xc7, 0xd9 } }

+  gGmmConfigGuid                        = { 0xc4b7f840, 0x1cbf, 0x4cdc, { 0x82, 0x8f, 0x26, 0x61, 0x8, 0x1c, 0x4f, 0x87 } }

+  gPmConfigGuid                         = { 0x5298aaf,  0x9c34, 0x49ad, { 0x84, 0xf5, 0xd0, 0x7c, 0xbc, 0x9f, 0x41, 0x59 } }

+  gLockDownConfigGuid                   = { 0xe70e508f, 0x4466, 0x49f3, { 0xbb, 0xfb, 0xfd, 0xf2, 0x4e, 0x95, 0xd, 0xbc } }

+  gSerialIrqConfigGuid                  = { 0xfbe8af4a, 0x2e50, 0x4047, { 0xa5, 0x95, 0x40, 0xc3, 0x24, 0x59, 0x58, 0x84 } }

+  gVtdConfigGuid                        = { 0x29a7c9c8, 0x6fec, 0x440c, { 0xac, 0xf7, 0xfb, 0x40, 0x57, 0xab, 0x61, 0x6b } }

+  gLpssConfigGuid                       = { 0xd18c0912, 0x6825, 0x4e8f, { 0x8d, 0x5a, 0xaf, 0x7e, 0xed, 0xb2, 0xe5, 0xbc } }

+  gScsConfigGuid                        = { 0xb09ed1e3, 0xdddf, 0x429f, { 0x97, 0x80, 0xc3, 0xb0, 0xc4, 0x85, 0x79, 0x24 } }

+  gIshConfigGuid                        = { 0x10c99a45, 0xe8b2, 0x42e0, { 0x9a, 0xcb, 0x9, 0x7e, 0x9f, 0xf6, 0x7a, 0xe0 } }

+  gFlashProtectionConfigGuid            = { 0xD0F71512, 0x9E32, 0x4CC9, { 0xA5, 0xA3, 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8 } }

+  gDciConfigGuid                        = { 0x9af1e14a, 0xe6b7, 0x4b64, { 0xbb, 0x33, 0x9b, 0x1, 0x33, 0x4c, 0x24, 0xfe } }

+  gP2sbConfigGuid                       = { 0x11354a0c, 0x781e, 0x44a1, { 0xa7, 0x87, 0xc0, 0x17, 0x8c, 0x8d, 0x57, 0xf } }

+  gInterruptConfigGuid                  = { 0x097dccd0, 0xf570, 0x41f6, { 0x9d, 0xf0, 0x72, 0xe2, 0x5a, 0xbe, 0xd3, 0x98 } }

+

+[Includes.common]

+  Include

+  Library

+  NorthCluster

+  NorthCluster/Include

+  SouthCluster

+  SouthCluster/Include

+  SouthCluster/Include/Library

+  SouthCluster/SampleCode/Include

+  Cpu

+  Cpu/Include

+  SampleCode/Include

+  SampleCode/MdeModulePkg/Include

+  SampleCode/IntelFrameworkPkg/Include

+  Txe/Include

+  Txe

+

+[PcdsFixedAtBuild]

+  gEfiBxtTokenSpaceGuid.PcdP2SBBaseAddress|0xD0000000|UINT32|0x10000200

+  gEfiBxtTokenSpaceGuid.PcdPmcIpc1BaseAddress0|0xD1000000|UINT32|0x10000201

+  gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress  |0xD1001000|UINT32|0x10000202

+  gEfiBxtTokenSpaceGuid.PcdPmcIpc1BaseAddress1|0xD1002000|UINT32|0x10000203

+  gEfiBxtTokenSpaceGuid.PcdPmcSsramBaseAddress0|0xD1004000|UINT32|0x10000205

+  gEfiBxtTokenSpaceGuid.PcdPmcSsramBaseAddress1|0xD1006000|UINT32|0x10000206

+

+  gEfiBxtTokenSpaceGuid.PcdEmmcBaseAddress0|0xFE903000|UINT32|0x10000207

+  gEfiBxtTokenSpaceGuid.PcdEmmcBaseAddress1|0xFE904000|UINT32|0x10000208

+  gEfiBxtTokenSpaceGuid.PcdPlatformIdRegisterOffset|0x0|UINT8|0x10000209

+  gEfiBxtTokenSpaceGuid.PcdScAcpiIoPortBaseAddress|0x400|UINT16|0x10000210

+  gEfiBxtTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x10000211

+  gEfiBxtTokenSpaceGuid.PcdSmbiosDefaultSocketDesignation|"U3E1"|VOID*|0x10000212

+  gEfiBxtTokenSpaceGuid.PcdSmbiosDefaultSerialNumber|"To Be Filled By O.E.M."|VOID*|0x10000213

+  gEfiBxtTokenSpaceGuid.PcdSmbiosDefaultAssetTag|"To Be Filled By O.E.M."|VOID*|0x10000214

+  gEfiBxtTokenSpaceGuid.PcdSmbiosDefaultPartNumber|"To Be Filled By O.E.M."|VOID*|0x10000215

+  gEfiBxtTokenSpaceGuid.PcdTcoBaseAddress|0x0500|UINT16|0x10000216

+

+  ##

+  ## PcdNemCodeCacheBase is usally the same as PEI FV Base address,

+  ## FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from PlatformPkg.fdf.

+  ##

+  ## Restriction:

+  ## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + PcdTemporaryRamSize) >= 4K

+  ## 2) PcdTemporaryRamBase >= 4G - 64M

+  ##

+  gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20000009

+  ##

+  ## PcdNemCodeCacheSize is usally the same as PEI FV Size,

+  ## FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf.

+  ##

+  ## Restriction:

+  ## 1) PcdNemTotalCacheSize = PcdNemCodeCacheSize + PcdTemporaryRamSize

+  ## <= Maximun CPU NEM total size (Code + Data)

+  ## = LLC size - 0.5M

+  ## 2) PcdTemporaryRamSize  <= Maximum CPU NEM data size

+  ## =  MLC size

+  ## NOTE: The size restriction may be changed in next generation processor.

+  ##

+  gSiPkgTokenSpaceGuid.PcdNemCodeCacheSize|0x00080000|UINT32|0x20000006

+  gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x10000001

+  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|0xFFE60000|UINT32|0x30000004

+  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32|0x30000005

+  gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x30000006

+

+  ## Maximum size of the PEI variable cache in bytes

+  gSiPkgTokenSpaceGuid.PcdVariableCacheMaximumSize|0x00001000|UINT32|0x30000007

+

+  ## Enable CSE variable HECI transactions in PEI

+  ##   Allow HECI transactions to request variable data outside of MRC training data in PEI

+  ##   This will use the BUP CSE filesystem driver to access such variables

+  gSiPkgTokenSpaceGuid.PcdEnablePeiCseVariableNvmAccess|FALSE|BOOLEAN|0x30000008

+

+  ## Primary CSE variable header region index file name

+  ##   The name of the file on CSE NVM that tracks CSE-stored variables.

+  gSiPkgTokenSpaceGuid.PcdPrimaryCseNvmStoreIndexFileName|L"NVS/INDEX"|VOID*|0x30000009

+

+  ## Enable CSE variables to be stored on the MRC training data file

+  ##   An empty string will not write variable data to the training data file

+  gSiPkgTokenSpaceGuid.PcdEnableCseMrcTrainingDataVariables|L"critical/mrc_trg_data"|VOID*|0x30000010

+

+  ## Determines whether to reinstall the CSE Variable Storage PPI after memory is installed.

+  ##   This could be disabled on some client systems.

+  gSiPkgTokenSpaceGuid.PcdReinstallCseVariablePpi|TRUE|BOOLEAN|0x30000011

+

+[PcdsDynamic, PcdsDynamicEx]

+  gEfiBxtTokenSpaceGuid.PcdIafwPlatformInfo|0x0|UINT32|0x10000220

+  gEfiBxtTokenSpaceGuid.PcdEmmcManufacturerId|0|UINT8|0x10000221

+  gEfiBxtTokenSpaceGuid.PcdProductSerialNumber|0|UINT32|0x10000222

+  gEfiBxtTokenSpaceGuid.PcdSetCoreCount|0|UINT32|0x10000223

+  gEfiBxtTokenSpaceGuid.PcdVtdGfxBaseAddress|0xFED64000|UINT32|0x10000224

+  gSiPkgTokenSpaceGuid.PcdForceVolatileVariable|FALSE|BOOLEAN|0x30000012

+

+[PcdsFeatureFlag]

+  gBxtRefCodePkgTokenSpaceGuid.PcdCeAtaSupport|FALSE|BOOLEAN|0x12

+  gBxtRefCodePkgTokenSpaceGuid.PcdMmcSdMultiBlockSupport|TRUE|BOOLEAN|0x13

+

+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]

+  ##

+  ## SerialIo Uart Configuration

+  gBxtRefCodePkgTokenSpaceGuid.PcdSerialIoUartNumber|2|UINT8|0x00100002

+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034

+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x30001035

+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x30001036

+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037

+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x30001038

+

+  ##

+  ## Silicon Reference Code versions

+  ##

+  gSiPkgTokenSpaceGuid.PcdSiliconRefCodeVersion|0x01010000|UINT32|0x30001039  # 1.1.0.0

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPrivate.dec b/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPrivate.dec
new file mode 100644
index 0000000000..f6a5386047
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPrivate.dec
@@ -0,0 +1,52 @@
+## @file

+#  Module describe the entire platform configuration.

+#

+#  The DEC files are used by the EDK II utilities that parse EDK II

+#  DSC and EDK II INF files to generate AutoGen.c and AutoGen.h files

+#  for the EDK II build infrastructure.

+#

+#  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+[Defines]

+  DEC_SPECIFICATION              = 0x00010005

+  PACKAGE_NAME                   = BxtSocPrivate

+  PACKAGE_GUID                   = DD6CB7A8-32F8-4170-8267-942093A5E5F6

+  PACKAGE_VERSION                = 0.1

+

+[Includes.common]

+  Include/Private

+  Cpu/Include/Private

+  SouthCluster

+  SampleCode/MdeModulePkg/Include

+

+[Guids]

+  #

+  # SouthCluster

+  #

+  gScPolicyHobGuid                  = { 0xc2ad1a7f, 0xd9df, 0x4638, { 0x8d, 0xac, 0x1, 0x59, 0x96, 0xc8, 0x88, 0x57 } }

+  gScDeviceTableHobGuid             = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 } }

+  gScPmcFunctionDisableResetHobGuid = { 0x7701aa8f, 0x27eb, 0x4562, { 0x8c, 0x59, 0x47, 0x31, 0xca, 0xa2, 0x4e, 0x7c } }

+  #

+  # CPU

+  #

+  gCpuStatusCodeDataTypeExceptionHandlerGuid = { 0x3BC2BD12, 0xAD2E, 0x11D5, { 0x87, 0xDD, 0x00, 0x06, 0x29, 0x45, 0xC3, 0xB9 }}

+  gPeiAcpiCpuDataGuid                        = { 0x7682bbef, 0xb0b6, 0x4939, { 0xae, 0x66, 0x1b, 0x3d, 0xf2, 0xf6, 0xaa, 0xf3 }}

+

+[Ppis]

+

+[Protocols]

+  #

+  # PCH

+  #

+  gScPcieIoTrapProtocolGuid = { 0xd66a1cf, 0x79ad, 0x494b, { 0x97, 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 } }

+

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgCommonLib.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgCommonLib.dsc
new file mode 100644
index 0000000000..4b15ed8baa
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgCommonLib.dsc
@@ -0,0 +1,64 @@
+## @file

+#  Component description file for the Broxton RC both Pei and Dxe libraries DSC file.

+#

+#  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+#

+# RC Common Library

+#

+

+#

+# Common

+#

+  AslUpdateLib|$(PLATFORM_SI_PACKAGE)/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf

+  ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf

+  BaseIpcLib|$(PLATFORM_SI_PACKAGE)/Library/PmcIpcLib/BaseIpcLib.inf

+  GpioLib|$(PLATFORM_SI_PACKAGE)/Library/GpioLib/GpioLib.inf

+  MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf

+  SideBandLib|$(PLATFORM_SI_PACKAGE)/Library/SideBandLib/SideBandLib.inf

+  SteppingLib|$(PLATFORM_SI_PACKAGE)/Library/SteppingLib/SteppingLib.inf

+  CseVariableStorageLib|$(PLATFORM_SI_PACKAGE)/Library/Private/BaseCseVariableStorageLib/BaseCseVariableStorageLib.inf

+  VariableStorageSelectorLib|$(PLATFORM_SI_PACKAGE)/Library/BaseVariableStorageSelectorLib/BaseVariableStorageSelectorLib.inf

+  VariableNvmStorageLib|$(PLATFORM_SI_PACKAGE)/Library/BaseVariableNvmStorageLib/BaseVariableNvmStorageLib.inf

+

+#

+# SC

+#

+  PeiDxeSmmScPciExpressHelpersLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/PeiDxeSmmScPciExpressHelpersLib.inf

+  ScPlatformLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/ScPlatformLib/ScPlatformLib.inf

+  UsbCommonLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/Private/PeiDxeUsbCommonLib/PeiDxeUsbCommonLib.inf

+  ScAslUpdateLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/SampleCode/Library/AslUpdate/Dxe/ScAslUpdateLib.inf

+  ScHdaLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/Private/DxeScHdaLib/DxeScHdaLib.inf

+  DxeVtdLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/DxeVtdLib/DxeVtdLib.inf

+

+#

+# NC

+#

+  DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf

+

+#

+# CPU

+#

+  CpuCommonLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/Private/PeiDxeSmmCpuCommonLib/PeiDxeSmmCpuCommonLib.inf

+  CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf

+  RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf

+  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf

+  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf

+

+#

+# TXE

+#

+  HeciInitLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/Private/PeiDxeHeciInitLib/PeiDxeHeciInitLib.inf

+  SeCChipsetLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/PeiDxeSeCChipsetLib/PeiDxeSeCChipsetLib.inf

+  Heci2PowerManagementLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/BaseHeci2PowerManagementNullLib/BaseHeci2PowerManagementNullLib.inf

+

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc
new file mode 100644
index 0000000000..b568bd9c3b
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc
@@ -0,0 +1,44 @@
+## @file

+#  Component description file for the Broxton RC DXE drivers.

+#

+#  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+#

+# CPU

+#

+  $(PLATFORM_SI_PACKAGE)/Cpu/CpuInit/Dxe/CpuInitDxe.inf

+  !if $(PPM_ENABLE) == TRUE

+    $(PLATFORM_SI_PACKAGE)/Cpu/PowerManagement/Dxe/PowerMgmtDxe.inf

+    $(PLATFORM_SI_PACKAGE)/Cpu/PowerManagement/Smm/PowerMgmtSmm.inf

+    $(PLATFORM_SI_PACKAGE)/Cpu/AcpiTables/CpuAcpiTables.inf

+  !endif

+    $(PLATFORM_SI_PACKAGE)/Cpu/SmmAccess/Dxe/SmmAccess.inf

+

+#

+# TXE

+#

+  !if $(SEC_ENABLE) == TRUE

+    $(PLATFORM_SI_PACKAGE)/Txe/Heci/Dxe/Hecidrv.inf

+  !endif

+

+#

+# HSTI

+#

+!if $(HSTI_ENABLE) == TRUE

+$(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf {

+    <LibraryClasses>

+      HstiLib | MdePkg/Library/DxeHstiLib/DxeHstiLib.inf

+      Tpm2CommandLib | SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf

+  }

+!endif

+

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc
new file mode 100644
index 0000000000..ff36dccd49
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc
@@ -0,0 +1,35 @@
+## @file

+#  Component description file for the Broxton RC DXE libraries.

+#

+#  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+#

+# RC Dxe Library

+#

+

+#

+# Common

+#

+  !if $(SMM_VARIABLE_ENABLE) == TRUE

+    CseVariableStorageSelectorLib|$(PLATFORM_SI_PACKAGE)/Library/Private/DxeSmmCseVariableStorageSelectorLib/SmmCseVariableStorageSelectorLib.inf

+  !else

+    CseVariableStorageSelectorLib|$(PLATFORM_SI_PACKAGE)/Library/Private/DxeSmmCseVariableStorageSelectorLib/DxeCseVariableStorageSelectorLib.inf

+  !endif

+  SmmHeciMsgLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/SmmHeciMsgLib/SmmHeciMsgLib.inf

+

+#

+# TXE

+#

+  HeciMsgLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.inf

+  SeCLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/SeCLib/SeCLib.inf

+

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgPei.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgPei.dsc
new file mode 100644
index 0000000000..65cce9f689
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgPei.dsc
@@ -0,0 +1,20 @@
+## @file

+#  Component description file for the Broxton RC PEI drivers.

+#

+#  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+#

+# CPU

+#

+  $(PLATFORM_SI_PACKAGE)/Cpu/SmmAccess/Pei/SmmAccess.inf

+

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgPeiLib.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgPeiLib.dsc
new file mode 100644
index 0000000000..14a887005d
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgPeiLib.dsc
@@ -0,0 +1,48 @@
+## @file

+#  Component description file for the Broxton RC PEI libraries.

+#

+#  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+#

+# RC Pei Library

+#

+

+#

+# Common

+#

+  CseVariableStorageSelectorLib|$(PLATFORM_SI_PACKAGE)/Library/Private/PeiCseVariableStorageSelectorLib/PeiCseVariableStorageSelectorLib.inf

+

+#

+# SC

+#

+  PeiScPolicyLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.inf

+

+#

+# CPU

+#

+  CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf

+  CpuPolicyLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLibPreMem.inf

+  CpuPolicyLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf

+  MpServiceLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/Private/PeiMpServiceLib/PeiMpServiceLib.inf

+  CpuS3Lib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/Private/PeiCpuS3Lib/PeiCpuS3Lib.inf

+

+#

+# NC

+#

+  PeiSaPolicyLib|$(PLATFORM_SI_PACKAGE)/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf

+

+#

+# TXE

+#

+  HeciMsgLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/HeciMsgLib/PeiHeciMsgLib.inf

+