diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-23 10:58:26 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:15:04 +0800 |
| commit | 94eafd1c86b1029bb489ab81f5d4048a54a56d34 (patch) | |
| tree | a16e1e453aae7abca557737ef2a06596828f63c0 /Silicon | |
| parent | 68e0fba8a28aa006bf1ed6db0702fb5a782b8e9d (diff) | |
| download | edk2-platforms-94eafd1c86b1029bb489ab81f5d4048a54a56d34.tar.xz | |
BroxtonSiPkg: Add NorthCluster/AcpiTables
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Silicon')
8 files changed, 3173 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Igfx.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Igfx.asl new file mode 100644 index 0000000000..4ca019966e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Igfx.asl @@ -0,0 +1,1724 @@ +/** @file
+ This file contains the IGD OpRegion/Software ACPI Reference Code.
+ It defines the methods to enable/disable output switching,
+ store display switching and LCD brightness BIOS control
+ and return valid addresses for all display device encoders
+ present in the system, etc.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+External(IPUD)
+External(NDID)
+External(DID1)
+External(DID2)
+External(DID3)
+External(DID4)
+External(DID5)
+External(DID6)
+External(DID7)
+External(DID8)
+External(DID9)
+External(DIDA)
+External(DIDB)
+External(DIDC)
+External(DIDD)
+External(DIDE)
+External(DIDF)
+External(DIDX)
+External(EDPV)
+External(BRTL)
+External(CADL)
+External(NSTE)
+External(CSTE)
+External(OSYS, IntObj)
+External(\GUAM, MethodObj)
+External(DSEN)
+External(S0ID)
+
+//
+// Enable/Disable Output Switching. In WIN2K/WINXP, _DOS = 0 will
+// get called during initialization to prepare for an ACPI Display
+// Switch Event. During an ACPI Display Switch, the OS will call
+// _DOS = 2 immediately after a Notify=0x80 to temporarily disable
+// all Display Switching. After ACPI Display Switching is complete,
+// the OS will call _DOS = 0 to re-enable ACPI Display Switching.
+//
+Method(_DOS, 1)
+{
+ // Store Display Switching and LCD brightness BIOS control bit
+ Store(And(Arg0,7),DSEN)
+}
+//
+// Enumerate the Display Environment. This method will return
+// valid addresses for all display device encoders present in the
+// system. The Miniport Driver will reject the addresses for every
+// encoder that does not have an attached display device. After
+// enumeration is complete, the OS will call the _DGS methods
+// during a display switch only for the addresses accepted by the
+// Miniport Driver. For hot-insertion and removal of display
+// devices, a re-enumeration notification will be required so the
+// address of the newly present display device will be accepted by
+// the Miniport Driver.
+//
+// To Enumeration of the AVStream virtual device as child of GFX
+// BIOS should list the IPU's AVStream virtual Camera device as GPU child device with a unique ID 0x0002wwww in the GFX _DOD method,
+// where "wwww", the latter 16 bits of the ACPI id, is IPU's AVStream virtual Camera's unique ID within the scope of the GFX driver.
+// BIOS shall place the IPU's AVStream virtual Camera device as a child device under GFX ACPI name space.
+// The Camera device definition should have a matching _ADR with same unique ID - "wwww" values that was defined in the GFX _DOD method.
+// In BXT, Intel GFX driver will recognize the "0x000234D7" as a unique ID for IPU's AVStream virtual Camera device by finding out that bit 17 of "0x000234D7" is set,
+// and therefore Intel GFX driver will takes the lower 4 nibbles and enumerates a device with ID INT34D7.
+
+Method(_DOD, 0, Serialized)
+{
+ If (LEqual(IPUD,1)) {
+ //
+ // Increment number of devices if IPU is enabled
+ //
+ Store(1, NDID)
+ } Else {
+ Store(0, NDID)
+ }
+
+ If(LNotEqual(DIDL, Zero))
+ {
+ Store(SDDL(DIDL),DID1)
+ }
+ If(LNotEqual(DDL2, Zero))
+ {
+ Store(SDDL(DDL2),DID2)
+ }
+ If(LNotEqual(DDL3, Zero))
+ {
+ Store(SDDL(DDL3),DID3)
+ }
+ If(LNotEqual(DDL4, Zero))
+ {
+ Store(SDDL(DDL4),DID4)
+ }
+ If(LNotEqual(DDL5, Zero))
+ {
+ Store(SDDL(DDL5),DID5)
+ }
+ If(LNotEqual(DDL6, Zero))
+ {
+ Store(SDDL(DDL6),DID6)
+ }
+ If(LNotEqual(DDL7, Zero))
+ {
+ Store(SDDL(DDL7),DID7)
+ }
+ If(LNotEqual(DDL8, Zero))
+ {
+ Store(SDDL(DDL8),DID8)
+ }
+ If(LNotEqual(DDL9, Zero))
+ {
+ Store(SDDL(DDL9),DID9)
+ }
+ If(LNotEqual(DD10, Zero))
+ {
+ Store(SDDL(DD10),DIDA)
+ }
+ If(LNotEqual(DD11, Zero))
+ {
+ Store(SDDL(DD11),DIDB)
+ }
+ If(LNotEqual(DD12, Zero))
+ {
+ Store(SDDL(DD12),DIDC)
+ }
+ If(LNotEqual(DD13, Zero))
+ {
+ Store(SDDL(DD13),DIDD)
+ }
+ If(LNotEqual(DD14, Zero))
+ {
+ Store(SDDL(DD14),DIDE)
+ }
+ If(LNotEqual(DD15, Zero))
+ {
+ Store(SDDL(DD15),DIDF)
+ }
+
+ // Enumerate the encoders. Note that for
+ // current silicon, the maximum number of encoders
+ // possible is 15.
+
+ If(LEqual(NDID,1))
+ {
+ Name(TMP1,Package() {
+ 0xFFFFFFFF})
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP1,0))
+ } Else {
+ Store(Or(0x10000,DID1),Index(TMP1,0))
+ }
+ Return(TMP1)
+ }
+
+ If(LEqual(NDID,2))
+ {
+ Name(TMP2,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP2,0))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP2,1))
+ } Else {
+ Store(Or(0x10000,DID2),Index(TMP2,1))
+ }
+ Return(TMP2)
+ }
+
+ If(LEqual(NDID,3))
+ {
+ Name(TMP3,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP3,0))
+ Store(Or(0x10000,DID2),Index(TMP3,1))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP3,2))
+ } Else {
+ Store(Or(0x10000,DID3),Index(TMP3,2))
+ }
+ Return(TMP3)
+ }
+
+ If(LEqual(NDID,4))
+ {
+ Name(TMP4,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP4,0))
+ Store(Or(0x10000,DID2),Index(TMP4,1))
+ Store(Or(0x10000,DID3),Index(TMP4,2))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP4,3))
+ } Else {
+ Store(Or(0x10000,DID4),Index(TMP4,3))
+ }
+ Return(TMP4)
+ }
+
+ If(LEqual(NDID,5))
+ {
+ Name(TMP5,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP5,0))
+ Store(Or(0x10000,DID2),Index(TMP5,1))
+ Store(Or(0x10000,DID3),Index(TMP5,2))
+ Store(Or(0x10000,DID4),Index(TMP5,3))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP5,4))
+ } Else {
+ Store(Or(0x10000,DID5),Index(TMP5,4))
+ }
+ Return(TMP5)
+ }
+
+ If(LEqual(NDID,6))
+ {
+ Name(TMP6,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP6,0))
+ Store(Or(0x10000,DID2),Index(TMP6,1))
+ Store(Or(0x10000,DID3),Index(TMP6,2))
+ Store(Or(0x10000,DID4),Index(TMP6,3))
+ Store(Or(0x10000,DID5),Index(TMP6,4))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP6,5))
+ } Else {
+ Store(Or(0x10000,DID6),Index(TMP6,5))
+ }
+ Return(TMP6)
+ }
+
+ If(LEqual(NDID,7))
+ {
+ Name(TMP7,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP7,0))
+ Store(Or(0x10000,DID2),Index(TMP7,1))
+ Store(Or(0x10000,DID3),Index(TMP7,2))
+ Store(Or(0x10000,DID4),Index(TMP7,3))
+ Store(Or(0x10000,DID5),Index(TMP7,4))
+ Store(Or(0x10000,DID6),Index(TMP7,5))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP7,6))
+ } Else {
+ Store(Or(0x10000,DID7),Index(TMP7,6))
+ }
+ Return(TMP7)
+ }
+
+ If(LEqual(NDID,8))
+ {
+ Name(TMP8,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP8,0))
+ Store(Or(0x10000,DID2),Index(TMP8,1))
+ Store(Or(0x10000,DID3),Index(TMP8,2))
+ Store(Or(0x10000,DID4),Index(TMP8,3))
+ Store(Or(0x10000,DID5),Index(TMP8,4))
+ Store(Or(0x10000,DID6),Index(TMP8,5))
+ Store(Or(0x10000,DID7),Index(TMP8,6))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP8,7))
+ } Else {
+ Store(Or(0x10000,DID8),Index(TMP8,7))
+ }
+ Return(TMP8)
+ }
+
+ If(LEqual(NDID,9))
+ {
+ Name(TMP9,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP9,0))
+ Store(Or(0x10000,DID2),Index(TMP9,1))
+ Store(Or(0x10000,DID3),Index(TMP9,2))
+ Store(Or(0x10000,DID4),Index(TMP9,3))
+ Store(Or(0x10000,DID5),Index(TMP9,4))
+ Store(Or(0x10000,DID6),Index(TMP9,5))
+ Store(Or(0x10000,DID7),Index(TMP9,6))
+ Store(Or(0x10000,DID8),Index(TMP9,7))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMP9,8))
+ } Else {
+ Store(Or(0x10000,DID9),Index(TMP9,8))
+ }
+ Return(TMP9)
+ }
+
+ If(LEqual(NDID,0x0A))
+ {
+ Name(TMPA,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPA,0))
+ Store(Or(0x10000,DID2),Index(TMPA,1))
+ Store(Or(0x10000,DID3),Index(TMPA,2))
+ Store(Or(0x10000,DID4),Index(TMPA,3))
+ Store(Or(0x10000,DID5),Index(TMPA,4))
+ Store(Or(0x10000,DID6),Index(TMPA,5))
+ Store(Or(0x10000,DID7),Index(TMPA,6))
+ Store(Or(0x10000,DID8),Index(TMPA,7))
+ Store(Or(0x10000,DID9),Index(TMPA,8))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMPA,9))
+ } Else {
+ Store(Or(0x10000,DIDA),Index(TMPA,9))
+ }
+ Return(TMPA)
+ }
+
+ If(LEqual(NDID,0x0B))
+ {
+ Name(TMPB,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPB,0))
+ Store(Or(0x10000,DID2),Index(TMPB,1))
+ Store(Or(0x10000,DID3),Index(TMPB,2))
+ Store(Or(0x10000,DID4),Index(TMPB,3))
+ Store(Or(0x10000,DID5),Index(TMPB,4))
+ Store(Or(0x10000,DID6),Index(TMPB,5))
+ Store(Or(0x10000,DID7),Index(TMPB,6))
+ Store(Or(0x10000,DID8),Index(TMPB,7))
+ Store(Or(0x10000,DID9),Index(TMPB,8))
+ Store(Or(0x10000,DIDA),Index(TMPB,9))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMPB,10))
+ } Else {
+ Store(Or(0x10000,DIDB),Index(TMPB,10))
+ }
+ Return(TMPB)
+ }
+
+ If(LEqual(NDID,0x0C))
+ {
+ Name(TMPC,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPC,0))
+ Store(Or(0x10000,DID2),Index(TMPC,1))
+ Store(Or(0x10000,DID3),Index(TMPC,2))
+ Store(Or(0x10000,DID4),Index(TMPC,3))
+ Store(Or(0x10000,DID5),Index(TMPC,4))
+ Store(Or(0x10000,DID6),Index(TMPC,5))
+ Store(Or(0x10000,DID7),Index(TMPC,6))
+ Store(Or(0x10000,DID8),Index(TMPC,7))
+ Store(Or(0x10000,DID9),Index(TMPC,8))
+ Store(Or(0x10000,DIDA),Index(TMPC,9))
+ Store(Or(0x10000,DIDB),Index(TMPC,10))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMPC,11))
+ } Else {
+ Store(Or(0x10000,DIDC),Index(TMPC,11))
+ }
+ Return(TMPC)
+ }
+
+ If(LEqual(NDID,0x0D))
+ {
+ Name(TMPD,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPD,0))
+ Store(Or(0x10000,DID2),Index(TMPD,1))
+ Store(Or(0x10000,DID3),Index(TMPD,2))
+ Store(Or(0x10000,DID4),Index(TMPD,3))
+ Store(Or(0x10000,DID5),Index(TMPD,4))
+ Store(Or(0x10000,DID6),Index(TMPD,5))
+ Store(Or(0x10000,DID7),Index(TMPD,6))
+ Store(Or(0x10000,DID8),Index(TMPD,7))
+ Store(Or(0x10000,DID9),Index(TMPD,8))
+ Store(Or(0x10000,DIDA),Index(TMPD,9))
+ Store(Or(0x10000,DIDB),Index(TMPD,10))
+ Store(Or(0x10000,DIDC),Index(TMPD,11))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMPD,12))
+ } Else {
+ Store(Or(0x10000,DIDD),Index(TMPD,12))
+ }
+ Return(TMPD)
+ }
+
+ If(LEqual(NDID,0x0E))
+ {
+ Name(TMPE,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPE,0))
+ Store(Or(0x10000,DID2),Index(TMPE,1))
+ Store(Or(0x10000,DID3),Index(TMPE,2))
+ Store(Or(0x10000,DID4),Index(TMPE,3))
+ Store(Or(0x10000,DID5),Index(TMPE,4))
+ Store(Or(0x10000,DID6),Index(TMPE,5))
+ Store(Or(0x10000,DID7),Index(TMPE,6))
+ Store(Or(0x10000,DID8),Index(TMPE,7))
+ Store(Or(0x10000,DID9),Index(TMPE,8))
+ Store(Or(0x10000,DIDA),Index(TMPE,9))
+ Store(Or(0x10000,DIDB),Index(TMPE,10))
+ Store(Or(0x10000,DIDC),Index(TMPE,11))
+ Store(Or(0x10000,DIDD),Index(TMPE,12))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMPE,13))
+ } Else {
+ Store(Or(0x10000,DIDE),Index(TMPE,13))
+ }
+ Return(TMPE)
+ }
+
+ If(LEqual(NDID,0x0F))
+ {
+ Name(TMPF,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPF,0))
+ Store(Or(0x10000,DID2),Index(TMPF,1))
+ Store(Or(0x10000,DID3),Index(TMPF,2))
+ Store(Or(0x10000,DID4),Index(TMPF,3))
+ Store(Or(0x10000,DID5),Index(TMPF,4))
+ Store(Or(0x10000,DID6),Index(TMPF,5))
+ Store(Or(0x10000,DID7),Index(TMPF,6))
+ Store(Or(0x10000,DID8),Index(TMPF,7))
+ Store(Or(0x10000,DID9),Index(TMPF,8))
+ Store(Or(0x10000,DIDA),Index(TMPF,9))
+ Store(Or(0x10000,DIDB),Index(TMPF,10))
+ Store(Or(0x10000,DIDC),Index(TMPF,11))
+ Store(Or(0x10000,DIDD),Index(TMPF,12))
+ Store(Or(0x10000,DIDE),Index(TMPF,13))
+ If (LEqual(IPUD,1)) {
+ //
+ // IGFX need report IPU0 as GFX0 child
+ //
+ Store(0x000234D7,Index(TMPF,14))
+ } Else {
+ Store(Or(0x10000,DIDF),Index(TMPF,14))
+ }
+ Return(TMPF)
+ }
+
+ If(LEqual(NDID,0x10))
+ {
+ Name(TMPG,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPG,0))
+ Store(Or(0x10000,DID2),Index(TMPG,1))
+ Store(Or(0x10000,DID3),Index(TMPG,2))
+ Store(Or(0x10000,DID4),Index(TMPG,3))
+ Store(Or(0x10000,DID5),Index(TMPG,4))
+ Store(Or(0x10000,DID6),Index(TMPG,5))
+ Store(Or(0x10000,DID7),Index(TMPG,6))
+ Store(Or(0x10000,DID8),Index(TMPG,7))
+ Store(Or(0x10000,DID9),Index(TMPG,8))
+ Store(Or(0x10000,DIDA),Index(TMPG,9))
+ Store(Or(0x10000,DIDB),Index(TMPG,10))
+ Store(Or(0x10000,DIDC),Index(TMPG,11))
+ Store(Or(0x10000,DIDD),Index(TMPG,12))
+ Store(Or(0x10000,DIDE),Index(TMPG,13))
+ Store(Or(0x10000,DIDF),Index(TMPG,14))
+ //
+ // IGFX need report IPU0 as GFX0 child
+ // NDID can only be 0x10 if IPU is enabled
+ //
+ Store(0x000234D7,Index(TMPG,15))
+ Return(TMPG)
+ }
+
+ //
+ // If nothing else, return Unknown LFP.
+ // (Prevents compiler warning.)
+ //
+ Return(Package() {0x00000400})
+}//end Method(_DOD,0)
+
+Device(DD01)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID1),0x400))
+ {
+ Store(0x1, EDPV)
+ Store(DID1, DIDX)
+ Return(1)
+ }
+ If(LEqual(DID1,0))
+ {
+ Return(1)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID1))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+
+ Method(_DCS,0)
+ {
+ Return(CDDS(DID1))
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID1))
+ }
+ //
+ // Device Set State.
+ //
+ // _DSS Table:
+ //
+ // BIT31 BIT30 Execution
+ // 0 0 Don't implement.
+ // 0 1 Cache change. Nothing to Implement.
+ // 1 0 Don't Implement.
+ // 1 1 Display Switch Complete. Implement.
+
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}//Device(DD01)
+
+Device(DD02)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID2),0x400))
+ {
+ Store(0x2, EDPV)
+ Store(DID2, DIDX)
+ Return(2)
+ }
+ If(LEqual(DID2,0))
+ {
+ Return(2)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID2))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+
+ Method(_DCS,0)
+ {
+ Return(CDDS(DID2))
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+
+ Method(_DGS,0)
+ {
+ //
+ // Return the Next State.
+ //
+ Return(NDDS(DID2))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}//Device(DD02)
+
+Device(DD03)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID3),0x400))
+ {
+ Store(0x3, EDPV)
+ Store(DID3, DIDX)
+ Return(3)
+ }
+ If(LEqual(DID3,0))
+ {
+ Return(3)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID3))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID3,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID3))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID3))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}//Device(DD03)
+
+Device(DD04)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID4),0x400))
+ {
+ Store(0x4, EDPV)
+ Store(DID4, DIDX)
+ Return(4)
+ }
+ If(LEqual(DID4,0))
+ {
+ Return(4)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID4))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID4,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID4))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID4))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}//Device(DD04)
+
+
+Device(DD05)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID5),0x400))
+ {
+ Store(0x5, EDPV)
+ Store(DID5, DIDX)
+ Return(5)
+ }
+ If(LEqual(DID5,0))
+ {
+ Return(5)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID5))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID5,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID5))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID5))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}//Device(DD05)
+
+
+Device(DD06)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID6),0x400))
+ {
+ Store(0x6, EDPV)
+ Store(DID6, DIDX)
+ Return(6)
+ }
+ If(LEqual(DID6,0))
+ {
+ Return(6)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID6))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID6,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID6))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID6))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+ }
+}//Device(DD06)
+
+
+Device(DD07)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID7),0x400))
+ {
+ Store(0x7, EDPV)
+ Store(DID7, DIDX)
+ Return(7)
+ }
+ If(LEqual(DID7,0))
+ {
+ Return(7)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID7))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID7,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID7))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID7))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}//Device(DD07)
+
+Device(DD08)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID8),0x400))
+ {
+ Store(0x8, EDPV)
+ Store(DID8, DIDX)
+ Return(8)
+ }
+ If(LEqual(DID8,0))
+ {
+ Return(8)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID8))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID8,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID8))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID8))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+}//Device(DD08)
+
+Device(DD09)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID9),0x400))
+ {
+ Store(0x9, EDPV)
+ Store(DID9, DIDX)
+ Return(9)
+ }
+ If(LEqual(DID9,0))
+ {
+ Return(9)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID9))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID9,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID9))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DID9))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+}//Device(DD09)
+
+Device(DD0A)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDA),0x400))
+ {
+ Store(0xA, EDPV)
+ Store(DIDA, DIDX)
+ Return(0x0A)
+ }
+ If(LEqual(DIDA,0))
+ {
+ Return(0x0A)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDA))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDA,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DIDA))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DIDA))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+}//Device(DD0A)
+
+Device(DD0B)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDB),0x400))
+ {
+ Store(0xB, EDPV)
+ Store(DIDB, DIDX)
+ Return(0X0B)
+ }
+ If(LEqual(DIDB,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDB))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDB,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DIDB))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DIDB))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+}//Device(DD0B)
+
+Device(DD0C)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDC),0x400))
+ {
+ Store(0xC, EDPV)
+ Store(DIDC, DIDX)
+ Return(0X0C)
+ }
+ If(LEqual(DIDC,0))
+ {
+ Return(0x0C)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDC))
+ }
+ }
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDC,0))
+ {
+ Return(0x0C)
+ }
+ Else
+ {
+ Return(CDDS(DIDC))
+ }
+ }
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DIDC))
+ }
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+}//Device(DD0C)
+
+Device(DD0D)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDD),0x400))
+ {
+ Store(0xD, EDPV)
+ Store(DIDD, DIDX)
+ Return(0X0D)
+ }
+ If(LEqual(DIDD,0))
+ {
+ Return(0x0D)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDD))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDD,0))
+ {
+ Return(0x0D)
+ }
+ Else
+ {
+ Return(CDDS(DIDD))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DIDD))
+ }
+
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+}//Device(DD0D)
+
+Device(DD0E)
+{
+
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDE),0x400))
+ {
+ Store(0xE, EDPV)
+ Store(DIDE, DIDX)
+ Return(0X0E)
+ }
+ If(LEqual(DIDE,0))
+ {
+ Return(0x0E)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDE))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDE,0))
+ {
+ Return(0x0E)
+ }
+ Else
+ {
+ Return(CDDS(DIDE))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DIDE))
+ }
+
+ // Device Set State. (See table above.)
+
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+}//Device(DD0E)
+
+Device(DD0F)
+{
+
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDF),0x400))
+ {
+ Store(0xF, EDPV)
+ Store(DIDF, DIDX)
+ Return(0X0F)
+ }
+ If(LEqual(DIDF,0))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDF))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDF,0))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(CDDS(DIDF))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DIDF))
+ }
+
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+}// Device(DD0F)
+
+//
+// Device for eDP
+//
+Device(DD1F)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(EDPV, 0x0))
+ {
+ Return(0x1F)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDX))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(EDPV, 0x0))
+ {
+ Return(0x00)
+ }
+ Else
+ {
+ Return(CDDS(DIDX))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ Return(NDDS(DIDX))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+ //
+ // Query List of Brightness Control Levels Supported.
+ //
+ Method(_BCL,0)
+ {
+ //
+ // List of supported brightness levels in the following sequence.
+ // Level when machine has full power.
+ // Level when machine is on batteries.
+ // Other supported levels.
+ //
+ Return(Package(){80, 50, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100})
+ }
+
+ //
+ // Set the Brightness Level.
+ //
+ Method (_BCM,1)
+ {
+ //
+ // Set the requested level if it is between 0 and 100%.
+ //
+ If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))
+ {
+ \_SB.PCI0.GFX0.AINT(1, Arg0)
+ Store(Arg0,BRTL) // Store Brightness Level.
+ }
+ }
+
+ //
+ // Brightness Query Current level.
+ //
+ Method (_BQC,0)
+ {
+ Return(BRTL)
+ }
+}
+
+Method(SDDL,1)
+{
+ Increment(NDID)
+ Store(And(Arg0,0xF0F),Local0)
+ Or(0x80000000,Local0, Local1)
+ If(LEqual(DIDL,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL2,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL3,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL4,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL5,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL6,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL7,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL8,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL9,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD10,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD11,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD12,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD13,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD14,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD15,Local0))
+ {
+ Return(Local1)
+ }
+ Return(0)
+}
+
+Method(CDDS,1)
+{
+ Store(And(Arg0,0xF0F),Local0)
+
+ If(LEqual(0, Local0))
+ {
+ Return(0x1D)
+ }
+ If(LEqual(CADL, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL2, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL3, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL4, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL5, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL6, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL7, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL8, Local0))
+ {
+ Return(0x1F)
+ }
+ Return(0x1D)
+}
+
+Method(NDDS,1)
+{
+ Store(And(Arg0,0xF0F),Local0)
+
+ If(LEqual(0, Local0))
+ {
+ Return(0)
+ }
+ If(LEqual(NADL, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL2, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL3, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL4, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL5, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL6, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL7, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL8, Local0))
+ {
+ Return(1)
+ }
+ Return(0)
+}
+
+//
+// Device Set State Table
+// BIT31 BIT30 Execution
+// 0 0 Don't implement.
+// 0 1 Cache change. Nothing to Implement.
+// 1 0 Don't Implement.
+// 1 1 Display Switch Complete. Implement.
+//
+
+Method(DSST,1)
+{
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+
+ Store(NSTE,CSTE)
+ }
+}
+//
+// Include IGD OpRegion/Software SCI interrupt handler which is use by
+// the graphics drivers to request data from system BIOS.
+//
+include("IgfxOpRn.asl")
+include ("IgfxDsm.asl")
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxDsm.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxDsm.asl new file mode 100644 index 0000000000..ce950a51e8 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxDsm.asl @@ -0,0 +1,418 @@ +/** @file
+ IGD OpRegion/_DSM Reference Code.
+ This file contains Get BIOS Data and Callback functions for
+ the Integrated Graphics Device (IGD) OpRegion/DSM mechanism.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+External(IPAT)
+External(IPSC)
+External(IBTT)
+External(IBIA)
+External(LIDS)
+External(IDMS)
+External(HVCO)
+External(\DHPD)
+
+//
+// _DSM Device Specific Method
+//
+// Arg0: UUID Unique function identifier
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (1 = Return Supported Functions)
+// Arg3: Additional Inputs/Package Parameters Bits [31:0] input as {Byte0, Byte1, Byte2, Byte3} to BIOS which is passed as 32 bit DWORD by Driver
+//
+Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
+
+ If (LEqual(Arg0, ToUUID ("3E5B41C6-EB1D-4260-9D15-C71FBADAE414"))) {
+ //
+ // _DSM Definition for Igd functions
+ // Arguments:
+ // Arg0: UUID: 3E5B41C6-EB1D-4260-9D15-C71FBADAE414
+ // Arg1: Revision ID: 1
+ // Arg2: Function Index: 16
+ // Arg3: Additional Inputs Bits[31:0] Arg3 {Byte0, Byte1, Byte2, Byte3}
+ //
+ // Return:
+ // Success for simple notification, Opregion update for some routines and a Package for AKSV
+ //
+ //
+ // Switch by function index
+ //
+ Switch(ToInteger(Arg2)) {
+ //
+ // Function Index: 0
+ // Standard query - A bitmask of functions supported
+ //
+ // Return: A bitmask of functions supported
+ //
+ Case (0)
+ {
+ If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+ Store("iGfx Supported Functions Bitmap ", Debug)
+ Return (0x3E7FF)
+ }
+ }
+
+ //
+ // Function Index: 1
+ // Adapter Power State Notification
+ // Arg3 Bits [7:0]: Adapter Power State bits [7:0] from Driver 00h = D0; 01h = D1; 02h = D2; 04h = D3 (Cold/Hot); 08h = D4 (Hibernate Notification)
+ // Return: Success
+ //
+ Case(1) {
+ If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+ Store(" Adapter Power State Notification ", Debug)
+
+#if (ENBDT_PF_ENABLE == 1)
+ //
+ // Handle Low Power S0 Idle Capability if enabled
+ //
+ If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) {
+ //
+ // Call GUAM to trigger CS Entry
+ // If Adapter Power State Notification = D1 (Arg3[0]=0x01)
+ //
+ If (LEqual (And(DerefOf (Index (Arg3,0)), 0xFF), 0x01)) {
+ // GUAM - Global User Absent Mode Notification Method
+ \GUAM(One) // 0x01 - Power State Standby (CS Entry)
+ }
+ }
+#endif
+
+ // Upon notification from driver that the Adapter Power State = D0,
+ // check if previous lid event failed. If it did, retry the lid
+ // event here.
+ If(LEqual(DerefOf (Index (Arg3,0)), 0)) {
+ Store(CLID, Local0)
+ If(And(0x80000000,Local0)) {
+ And(CLID, 0x0000000F, CLID)
+ GLID(CLID)
+ }
+ }
+ Return(0x01)
+ }
+ }
+
+ //
+ // Function Index: 2
+ // Display Power State Notification
+ // Arg3: Display Power State Bits [15:8]
+ // 00h = On
+ // 01h = Standby
+ // 02h = Suspend
+ // 04h = Off
+ // 08h = Reduced On
+ // Return: Success
+ //
+ Case(2) {
+ if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+ Store("Display Power State Notification ", Debug)
+#if (ENBDT_PF_ENABLE == 1)
+ //
+ // Handle Low Power S0 Idle Capability if enabled
+ //
+ If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) {
+ Store(And(DerefOf (Index (Arg3,1)), 0xFF), Local0)
+ //
+ // Call GUAM
+ // If Display Turn ON Notification (Arg3 [1] == 0) for CS Exit
+ //
+ If (LEqual (Local0, 0)) {
+ // GUAM - Global User Absent Mode Notification Method
+ \GUAM(Zero) // 0x00 - Power State On (CS Exit)
+ }
+ }
+#endif
+ Return(0x01)
+ }
+ }
+
+ //
+ // Function Index: 3
+ // BIOS POST Completion Notification
+ // Return: Success
+ //
+ Case(3) {
+ if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+ Store("BIOS POST Completion Notification ", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 4
+ // Pre-Hires Set Mode
+ // Return: Success
+ //
+ Case(4) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("Pre-Hires Set Mode ", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 5
+ // Post-Hires Set Mode
+ // Return: Success
+ //
+ Case(5) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("Post-Hires Set Mode ", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 6
+ // SetDisplayDeviceNotification (Display Switch)
+ // Return: Success
+ //
+ Case(6) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("SetDisplayDeviceNotification", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 7
+ // SetBootDevicePreference
+ // Return: Success
+ //
+ Case(7) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ //<TODO> An OEM may elect to implement this method. In that case,
+ // the input values must be saved into non-volatile storage for
+ // parsing during the next boot. The following Sample code is Intel
+ // validated implementation.
+
+ Store("SetBootDevicePreference ", Debug)
+ And(DerefOf (Index (Arg3,0)), 0xFF, IBTT) // Save the boot display to NVS
+ Return(0x01)
+ }
+ }
+
+ //
+ // Function Index: 8
+ // SetPanelPreference
+ // Return: Success
+ //
+ Case(8) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ // An OEM may elect to implement this method. In that case,
+ // the input values must be saved into non-volatile storage for
+ // parsing during the next boot. The following Sample code is Intel
+ // validated implementation.
+
+ Store("SetPanelPreference ", Debug)
+ //
+ // Set the panel-related NVRAM variables based the input from the driver.
+ //
+ And(DerefOf (Index (Arg3,0)), 0xFF, IPSC)
+
+ //
+ // Change panel type if a change is requested by the driver (Change if
+ // panel type input is non-zero). Zero=No change requested.
+ //
+ If(And(DerefOf (Index (Arg3,1)), 0xFF)) {
+ And(DerefOf (Index (Arg3,1)), 0xFF, IPAT)
+ Decrement(IPAT) // 0 = no change, so fit to CMOS map
+ }
+ And(ShiftRight(DerefOf (Index (Arg3,2)), 4), 0x7, IBIA)
+ Return(0x01) // Success
+ }
+ }
+
+ //
+ // Function Index: 9
+ // FullScreenDOS
+ // Return: Success
+ //
+ Case(9) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("FullScreenDOS ", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 10
+ // APM Complete
+ // Return: Adjusted Lid State
+ //
+ Case(10) {
+ if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+
+ Store("APM Complete ", Debug)
+ Store(ShiftLeft(LIDS, 8), Local0) // Report the lid state
+ Add(Local0, 0x100, Local0) // Adjust the lid state, 0 = Unknown
+ Return(Local0)
+ }
+ }
+
+ //
+ //
+ // Function Index: 13
+ // GetBootDisplayPreference
+ // Arg3 Bits [30:16] : Boot Device Ports
+ // Arg3 Bits [7:0] : Boot Device Type
+ // Return: Boot device port and Boot device type from saved configuration
+ //
+ Case(13) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+
+ Store("GetBootDisplayPreference ", Debug)
+ Or(ShiftLeft(DerefOf (Index (Arg3,3)), 24), ShiftLeft(DerefOf (Index (Arg3,2)), 16), Local0) // Combine Arg3 Bits [31:16]
+ And(Local0, 0xEFFF0000, Local0)
+ And(Local0, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), Local0)
+ Or(IBTT, Local0, Local0) // Arg3 Bits [7:0] = Boot device type
+ Return(Local0)
+ }
+ }
+
+ //
+ // Function Index: 14
+ // GetPanelDetails
+ // Return: Different Panel Settings
+ //
+ Case(14) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("GetPanelDetails ", Debug)
+
+ //
+ // Report the scaling setting
+ // Bits [7:0] - Panel Scaling
+ // Bits contain the panel scaling user setting from CMOS
+ // 00h = On: Auto
+ // 01h = On: Force Scaling
+ // 02h = Off
+ // 03h = Maintain Aspect Ratio
+ //
+ Store(IPSC, Local0)
+ Or(Local0, ShiftLeft(IPAT, 8), Local0)
+
+ //
+ // Adjust panel type, 0 = VBT default
+ // Bits [15:8] - Panel Type
+ // Bits contain the panel type user setting from CMOS
+ // 00h = Not Valid, use default Panel Type & Timings from VBT
+ // 01h - 0Fh = Panel Number
+ //
+ Add(Local0, 0x100, Local0)
+
+ //
+ // Report the lid state and Adjust it
+ // Bits [16] - Lid State
+ // Bits contain the current panel lid state
+ // 0 = Lid Open
+ // 1 = Lid Closed
+ //
+ Or(Local0, ShiftLeft(LIDS, 16), Local0)
+ Add(Local0, 0x10000, Local0)
+
+ //
+ // Report the BIA setting
+ // Bits [22:20] - Backlight Image Adaptation (BIA) Control
+ // Bits contain the backlight image adaptation control user setting from CMOS
+ // 000 = VBT Default
+ // 001 = BIA Disabled (BLC may still be enabled)
+ // 010 - 110 = BIA Enabled at Aggressiveness Level [1 - 5]
+ //
+ Or(Local0, ShiftLeft(IBIA, 20), Local0)
+ Return(Local0)
+ }
+ }
+
+ //
+ // Function Index: 15
+ // GetInternalGraphics
+ // Return: Different Internal Grahics Settings
+ //
+
+ Case(15) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("GetInternalGraphics ", Debug)
+
+ Store(GIVD, Local0) // Local0[0] - VGA mode(1=VGA)
+ Xor(Local0, 1, Local0) // Invert the VGA mode polarity
+
+ Or(Local0, ShiftLeft(GMFN, 1), Local0) // Local0[1] - # IGD PCI functions-1
+ // Local0[3:2] - Reserved
+ // Local0[4] - IGD D3 support(0=cold)
+ // Local0[10:5] - Reserved
+ Or(Local0, ShiftLeft(3, 11), Local0) // Local0[12:11] - DVMT version (11b = 5.0)
+
+ //
+ // Report DVMT 5.0 Total Graphics memory size.
+ //
+ Or(Local0, ShiftLeft(IDMS, 17), Local0) // Bits 20:17 are for Gfx total memory size
+
+ //
+ // If the "Set Internal Graphics" call is supported, the modified
+ // settings flag must be programmed per the specification. This means
+ // that the flag must be set to indicate that system BIOS requests
+ // these settings. Once "Set Internal Graphics" is called, the
+ // modified settings flag must be cleared on all subsequent calls to
+ // this function.
+ //
+ // Report the graphics frequency based on B0:D2:F0:RF0h[12]. Must
+ // take into account the current VCO.
+ //
+#if (ENBDT_PF_ENABLE == 1)
+ Or(ShiftLeft(DeRefOf(Index(DeRefOf(Index(CDCT, HVCO)), CDVL)), 21),Local0, Local0)
+ Return(Local0)
+#endif
+ }
+ }
+
+ //
+ // Function Index: 16
+ // GetAKSV
+ // Retrun: 5 bytes of AKSV
+ //
+
+ Case(16) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("GetAKSV", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+ //
+ // Function Index: 17 Set DISPLAY_HPD_CTL
+ //
+ // Arg2: function = PMC_HPD_CTL (define as next function # available)
+ // Arg3: value to be programmed
+ // Function PMC_HPD_CTL:
+ // Feature Overview:
+ // During DC9, Display Engine HPD logic is powered off. This requires special handling from PMC, Punit/PCU and DE.
+ // Based on BIOS configuration, PMC will detect Hotplug events and wakes system while display engine is powered off.
+ // ->Detects rising edge, falling edge or any edge
+ // PMC communicates Hotplug event to Punit/PCU to DE. DE generates new "PCU Interrupt for DDI" to IA.
+ // IA calls driver ISR to handle the interrupt
+ //
+
+ Case(17) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("SetDHPD", Debug)
+ Store(arg3, \DHPD)
+ }
+ }
+
+ } // End of switch(Arg2)
+
+ } // End of if (ToUUID("3E5B41C6-EB1D-4260-9D15-C71FBADAE414D"))
+ Return (Buffer () {0x00})
+} // End of _DSM
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxOpMobf.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxOpMobf.asl new file mode 100644 index 0000000000..e545f96789 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxOpMobf.asl @@ -0,0 +1,459 @@ +/** @file
+ IGD OpRegion/Software SCI Reference Code for the Broxton Family.
+ This file contains ASL code with the purpose of handling events
+ i.e. hotkeys and other system interrupts.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+External (GSMI)
+
+// Notes:
+// 1. The following routines are to be called from the appropriate event
+// handlers.
+// 2. This code cannot comprehend the exact implementation in the OEM's BIOS.
+// Therefore, an OEM must call these methods from the existing event
+// handler infrastructure. Details on when/why to call each method is
+// included in the method header under the "usage" section.
+
+
+/************************************************************************;
+;* ACPI Notification Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name: PDRD
+;*
+;* Description: Check if the graphics driver is ready to process
+;* notifications and video extensions.
+;*
+;* Usage: This method is to be called prior to performing any
+;* notifications or handling video extensions.
+;* Ex: If (PDRD()) {Return (FAIL)}
+;*
+;* Input: None
+;*
+;* Output: None
+;*
+;* References: DRDY (Driver ready status), ASLP (Driver recommended
+;* sleep timeout value).
+;*
+;************************************************************************/
+
+Method(PDRD)
+{
+ If (LNot(DRDY)) {
+ //
+ // Sleep for ASLP milliseconds if the driver is not ready.
+ //
+ Sleep(ASLP)
+ }
+
+ // If DRDY is clear, the driver is not ready. If the return value is
+ // !=0, do not perform any notifications or video extension handling.
+
+ Return(LNot(DRDY))
+}
+
+/************************************************************************;
+;*
+;* Name: PSTS
+;*
+;* Description: Check if the graphics driver has completed the previous
+;* "notify" command.
+;*
+;* Usage: This method is called before every "notify" command. A
+;* "notify" should only be set if the driver has completed the
+;* previous command. Else, ignore the event and exit the parent
+;* method.
+;* Ex: If (PSTS()) {Return (FAIL)}
+;*
+;* Input: None
+;*
+;* Output: None
+;*
+;* References: CSTS (Notification status), ASLP (Driver recommended sleep
+;* timeout value).
+;*
+;************************************************************************/
+
+Method(PSTS)
+{
+ If (LGreater(CSTS, 2)) {
+ //
+ // Sleep for ASLP milliseconds if the status is not "success,
+ // failure, or pending"
+ //
+ Sleep(ASLP)
+ }
+ Return(LEqual(CSTS, 3)) // Return True if still Dispatched
+}
+
+/************************************************************************;
+;*
+;* Name: GNOT
+;*
+;* Description: Call the appropriate methods to query the graphics driver
+;* status. If all methods return success, do a notification of
+;* the graphics device.
+;*
+;* Usage: This method is to be called when a graphics device
+;* notification is required (display switch hotkey, etc).
+;*
+;* Input: Arg0 = Current event type:
+;* 1 = display switch
+;* 2 = lid
+;* 3 = dock
+;* Arg1 = Notification type:
+;* 0 = Re-enumeration
+;* 0x80 = Display switch
+;*
+;* Output: Returns 0 = success, 1 = failure
+;*
+;* References: PDRD and PSTS methods. OSYS (OS version)
+;*
+;************************************************************************/
+
+Method(GNOT, 2)
+{
+ //
+ // Check for 1. Driver loaded, 2. Driver ready.
+ // If any of these cases is not met, skip this event and return failure.
+ //
+ If (PDRD ()) {
+ Return(0x1) // Return failure if driver not loaded.
+ }
+
+ Store(Arg0, CEVT) // Set up the current event value
+ Store(3, CSTS) // CSTS=BIOS dispatched an event
+
+ Notify(\_SB.PCI0.GFX0,0x80)
+
+ Return(0x0) // Return success
+}
+
+/************************************************************************;
+;*
+;* Name: GHDS
+;*
+;* Description: Handle a hotkey display switching event (performs a
+;* Notify(GFX0, 0).
+;*
+;* Usage: This method must be called when a hotkey event occurs and the
+;* purpose of that hotkey is to do a display switch.
+;*
+;* Input: Arg0 = Toggle table number.
+;*
+;* Output: Returns 0 = success, 1 = failure.
+;* CEVT and TIDX are indirect outputs.
+;*
+;* References: TIDX, GNOT
+;*
+;************************************************************************/
+
+Method(GHDS, 1)
+{
+ Store(Arg0, TIDX) // Store the table number
+ //
+ // Call GNOT for CEVT = 1 = hotkey, notify value = 0
+ //
+ Return(GNOT(1, 0)) // Return stats from GNOT
+}
+
+/************************************************************************;
+;*
+;* Name: GLID
+;*
+;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the
+;* lid notify).
+;*
+;* Usage: This method must be called when a lid event occurs. A
+;* Notify(LID0, 0x80) must follow the call to this method.
+;*
+;* Input: Arg0 = Lid state:
+;* 0 = All closed
+;* 1 = internal LFP lid open
+;* 2 = external lid open
+;* 3 = both external and internal open
+;*
+;* Output: Returns 0=success, 1=failure.
+;* CLID and CEVT are indirect outputs.
+;*
+;* References: CLID, GNOT
+;*
+;************************************************************************/
+
+Method(GLID, 1)
+{
+ Store(Arg0, CLID) // Store the current lid state
+
+ //
+ // Call GNOT for CEVT=2=Lid, notify value = 0
+ //
+ Return(GNOT(2, 0)) // Return stats from GNOT
+}
+
+/************************************************************************;
+;*
+;* Name: GDCK
+;*
+;* Description: Handle a docking event by updating the current docking status
+;* and doing a notification.
+;*
+;* Usage: This method must be called when a docking event occurs.
+;*
+;* Input: Arg0 = Docking state:
+;* 0 = Undocked
+;* 1 = Docked
+;*
+;* Output: Returns 0=success, 1=failure.
+;* CDCK and CEVT are indirect outputs.
+;*
+;* References: CDCK, GNOT
+;*
+;************************************************************************/
+
+Method(GDCK, 1)
+{
+ Store(Arg0, CDCK) // Store the current dock state
+
+ //
+ // Call GNOT for CEVT=4=Dock, notify value = 0
+ //
+ Return(GNOT(4, 0)) // Return stats from GNOT
+}
+
+
+/************************************************************************;
+;* ASLE Interrupt Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name: PARD
+;*
+;* Description: Check if the driver is ready to handle ASLE interrupts
+;* generate by the system BIOS.
+;*
+;* Usage: This method must be called before generating each ASLE
+;* interrupt.
+;*
+;* Input: None
+;*
+;* Output: Returns 0 = success, 1 = failure.
+;*
+;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep
+;* timeout value)
+;*
+;************************************************************************/
+
+Method(PARD)
+{
+ If (LNot (ARDY)) {
+ //
+ // Sleep for ASLP milliseconds if the driver is not ready.
+ //
+ Sleep(ASLP)
+ }
+ //
+ // If ARDY is clear, the driver is not ready. If the return value is
+ // !=0, do not generate the ASLE interrupt.
+ //
+ Return(LNot(ARDY))
+}
+
+/************************************************************************;
+;*
+;* Name: AINT
+;*
+;* Description: Call the appropriate methods to generate an ASLE interrupt.
+;* This process includes ensuring the graphics driver is ready
+;* to process the interrupt, ensuring the driver supports the
+;* interrupt of interest, and passing information about the event
+;* to the graphics driver.
+;*
+;* Usage: This method must called to generate an ASLE interrupt.
+;*
+;* Input: Arg0 = ASLE command function code:
+;* 0 = Set ALS illuminance
+;* 1 = Set backlight brightness
+;* 2 = Do Panel Fitting
+;* Arg1 = If Arg0 = 0, current ALS reading:
+;* 0 = Reading below sensor range
+;* 1-0xFFFE = Current sensor reading
+;* 0xFFFF = Reading above sensor range
+;* Arg1 = If Arg0 = 1, requested backlight percentage
+;*
+;* Output: Returns 0 = success, 1 = failure
+;*
+;* References: PARD method.
+;*
+;************************************************************************/
+
+Method(AINT, 2)
+{
+ //
+ // Return failure if the requested feature is not supported by the
+ // driver.
+ //
+ If (LNot(And(TCHE, ShiftLeft(1, Arg0)))) {
+ Return(0x1)
+ }
+
+ //
+ // Return failure if the driver is not ready to handle an ASLE
+ // interrupt.
+ //
+
+ If (PARD()) {
+ Return(0x1)
+ }
+
+ //
+ // Evaluate the first argument (Panel fitting, backlight brightness, or ALS).
+ //
+ If(LEqual(Arg0, 2)) // Arg0 = 2, so request a panel fitting mode change.
+ {
+ If(CPFM) // If current mode field is non-zero use it.
+ {
+ And(CPFM, 0x0F, Local0) // Create variables without reserved
+ And(EPFM, 0x0F, Local1) // or valid bits.
+
+ If(LEqual(Local0, 1)) // If current mode is centered,
+ {
+ If(And(Local1, 6)) // and if stretched is enabled,
+ {
+ Store(6, PFIT) // request stretched.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 8)) // if aspect ratio is enabled,
+ {
+ Store(8, PFIT) // request aspect ratio.
+ }
+ Else // Only centered mode is enabled
+ {
+ Store(1, PFIT) // so request centered. (No change.)
+ }
+ }
+ }
+ If(LEqual(Local0, 6)) // If current mode is stretched,
+ {
+ If(And(Local1, 8)) // and if aspect ratio is enabled,
+ {
+ Store(8, PFIT) // request aspect ratio.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 1)) // if centered is enabled,
+ {
+ Store(1, PFIT) // request centered.
+ }
+ Else // Only stretched mode is enabled
+ {
+ Store(6, PFIT) // so request stretched. (No change.)
+ }
+ }
+ }
+ If(LEqual(Local0, 8)) // If current mode is aspect ratio,
+ {
+ If(And(Local1, 1)) // and if centered is enabled,
+ {
+ Store(1, PFIT) // request centered.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 6)) // if stretched is enabled,
+ {
+ Store(6, PFIT) // request stretched.
+ }
+ Else // Only aspect ratio mode is enabled
+ {
+ Store(8, PFIT) // so request aspect ratio. (No change.)
+ }
+ }
+ }
+ }
+
+ // The following code for panel fitting (within the Else condition) is retained for backward compatiblity.
+
+ Else // If CFPM field is zero use PFIT and toggle the
+ {
+ Xor(PFIT,7,PFIT) // mode setting between stretched and centered only.
+ }
+
+ Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases.
+
+ Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1]
+ }
+ Else
+ {
+ If(LEqual(Arg0, 1)) // Arg0=1, so set the backlight brightness.
+ {
+ Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255.
+
+ Or(BCLP, 0x80000000, BCLP) // Set the valid bit.
+
+ Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1]
+ }
+ Else
+ {
+ If(LEqual(Arg0, 0)) // Arg0=0, so set the ALS illuminace
+ {
+ Store(Arg1, ALSI)
+
+ Store(1, ASLC) // Store "ALS event" to ASLC[31:1]
+ }
+ Else
+ {
+ Return(0x1) // Unsupported function
+ }
+ }
+ }
+
+ Store(0x01, ASLE) // Generate ASLE interrupt
+ Return(0x0) // Return success
+}
+
+
+/************************************************************************;
+;*
+;* Name: SCIP
+;*
+;* Description: Checks the presence of the OpRegion and SCI
+;*
+;* Usage: This method is called before other OpRegion methods. The
+;* former "GSMI True/False is not always valid. This method
+;* checks if the OpRegion Version is non-zero and if non-zero,
+;* (present and readable) then checks the GSMI flag.
+;*
+;* Input: None
+;*
+;* Output: Boolean True = SCI present.
+;*
+;* References: None
+;*
+;************************************************************************/
+
+Method(SCIP)
+{
+ If (LNotEqual(OVER,0)) // If OpRegion Version not 0.
+ {
+ Return(LNot(GSMI)) // Return True if SCI.
+ }
+
+ Return(0) // Else Return False.
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxOpRn.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxOpRn.asl new file mode 100644 index 0000000000..cf1c332261 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/IgfxOpRn.asl @@ -0,0 +1,277 @@ +/** @file
+ IGD OpRegion/Software SCI Reference Code.
+ This file contains the interrupt handler code for the Integrated
+ Graphics Device (IGD) OpRegion/Software SCI mechanism.
+ It defines OperationRegions to cover the IGD PCI configuration space
+ as described in the IGD OpRegion specification.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+//NOTES:
+//
+// (1) The code contained in this file inherits the scope in which it
+// was included. So BIOS developers must be sure to include this
+// file in the scope associated with the graphics device
+// (ex. \_SB.PCI0.GFX0).
+// (2) Create a _L06 method under the GPE scope to handle the event
+// generated by the graphics driver. The _L06 method must call
+// the GSCI method in this file.
+// (3) The MCHP operation region assumes that _ADR and _BBN names
+// corresponding to bus 0, device0, function 0 have been declared
+// under the PCI0 scope.
+// (4) Before the first execution of the GSCI method, the base address
+// of the GMCH SCI OpRegion must be programmed where the driver can
+// access it. A 32bit scratch register at 0xFC in the IGD PCI
+// configuration space (B0/D2/F0/R0FCh) is used for this purpose.
+//
+// Define an OperationRegion to cover the GMCH PCI configuration space as
+// described in the IGD OpRegion specificiation.
+//
+// Define an OperationRegion to cover the IGD PCI configuration space as
+// described in the IGD OpRegion specificiation.
+//
+External(ASLB)
+
+OperationRegion(IGDP, PCI_Config,0x00,0x100)
+Field(IGDP, AnyAcc, NoLock, Preserve)
+{
+ Offset(0x10), // GTTMMADR
+ MADR, 32,
+ Offset(0x50), // Mirror of Cunit's Graphics Control Register (0:0:0:50h)
+ , 1, // BIT0: GCCLCK
+ GIVD, 1, // BIT1: IGD VGA disable bit
+ , 1, // BIT2: VAMEN
+ , 3, // BIT5:3 Reserved
+ GUMA, 2, // BIT7:6 Stolen memory size
+ , 8, // BIT15:8 GMS
+ Offset(0x54), // Mirror of Cunit's DevEn Register (0:0:0:54h)
+ , 4,
+ GMFN, 1, // Gfx function 1 enable
+ , 27,
+ Offset(0x5C), // Mirror of Cunit's Base address of stolen DRAM memory for the GTT (0:0:0:5ch)
+ GSTM, 32, // Base address of stolen DRAM memory for the GTT
+
+ Offset(0xB0), // Gfx Clk Frequency and Gating Control
+ , 12,
+ CDVL, 1, // Core display clock value
+ , 3, // Graphics Core Display Clock Select
+
+ Offset(0xE4),
+ ASLE, 8, // Reg 0xE4, ASLE interrupt register
+ , 24, // Only use first byte of ASLE reg
+ Offset(0xE8), // Reg 0xE8, SWSCI control register
+ GSSE, 1, // Graphics SCI event (1=event pending)
+ GSSB, 14, // Graphics SCI scratchpad bits
+ GSES, 1, // SCI or SMI event select (1=SCI)
+ Offset(0xFC),
+ ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion
+}
+
+//
+// Define an OperationRegion to cover the IGD OpRegion layout.
+//
+
+OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)
+Field(IGDM, AnyAcc, NoLock, Preserve)
+{
+ //
+ // OpRegion Header
+ //
+ SIGN, 128, // Signature-"IntelGraphicsMem"
+ SIZE, 32, // OpRegion Size
+ OVER, 32, // OpRegion Version
+ SVER, 256, // System BIOS Version
+ VVER, 128, // VBIOS Version
+ GVER, 128, // Driver version
+ MBOX, 32, // Mailboxes supported
+ DMOD, 32, // Driver Model
+ PCON, 32, // Platform Configuration
+ DVER, 256, // GOP Version
+ //
+ // OpRegion Mailbox 1 (Public ACPI Methods)
+ // Note: Mailbox 1 is normally reserved for desktop platforms.
+ //
+
+ Offset(0x100),
+ DRDY, 32, // Driver readiness (ACPI notification)
+ CSTS, 32, // Notification status
+ CEVT, 32, // Current event
+ Offset(0x120),
+ DIDL, 32, // Supported display device ID list
+ DDL2, 32, // Allows for 8 devices
+ DDL3, 32,
+ DDL4, 32,
+ DDL5, 32,
+ DDL6, 32,
+ DDL7, 32,
+ DDL8, 32,
+ CPDL, 32, // Currently present display list
+ CPL2, 32, // Allows for 8 devices
+ CPL3, 32,
+ CPL4, 32,
+ CPL5, 32,
+ CPL6, 32,
+ CPL7, 32,
+ CPL8, 32,
+ CAD1, 32, // Currently active display list
+ CAL2, 32, // Allows for 8 devices
+ CAL3, 32,
+ CAL4, 32,
+ CAL5, 32,
+ CAL6, 32,
+ CAL7, 32,
+ CAL8, 32,
+ NADL, 32, // Next active display list
+ NDL2, 32, // Allows for 8 devices
+ NDL3, 32,
+ NDL4, 32,
+ NDL5, 32,
+ NDL6, 32,
+ NDL7, 32,
+ NDL8, 32,
+ ASLP, 32, // ASL sleep timeout
+ TIDX, 32, // Toggle table index
+ CHPD, 32, // Current hot plug enable indicator
+ CLID, 32, // Current lid state indicator
+ CDCK, 32, // Current docking state indicator
+ SXSW, 32, // Display switch notify on resume
+ EVTS, 32, // Events supported by ASL (diag only)
+ CNOT, 32, // Current OS notifications (diag only)
+ NRDY, 32,
+
+ //
+ //Extended DIDL list
+ //
+ DDL9, 32,
+ DD10, 32,
+ DD11, 32,
+ DD12, 32,
+ DD13, 32,
+ DD14, 32,
+ DD15, 32,
+
+ //
+ //Extended Currently attached Display Device List CPD2
+ //
+ CPL9, 32,
+ CP10, 32,
+ CP11, 32,
+ CP12, 32,
+ CP13, 32,
+ CP14, 32,
+ CP15, 32,
+
+ //
+ // OpRegion Mailbox 2 (Software SCI Interface)
+ //
+ Offset(0x200), // SCIC
+ SCIE, 1, // SCI entry bit (1=call unserviced)
+ GEFC, 4, // Entry function code
+ GXFC, 3, // Exit result
+ GESF, 8, // Entry/exit sub-function/parameter
+ , 16, // SCIC[31:16] reserved
+ Offset(0x204), // PARM
+ PARM, 32, // PARM register (extra parameters)
+ DSLP, 32, // Driver sleep time out
+
+ //
+ // OpRegion Mailbox 3 (BIOS to Driver Notification)
+ // Note: Mailbox 3 is normally reserved for desktop platforms.
+ //
+ Offset(0x300),
+ ARDY, 32, // Driver readiness (power conservation)
+ ASLC, 32, // ASLE interrupt command/status
+ TCHE, 32, // Technology enabled indicator
+ ALSI, 32, // Current ALS illuminance reading
+ BCLP, 32, // Backlight brightness
+ PFIT, 32, // Panel fitting state or request
+ CBLV, 32, // Current brightness level
+ BCLM, 320, // Backlight brightness level duty cycle mapping table
+ CPFM, 32, // Current panel fitting mode
+ EPFM, 32, // Enabled panel fitting modes
+ PLUT, 592, // Optional. 74-byte Panel LUT Table
+ PFMB, 32, // Optional. PWM Frequency and Minimum Brightness
+ CCDV, 32, // Optional. Gamma, Brightness, Contrast values.
+ PCFT, 32, // Optional. Power Conservation Features
+ SROT, 32, // Supported rotation angle.
+ IUER, 32, // Optional. Intel Ultrabook Event Register.
+ FDSP, 64, // Optional. FFS Display Physical address
+ FDSS, 32, // Optional. FFS Display Size
+ STAT, 32, // State Indicator
+
+ //
+ // OpRegion Mailbox 4 (VBT)
+ //
+ Offset(0x400),
+ GVD1, 0xC000, // 6K bytes maximum VBT image
+
+ //
+ // OpRegion Mailbox 5 (BIOS to Driver Notification Extension)
+ //
+ Offset(0x1C00),
+ PHED, 32, // Panel Header
+ BDDC, 2048, // Panel EDID (Max 256 bytes)
+}
+
+//
+// Convert boot display type into a port mask.
+//
+Name (DBTB, Package()
+{
+ 0x0000, // Automatic
+ 0x0007, // Port-0 : Integrated CRT
+ 0x0038, // Port-1 : DVO-A, or Integrated LVDS
+ 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C
+ 0x0E00, // Port-3 : SDVO-C
+ 0x003F, // [CRT + DVO-A / Integrated LVDS]
+ 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C]
+ 0x0E07, // [CRT + SDVO-C]
+ 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B]
+ 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C]
+ 0x0FC0, // [SDVO-B + SDVO-C]
+ 0x0000, // Reserved
+ 0x0000, // Reserved
+ 0x0000, // Reserved
+ 0x0000, // Reserved
+ 0x0000, // Reserved
+ 0x7000, // Port-4: Integrated TV
+ 0x7007, // [Integrated TV + CRT]
+ 0x7038, // [Integrated TV + LVDS]
+ 0x71C0, // [Integrated TV + DVOB]
+ 0x7E00 // [Integrated TV + DVOC]
+})
+
+//
+// Core display clock value table.
+//
+Name (CDCT, Package()
+{
+ Package() {160},
+ Package() {200},
+ Package() {267},
+ Package() {320},
+ Package() {356},
+ Package() {400},
+})
+
+//
+// Defined exit result values:
+//
+Name (SUCC, 1) // Exit result: Success
+Name (NVLD, 2) // Exit result: Invalid parameter
+Name (CRIT, 4) // Exit result: Critical failure
+Name (NCRT, 6) // Exit result: Non-critical failure
+
+Include("IgfxOpMobf.asl") // IGD SCI mobile features
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Ipu.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Ipu.asl new file mode 100644 index 0000000000..cdf83c75c6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Ipu.asl @@ -0,0 +1,90 @@ +/** @file
+ This file contains the device definition of the System Agent
+ ACPI reference code.
+ Currently defines the device objects for the
+ System Agent Camera IPU device.
+
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+External(\_SB.OSSL, IntObj)
+External(\_SB.IPUD, IntObj)
+
+//
+// Device IPU is the Bxt IPU device
+//
+
+//
+// Device IPU0 is the AVStream virtual device and it appears under _SB
+//
+
+Scope (\_SB) {
+ Device(IPU0)
+ {
+ Name (_HID, "INT34D7") // This is an the ACPI ID of AVStream device driver
+ /*
+ Allows OS to not yellow bang if Intel do not
+ provide driver for that OS version, otherwise
+ if we have driver for every OS, then no need
+ for _CID at all.
+ */
+ Name(_CID, EISAID("PNP0C02"))
+ /*
+ The following is a technique that may be used (per OEM needs) to prevent
+ the load of the camera device in one of the following cases:
+ - Camera device and the CIO2 device are fused out
+ - If the platform setup requires that in a secured boot the camera device
+ should not be enabled
+ */
+ Method (_STA, 0, NotSerialized) {
+ If (LAnd(LEqual(IPUD,2),And(OSSL,0))) { // ACPI need report IPU0 as available device for WOS
+ Return (0xF)
+ } Else { // ACPI should NOT report IPU0 as available device
+ Return (0x0)
+ }
+ }
+ }
+}
+
+//
+// Device IPU0 is the AVStream virtual device and it appears under GFX0
+//
+Scope (\_SB.PCI0.GFX0)
+{
+ Device(IPU0) // AVStream virtual device name
+ {
+ /*
+ The identifier for this device (Same as in
+ _DOD above). This is required so GFX driver can
+ associate a matching device ID for the AVStream
+ driver and provide it to PnP (this device ID
+ should appear in the INF file of the AVStream
+ driver).
+ */
+ Name(_ADR, 0x000034D7)
+ /*
+ The following is a technique that may be used (per OEM needs) to prevent
+ the load of the camera device in one of the following cases:
+ - Camera device and the CIO2 device are fused out
+ - If the platform setup requires that in a secured boot the camera device
+ should not be enabled
+ */
+ Method (_STA, 0, NotSerialized) {
+ If(LAnd(LEqual(IPUD,1),And(OSSL,0))) { // IGFX need report IPU0 as GFX0 child for WOS
+ Return (0xF)
+ } Else { // IGFX should NOT report IPU0 as GFX0 child
+ Return (0x0)
+ }
+ }
+ } // End IPU0
+} // end I.G.D
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Sa.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Sa.asl new file mode 100644 index 0000000000..ad8240264c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/Sa.asl @@ -0,0 +1,119 @@ +/** @file
+ Broxton SA configuration space definition.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+External(\_SB.PCI0, DeviceObj)
+
+External(PNSL)
+External(\_SB.PEPD, DeviceObj)
+
+Scope (\_SB.PCI0) {
+
+ Device(GFX0) { // Mobile I.G.D
+ Name(_ADR, 0x00020000)
+#if (ENBDT_PF_ENABLE == 1)
+ Name (_S0W, 3)
+
+ Method (_DEP, 0, NotSerialized) {
+ Return (Package() {\_SB.PEPD})
+ }
+
+
+ Name (CBUF, ResourceTemplate() {
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {37} // MIPI_DSI_RST_1_8V, GPIO_77 (NorthWest, 37)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {9} // PANEL1_VDDEN_1_8V_R, Used as GPIO_196 for MIPI (NorthWest, 6)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {10} // PANEL1_BKLTEN_1_8V_R, Used as GPIO_197 for MIPI (NorthWest, 7)
+ })
+
+ Name (DBUF, ResourceTemplate() {})//ed
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ If (LAnd (LNotEqual (PNSL, 0), LNotEqual (PNSL, 4))) {
+ Return (CBUF)
+ } Else {
+ Return (DBUF)
+ }
+ }
+#else
+
+ Name (_S0W, 3)
+
+ Method (_DEP, 0, NotSerialized) {
+ Return (Package() {\_SB.PCI0.PEPD})
+ }
+
+ Name (CBUF, ResourceTemplate() {
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO0", ) {27} // N27: DISP0_RST_N, GPIO_27 (North, 27)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO4", ) {6} // DISP0_VDDEN, Used as GPIO_193 for MIPI (South, 6)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO4", ) {7} // DISP0_BKLTEN, Used as GPIO_194 for MIPI (South, 7)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO4", ) {9} // DISP1_VDDEN, Used as GPIO_196 for MIPI (South, 9)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO4", ) {10} // DISP1_BKLTEN, Used as GPIO_197 for MIPI (South, 10)
+ // DISP0 I2C bus for Display backlight DC/DC LM3631 (0x29, 400k) on I2C BUS6 (1 based)
+ I2CSerialBus(0x29, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C6", //ResourceSource: I2C bus controller name
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ // DISP1 I2C bus for Display backlight DC/DC LM3631 (0x29, 400k) on I2C BUS4 (1 based) for FAB B/C
+ I2CSerialBus(0x29, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name
+ , //Descriptor Name: creates name for offset of resource descriptor
+ )
+ })
+
+ Name (DBUF, ResourceTemplate() {
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO0", ) {27} // N27: DISP0_RST_N, GPIO_27 (North, 27)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO4", ) {6} // DISP0_VDDEN, Used as GPIO_193 for MIPI (South, 6)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO4", ) {7} // DISP0_BKLTEN, Used as GPIO_194 for MIPI (South, 7)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO4", ) {9} // DISP1_VDDEN, Used as GPIO_196 for MIPI (South, 9)
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO4", ) {10} // DISP1_BKLTEN, Used as GPIO_197 for MIPI (South, 10)
+ // DISP0 I2C bus for Display backlight DC/DC LM3631 (0x29, 400k) on I2C BUS6 (1 based)
+ I2CSerialBus(0x29, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C6", //ResourceSource: I2C bus controller name
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ // DISP1 I2C bus for Display backlight DC/DC LM3631 (0x29, 400k) on I2C BUS5 (1 based) for FAB D
+ I2CSerialBus(0x29, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C5", //ResourceSource: I2C bus controller name
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ })
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ If (LAnd(LEqual(BDID, 0x00), LLess(BREV, 0x4)))
+ {
+ Return(CBUF) // This resource buffer is only exposed for RVP A/B/C
+ }
+ Return (DBUF) //Not FAB D
+ }
+#endif
+ include("Igfx.asl")
+ } // end "IGD Device"
+
+ include("Ipu.asl")
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/SaAcpiTables.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/SaAcpiTables.inf new file mode 100644 index 0000000000..e7aa05191d --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/SaAcpiTables.inf @@ -0,0 +1,58 @@ +## @file
+# Component description file for the ACPI tables.
+#
+# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SaAcpiTables
+ FILE_GUID = ca89914d-2317-452e-b245-36c6fb77a9c6
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ SaSsdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+
+[Protocols]
+
+[PPIs]
+
+[Guids]
+
+[Depex]
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/SaSsdt.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/SaSsdt.asl new file mode 100644 index 0000000000..81b6e9d8a6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/AcpiTables/SaSsdt.asl @@ -0,0 +1,28 @@ +/** @file
+ This file contains the SystemAgent SSDT Table ASL code.
+ It defines a Global NVS table which exchanges datas between OS and BIOS.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "SaSsdt.aml",
+ "SSDT",
+ 0x02,
+ "SaSsdt",
+ "SaSsdt ",
+ 0x3000
+ )
+{
+ include ("Sa.asl")
+}
+
|