diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-23 10:58:54 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:15:05 +0800 |
| commit | d254955360382276b857852962265b1ed9b63ae8 (patch) | |
| tree | 73505ff830df43c482f58838a03879c3ee078ca4 /Silicon | |
| parent | 94eafd1c86b1029bb489ab81f5d4048a54a56d34 (diff) | |
| download | edk2-platforms-d254955360382276b857852962265b1ed9b63ae8.tar.xz | |
BroxtonSiPkg: Add MemoryInit
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Silicon')
8 files changed, 1759 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h new file mode 100644 index 0000000000..e1342a07dd --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h @@ -0,0 +1,89 @@ +/** @file
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MRCEFIDEFINITIONS_H_
+#define _MRCEFIDEFINITIONS_H_
+
+#if defined(EFI_MEMORY_INIT) || defined(FSP_FLAG)
+#include <Ppi/DramPolicyPpi.h>
+#include <Library/SteppingLib.h>
+#define DRAM_POLICY DRAM_POLICY_PPI
+#else
+
+#include <Guiddef.h>
+#include "DataTypes.h"
+
+#define DRAM_POLICY_NUMBER_CHANNELS 4
+#define DRAM_POLICY_NUMBER_BITS 32
+#define DRAM_POLICY_NUMBER_SPD_ADDRESSES 2
+
+#pragma pack(push,1)
+
+typedef GUID EFI_GUID;
+
+typedef struct {
+ UINT8 RankEnable;
+ UINT8 DeviceWidth;
+ UINT8 DramDensity;
+ UINT8 Option;
+ UINT8 OdtConfig;
+ UINT8 TristateClk1;
+ UINT8 Mode2N;
+ UINT8 OdtLevels;
+} DRP_DRAM_POLICY;
+
+typedef struct {
+ UINT8 Package;
+ UINT8 Profile;
+ UINT8 MemoryDown;
+ UINT8 DDR3LPageSize;
+ UINT8 DDR3LASR;
+ EFI_PHYSICAL_ADDRESS MrcTrainingDataPtr;
+ EFI_PHYSICAL_ADDRESS MrcBootDataPtr;
+ UINT8 ScramblerSupport;
+ UINT16 ChannelHashMask;
+ UINT16 SliceHashMask;
+ UINT8 InterleavedMode;
+ UINT8 ChannelsSlicesEnabled; /// bit0 = SliceEnabled; bit1 = channelEnabled
+ UINT8 MinRefRate2xEnabled;
+ UINT8 DualRankSupportEnabled;
+ UINT16 SystemMemorySizeLimit;
+ UINT16 LowMemMaxVal;
+ UINT16 HighMemMaxVal;
+ UINT8 DisableFastBoot;
+ UINT8 RmtMode;
+ UINT8 RmtCheckRun;
+ UINT16 RmtMarginCheckScaleHighThreshold;
+ UINT32 MsgLevelMask;
+ UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];
+ UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
+ DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS];
+ UINT8 DebugMsgLevel;
+ UINT8 reserved[13];
+} DRAM_POLICY_PPI;
+
+#define DRAM_POLICY DRAM_POLICY_PPI
+
+#pragma pack(pop)
+
+typedef enum {
+ Bxt = 0x00,
+ Bxt1,
+ BxtX,
+ BxtP,
+ BxtSeriesMax = 0xFF
+} BXT_SERIES;
+
+#endif
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/MemoryInit.dec b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/MemoryInit.dec new file mode 100644 index 0000000000..64f9de5829 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/MemoryInit.dec @@ -0,0 +1,35 @@ +## @file
+# Package for cryptography modules.
+#
+# This Package provides cryptographic-related libraries for UEFI
+# security modules.
+#
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = MemoryInit
+ PACKAGE_GUID = 3282742A-3E7C-4699-AA70-AFE302C76630
+ PACKAGE_VERSION = 0.01
+
+[Guids]
+
+[Includes]
+ Mmrc/ProjectData/BXTP/Include
+ Mmrc/ProjectIndependent/Include
+ BXT/Include
+
+[LibraryClasses]
+
+[Protocols]
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitions.h new file mode 100644 index 0000000000..96f3d0935c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitions.h @@ -0,0 +1,33 @@ +/** @file
+ Includes all hard defines specific to a project which are NOT
+ outputted by the MMRC tool. Things like the maximum number of
+ channels, ranks, DIMMs, etc, should be included here. This file
+ needs to be included by most MMRC components, including Mmrc.h.
+
+ Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MMRCPROJECTDEFINITIONS_H
+#define _MMRCPROJECTDEFINITIONS_H
+
+#include "MmrcProjectDefinitionsGenerated.h"
+#include "MrcEfiDefinitions.h"
+
+
+//
+// RMT project specific definitions.
+//
+#define PSEUDO_RANKS 0 // PT changed from 2 to 0. Effectively disable it
+#define MAX_RMT_ELEMENTS 7 // PT changed from 10 to 7
+
+#endif // _MMRCPROJECTDEFINITIONS_H
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitionsGenerated.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitionsGenerated.h new file mode 100644 index 0000000000..b0b6a01376 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitionsGenerated.h @@ -0,0 +1,1050 @@ +/** @file
+ File name: MmrcProjectDefinitionsGenerated.h
+ Input File: BXTP_SOC.xlsx
+
+ THIS FILE IS AUTO-GENERATED BY THE MMRC TOOL. DO NOT CHANGE THIS CODE.
+
+ If edits are needed in this file, they must be done via the MMRC tool.
+
+ If there is additional project-specific data required by the MMRC, it
+ can be placed in MmrcProjectDefinitions.h, which is used for non-tool-generated
+ data
+
+ Includes all hard defines specific to a project. Things like
+ the maximum number of channels, ranks, DIMMs, etc, should be included
+ here. This file needs to be included by most MMRC components,
+ including Mmrc.h.
+
+ Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MMRCPROJECTDEFINITIONSGENERATED_H_
+#define _MMRCPROJECTDEFINITIONSGENERATED_H_
+
+
+
+//
+// Maximum number of blueprints
+//
+#define MAX_BLUEPRINTS 2
+
+//
+// Maximum number of Instances
+//
+#define MAX_INSTANCE_PORTS 50
+//
+
+//
+// This project contains 64 bit variables.
+//
+#define USE_64_BIT_VARIABLES 1
+//
+// Channels
+//
+#define MAX_CHANNELS 4
+//
+// DIMMS Per Channel
+//
+#define MAX_DIMMS 1
+//
+// Ranks Per Channel
+//
+#define MAX_RANKS 2
+
+//
+// Max Strobes Per Channel
+//
+#define MAX_STROBES 9
+//
+// Max Strobes Per Channel when ECC is disabled
+//
+#define MAX_STROBES_NON_ECC (MAX_STROBES-1)
+
+//
+// Max number of ranks for a single DIMM
+//
+#define MAX_RANKS_PER_DIMM 2
+
+//
+// Number of DQ per BL
+//
+#define MAX_BITS 8
+//
+// Command groups per channel.
+//
+#define MAX_CMDS 2
+//
+// Control Groups Per Channel.
+//
+#define MAX_CTLS 2
+//
+// Clock Groups Per Channel.
+//
+#define MAX_CLKS 2
+//
+// Major Version
+//
+#define VERSION_MAJOR 89
+//
+// Minor Version
+//
+#define VERSION_MINOR 0
+//
+// Print MRC functions as they execute
+//
+#define CAPSULESTRINGS 0
+//
+//
+//
+#define ERROR_MESSAGES 1
+//
+// Use CPGC for training
+//
+#define CPGC_API 1
+//
+// Lowest address bit for rank selection during training
+//
+#define RANK_SHIFT_BIT 25
+//
+// Debug message output to serial or console
+//
+#define DEBUG_MSG 1
+//
+// Enable training algorithms
+//
+#define TRAINING_ALGOS 1
+//
+// Number of Samples to take for Rcvn/FWL.
+//
+#define NUMSAMPLES 8
+//
+// Number of consecutive samples to pass for RCVN/FWL.
+//
+#define SAMPLETHRESH 5
+//
+// Dithering check for stability for RCVN/FWL.
+//
+#define DITHER 5
+//
+// Receive enable training
+//
+#define RECEIVE_ENABLE 1
+//
+// Number of 2x for LP3
+//
+#define RCVN_PREAMBLE_CNTR_LP3 1
+//
+// Number of 2x for LP4
+//
+#define RCVN_PREAMBLE_CNTR_LP4 2
+//
+// Number of 2x for DDR3
+//
+#define RCVN_PREAMBLE_CNTR_DDR3 1
+//
+// Number of ps for LP3
+//
+#define RCVN_PREAMBLE_OFFSET_LP3 0
+//
+// Number of ps for LP4
+//
+#define RCVN_PREAMBLE_OFFSET_LP4 0
+//
+// Number of ps for DDR3
+//
+#define RCVN_PREAMBLE_OFFSET_DDR3 0
+//
+// Starting point for the half clock during receive enable.
+//
+#define RCVN_INITIAL2XVAL_LP3 12
+//
+// Starting point for the half clock during receive enable.
+//
+#define RCVN_INITIAL2XVAL_LP4 13
+//
+// Starting point for the half clock during receive enable.
+//
+#define RCVN_INITIAL2XVAL_DDR3 14
+//
+// Enable Rank-2-Rank Training for LP3
+//
+#define RCVN_RANK2RANK_ON_LP3 0
+//
+// Enable Rank-2-Rank Training for LP4
+//
+#define RCVN_RANK2RANK_ON_LP4 0
+//
+// Enable Rank-2-Rank Training for DDR3
+//
+#define RCVN_RANK2RANK_ON_DDR3 0
+//
+// Large Step size as percentage of the Half Clock.
+//
+#define RCVN_LARGE_STEP 25
+//
+// Step size during second phase of receive enable
+//
+#define RCVN_MEDIUM_STEP 5
+//
+// Step size during final phase of receive enable
+//
+#define RCVN_SMALL_STEP 1
+//
+// Fine write leveling training
+//
+#define FINE_WRITE_LEVELING 1
+//
+// Enable Rank-2-Rank Training for LP3
+//
+#define FWL_RANK2RANK_ON_LP3 0
+//
+// Enable Rank-2-Rank Training for LP4
+//
+#define FWL_RANK2RANK_ON_LP4 0
+//
+// Large Step size as percentage of the Half Clock.
+//
+#define FWL_LARGE_STEP 25
+//
+// Step size during second phase of receive enable
+//
+#define FWL_MEDIUM_STEP 5
+//
+// Step size during final phase of receive enable
+//
+#define FWL_SMALL_STEP 1
+//
+// Coarse write leveling training
+//
+#define COARSE_WRITE_LEVELING 1
+//
+// Number of cks to push out DQS
+//
+#define CWL_CLK_PUSHOUT 3
+//
+// Step size for each DQ Testing (LP4)
+//
+#define CWL_DQ_STEP 5
+//
+// Early Command Training
+//
+#define EARLY_COMMAND_TRAINING 1
+//
+// Vref to perform ECT.
+//
+#define ECT_LP4_VREF 0x60
+//
+// Width and Height of the search matrix.
+//
+#define ECT_TILE_WIDTH 9
+//
+// Use CPGC or DRAM_CMD to enter CBT mode (LP3 Only CA-2N Mode)
+//
+#define ECT_ENTERCBT_CPGC 1
+//
+// Enable the pushout of the CCC flag
+//
+#define PUSHOUT_CCC 1
+//
+// Pushout by the number of 2x clcoks.
+//
+#define PUSHOUT_VALUE 2
+//
+// Early Read Training
+//
+#define EARLY_READ_TRAINING 1
+//
+// After finding final edge, amount of dithering to test.
+//
+#define ERT_DITHER 0
+//
+// Nominal RdVref for ERT training.
+//
+#define ERT_VREF_LPDDR4 0xA
+//
+// Nominal RdVref for ERT training.
+//
+#define ERT_VREF_LPDDR3 0x1f
+//
+// Nominal RdVref for ERT training.
+//
+#define ERT_VREF_DDR3 0x1f
+//
+// Larger step size to find edge.
+//
+#define ERT_LARGESTEP 10
+//
+// Medium step size to find edge.
+//
+#define ERT_MEDIUMSTEP 5
+//
+// Small step size to find edge.
+//
+#define ERT_SMALLSTEP 1
+//
+// Victim/aggressor read training
+//
+#define READ_TRAINING 1
+//
+// P/N Independent Training
+//
+#define RT_PN_ENABLED 1
+//
+// If no PBD set to 0xFF else use format RANK_SHARED|KNOB_SHARED | BIT_SHARED | BIT_CONTROL
+//
+#define RT_BIT_SHARING RANK_SHARED|KNOB_SHARED | BIT_CONTROL|CALCULATE_BIT
+//
+//
+//
+#define RT_BYTE_SHARING BIT_SHARED|KNOB_SHARED
+//
+//
+//
+#define RT_PERBIT_ENABLED 1
+//
+//
+//
+#define RT_NUM_EYEMASKS 2
+//
+//
+//
+#define RT_EYEMASK0_PI 15
+//
+//
+//
+#define MAX_POWER_KNOBS 1
+//
+//
+//
+#define RT_EYEMASK_VREF 3
+//
+//
+//
+#define RT_EYEMASK1_PI 15
+//
+//
+//
+#define RT_STEP1_VREFMIN 0
+//
+//
+//
+#define RT_STEP1_VREFMAX 63
+//
+//
+//
+#define RT_STEP1_VREFSTEP 2
+//
+//
+//
+#define RT_STEP1_VREFSTART_LP3 25
+//
+//
+//
+#define RT_STEP1_VREFSTART_LP4 0
+//
+//
+//
+#define RT_STEP1_VREFSTART_DDR3 25
+//
+//
+//
+#define RT_STEP1_3_PISTEPLARGE 1
+//
+//
+//
+#define RT_STEP1_3_PISTEPMEDIUM 0
+//
+//
+//
+#define RT_STEP1_3_PISTEPSMALL 0
+//
+//
+//
+#define RT_CTLE_MIN 0
+//
+//
+//
+#define RT_CTLE_MAX 0
+//
+//
+//
+#define RT_CTLE_STEP 2
+//
+//
+//
+#define RT_CTLE_ENABLE 0
+//
+//
+//
+#define RT_STEP2_VREFMIN 0
+//
+//
+//
+#define RT_STEP2_VREFMAX 63
+//
+//
+//
+#define RT_STEP2_VREFSTEP 5
+//
+//
+//
+#define RT_STEP3_VREFSAMPLES 3
+//
+// Pi/VREF center estimate weight
+//
+#define RT_STEP1_PICENTER_MINWEIGHT 2
+//
+//
+//
+#define RT_STEP1_PICENTER_MIDWEIGHT 3
+//
+//
+//
+#define RT_STEP1_PICENTER_MAXWEIGHT 5
+//
+//
+//
+#define RT_CTLE_SHARED RANK_SHARED|KNOB_SHARED | BIT_SHARED | BIT_CONTROL
+//
+//
+//
+#define RT_STEP2_PISAMPLES 3
+//
+// Advance Write Training
+//
+#define WRITE_TRAINING 1
+//
+//
+//
+#define WT_PERBIT_ENABLED 1
+//
+// 0xff
+//
+#define WT_BIT_SHARING RANK_SHARED|KNOB_SHARED | BIT_CONTROL
+//
+//
+//
+#define WT_BYTE_SHARING BIT_SHARED|KNOB_SHARED
+//
+//
+//
+#define WT_NUM_EYEMASKS 2
+//
+//
+//
+#define WT_EYEMASK0_PI 40
+//
+//
+//
+#define WT_EYEMASK_VREF 3
+//
+//
+//
+#define WT_EYEMASK1_PI 1
+//
+// No Vref Control
+//
+#define WT_STEP1_VREFMIN_DDR3 0
+//
+// Vref Control
+//
+#define WT_STEP1_VREFMIN_LP3 0
+//
+// 10th of percange of VDDQ; THESE ARE NOT USED
+//
+#define WT_STEP1_VREFMIN_LP4 100
+//
+// No Vref Control
+//
+#define WT_STEP1_VREFSTEP_DDR3 1
+//
+// Vref Control
+//
+#define WT_STEP1_VREFSTEP_LP3 2
+//
+// 10th of percange of VDDQ
+//
+#define WT_STEP1_VREFSTEP_LP4 8
+//
+// NO Vref Control
+//
+#define WT_STEP1_VREFMAX_DDR3 1
+//
+// Vref Control
+//
+#define WT_STEP1_VREFMAX_LP3 63
+//
+// 10th of percange of VDDQ; THESE ARE NOT USED
+//
+#define WT_STEP1_VREFMAX_LP4 420
+//
+// No Vref Control
+//
+#define WT_STEP1_VREFSTART_DDR3 0
+//
+// Vref Control
+//
+#define WT_STEP1_VREFSTART_LP3 0
+//
+// 10th of percange of VDDQ; THESE ARE NOT USED
+//
+#define WT_STEP1_VREFSTART_LP4 420
+//
+// 10th of percange of VDDQ
+//
+#define WT_STEP1_VREFSTEP 8
+//
+// 10th of percange of VDDQ; THESE ARE NOT USED
+//
+#define WT_STEP1_VREFMAX 420
+//
+// 10th of percange of VDDQ; THESE ARE NOT USED
+//
+#define WT_STEP1_VREFSTART 420
+//
+//
+//
+#define WT_STEP1_3_PISTEPLARGE 1
+//
+//
+//
+#define WT_STEP1_3_PISTEPMEDIUM 0
+//
+//
+//
+#define WT_STEP1_3_PISTEPSMALL 0
+//
+//
+//
+#define WT_STEP2_VREFMIN 400
+//
+//
+//
+#define WT_STEP2_VREFMAX 4
+//
+// No Vref Control
+//
+#define WT_STEP2_VREFSTEP_DDR3 1
+//
+// Vref Control
+//
+#define WT_STEP2_VREFSTEP_LP3 5
+//
+// Vref Control
+//
+#define WT_STEP2_VREFSTEP_LP4 421
+//
+//
+//
+#define WT_STEP3_VREFSAMPLES 3
+//
+//
+//
+#define WT_STEP1_PICENTER_MINWEIGHT 2
+//
+//
+//
+#define WT_STEP1_PICENTER_MIDWEIGHT 3
+//
+//
+//
+#define WT_STEP1_PICENTER_MAXWEIGHT 5
+//
+//
+//
+#define WT_VREFOVERRIDE_VALUE 37
+//
+//
+//
+#define WT_VREF_OVERRIDE_ENABLE 1
+//
+//
+//
+#define VDDQ 1100
+//
+//
+//
+#define LDO_TARGET 850
+//
+//
+//
+#define LDO_ENABLED 0
+//
+//
+//
+#define RON 35
+//
+//
+//
+#define ODT 999999
+//
+//
+//
+#define RTWT_SIM 0
+//
+//
+//
+#define PERIODIC_TRAINING 1
+//
+// Enable RMT Support
+//
+#define RMT 1
+//
+// OKAY to DELETE ** set to 0 on release code ** Peter put here just for sim purposes
+//
+#define RMT_WRITE_CHECKPOINT 0
+//
+// default RMT burst length
+//
+#define RMT_NUMBURSTS 13
+//
+// default RMT loop count
+//
+#define RMT_LOOPCOUNT 10
+//
+// Loopcount for production RMT test
+//
+#define RMT_PRODUCTION_LOOPCOUNT 7
+//
+// Numbursts for production RMT test
+//
+#define RMT_PRODUCTION_NUMBURSTS 7
+//
+// CPGC RMT Logging Enable
+//
+#define RMT_BIT_ERROR_LOGGING_ENABLE 0
+//
+// Loopcount for PPV RMT test
+//
+#define RMT_PPV_LOOPCOUNT 7
+//
+// Numbursts for PPV RMT test
+//
+#define RMT_PPV_NUMBURSTS 13
+//
+// Enable Per-Bit margin
+//
+#define RMT_PER_BIT_MARGIN 1
+//
+// max # of retries (w/JEDEC) if fail after RMT test
+//
+#define POST_RMT_RETRIES 5
+//
+// jump to other training postcode from RMT command loop
+//
+#define RMT_JUMP_POSTCODES 1
+//
+// Enable or disable support of the production RMT margin check
+//
+#define RMT_PRODUCTION_MODE_SUPPORT 1
+//
+// Late command training
+//
+#define COMMAND_TRAINING 1
+//
+// Test all memory at the end of MRC
+//
+#define MEMORY_TEST 0
+//
+// Initialize ECC at the end of MRC
+//
+#define ECC_SCRUB 0
+//
+// Display all DDRIO delays at the end of MRC
+//
+#define PHYVIEW_TABLE 1
+//
+// Display memory controller timings
+//
+#define TIMING_TABLE 1
+//
+// Display function calls
+//
+#define MRC_FLOW 0
+//
+// Enable BDAT table for publishing memory information in ACPI
+//
+#define BDAT 0
+//
+// Detect DIMMs via SPD reads
+//
+#define DETECT_DIMMS 0
+//
+// Enable PUNIT communication via mailbox
+//
+#define PUNIT_MAILBOX 0
+//
+// Use ODT input table from KIT team
+//
+#define ODT_TABLE 0
+//
+// Are minus 1 selects supported on this project?
+//
+#define TX_DQS_MINUS1_SUPPORT 0
+//
+// Are minus 1 selects supported on this project?
+//
+#define TX_DQ_MINUS1_SUPPORT 0
+//
+// Display register names with dumping
+//
+#define DUMP_REGISTER_NAMES 0
+//
+// Display register fields when dumping registers
+//
+#define DUMP_REGISTER_FIELDS 0
+//
+// Display all descriptions when dumping them
+//
+#define DUMP_REGISTER_DESCRIPTIONS 0
+//
+// Enable to use new receive enable and fine write leveling algos. These save code space.
+//
+#define SPACE_OPTIMIZED_ALGOS 1
+//
+// Min receive VREF
+//
+#define RX_VREF_MIN 0
+//
+// Max receive VREF
+//
+#define RX_VREF_MAX 30
+//
+// Receive VREF step
+//
+#define RX_VREF_STEP 3
+//
+// Min transmit VREF
+//
+#define TX_VREF_MIN 0
+//
+// Max transmit VREF
+//
+#define TX_VREF_MAX 63
+//
+// Transmit VREF step
+//
+#define TX_VREF_STEP 3
+//
+// Enable Stack size reduction by commented out unused variable
+//
+#define STACK_SIZE_REDUCE_EN 1
+//
+// Enable flag internal validation SV Hooks
+//
+#define MEM_SV_HOOKS 0
+//
+// Minimum allowable pulse width for RCVN and FWL in 1/16 clock increments. i.e. 4 = 1/4 clock.
+//
+#define MIN_PULSE_WIDTH 2
+//
+// When running Rd/Wr training, use per-bit algo.
+//
+#define NEW_RTWT_ALGO 1
+//
+//
+//
+#define CPGC_BASED_READWRITES 1
+//
+//
+//
+#define CPGC_BASED_WRITES 1
+//
+//
+//
+#define CPGC_BASED_READS 0
+//
+//
+//
+#define CPGC_BASE_EARLYREADS 0
+//
+//
+//
+#define EARLYMPR_1DSWEEP 1
+//
+//
+//
+#define RX_PI_MIN_WIDTH 20
+//
+//
+//
+#define LDO_TRAINING 0
+//
+//
+//
+#define CTLE_MIN 0
+//
+//
+//
+#define CTLE_MAX 3
+//
+//
+//
+#define CTLE_STEP 1
+//
+//
+//
+#define RT_VREF_MIN 0
+//
+//
+//
+#define RT_VREF_MAX 30
+//
+//
+//
+#define RT_VREF_STEP 3
+//
+//
+//
+#define NUM_CONS_MIN_EWS 3
+//
+//
+//
+#define NUM_FINAL_VREF_SAMPLES 7
+//
+//
+//
+#define RX_PI_MIN_EYEWIDTH 15
+//
+//
+//
+#define TX_PI_MIN_EYEWIDTH 15
+//
+// When doing VREF Sweep, starting value
+//
+#define RT_VREF_SWEEPMIN 0
+//
+//
+//
+#define RT_VREF_SWEEPMAX 30
+//
+//
+//
+#define RT_VREF_SWEEPSTEP 5
+//
+// Pi/VREF center estimate weight
+//
+#define MIN_WEIGHT 2
+//
+//
+//
+#define MID_WEIGHT 3
+//
+//
+//
+#define MAX_WEIGHT 5
+//
+// When doing VREF Sweep, starting value
+//
+#define WT_VREF_SWEEPMIN 0
+//
+//
+//
+#define WT_VREF_SWEEPMAX 30
+//
+//
+//
+#define WT_VREF_SWEEPSTEP 5
+//
+// When determing Vref Center, number of PI columns
+//
+#define MAX_PI_SAMPLES 3
+//
+// When determing Pi center, number Vref rows
+//
+#define NUM_CONS_VREFS 3
+//
+//
+//
+#define RX_PI_MIN 0
+//
+//
+//
+#define RX_PI_MAX 64
+//
+//
+//
+#define RX_PI_STEP 1
+//
+//
+//
+#define MAX_PI 63
+//
+//
+//
+#define RTWT_SIM 0
+//
+//
+//
+#define BXT_PO 0
+//
+// Tile Search Step Size
+//
+#define ECT_STEP_SIZE 5
+//
+// Tile Search Width
+//
+#define ECT_TSWIDTH 9
+//
+// Tile Search Shedding Percentage
+//
+#define ECT_TS_SHEDDING_PERCENT 50
+//
+// Tile Search Value Limit for each Loop (To prevent overflowing integers)
+//
+#define ECT_TS_VAL_LIMIT 255
+//
+//
+//
+#define RCVN_PREAM_CLK_SUBTRACT 3
+//
+//
+//
+#define VOC_TRAINING 1
+//
+//
+//
+#define VOC_LP4_VrefRMin_LDO_ENABLE 93
+//
+//
+//
+#define VOC_LP4_VrefRMax_LDO_ENABLE 429
+//
+// Voltage ; LDO on = LP4 only
+//
+#define VOC_LP4_VrefRMin_LDO_DISABLE 238
+//
+// Voltage ; LDO on = LP4 only
+//
+#define VOC_LP4_VrefRMax_LDO_DISABLE 742
+//
+// Voltage
+//
+#define VOC_LP3_VrefRMin 238
+//
+// Voltage
+//
+#define VOC_LP3_VrefRMax 742
+//
+// Voltage
+//
+#define VOC_DDR3L_VrefRMin 238
+//
+// Voltage
+//
+#define VOC_DDR3L_VrefRMax 742
+//
+//
+//
+#define VOC_Rext 105
+//
+//
+//
+#define VOC_VREF_MAX 63
+//
+//
+//
+#define VOC_VREF_STEP_SIZE 1
+//
+//
+//
+#define VOC_LP4_PullUpRon_LDO_ENABLE 140
+//
+//
+//
+#define VOC_LP4_PullDnRon_LDO_ENABLE 40
+//
+//
+//
+#define VOC_LP4_PullUpRon_LDO_DISABLE 140
+//
+//
+//
+#define VOC_LP4_PullDnRon_LDO_DISABLE 40
+//
+//
+//
+#define VOC_LP3_PullUpRon 40
+//
+//
+//
+#define VOC_LP3_PullDnRon 40
+//
+//
+//
+#define VOC_DDR3L_PullUpRon 40
+//
+//
+//
+#define VOC_DDR3L_PullDnRon 40
+//
+//
+//
+#define VOC_LP4_SegmentsEnabled_LDO_ENABLE 2
+//
+//
+//
+#define VOC_LP4_SegmentsEnabled_LDO_DISABLE 2
+//
+//
+//
+#define VOC_LP3_SegmentsEnabled 2
+//
+//
+//
+#define VOC_DDR3L_SegmentsEnabled 2
+//
+// Enable or disable debug messages related to Max PI setup.
+//
+#define MAXPIDLL_DEBUG_PRINT 0
+//
+//
+//
+#define RDCMD2RDVLD_TRAINING 1
+//
+// Does this DDRIO have an analog DLL?
+//
+#define ANALOG_DLL_SUPPORT_BLUEPRINT_LPDDR34 0
+//
+// Does this project have a digital DLL?
+//
+#define DIGITAL_DLL_SUPPORT_BLUEPRINT_LPDDR34 1
+//
+// Number of delay types which use clock crossings. Sometimes this is 1 in the case of only having a PI delay. Other projects have a coarse and a fine delay, so this would be 2.
+//
+#define NUM_CC_DEPENDENT_ELEMENTS_BLUEPRINT_LPDDR34 1
+//
+// Does this DDRIO have an analog DLL?
+//
+#define ANALOG_DLL_SUPPORT_BLUEPRINT_DDR3 0
+//
+// Does this project have a digital DLL?
+//
+#define DIGITAL_DLL_SUPPORT_BLUEPRINT_DDR3 1
+//
+// Number of delay types which use clock crossings. Sometimes this is 1 in the case of only having a PI delay. Other projects have a coarse and a fine delay, so this would be 2.
+//
+#define NUM_CC_DEPENDENT_ELEMENTS_BLUEPRINT_DDR3 1
+
+//
+// Max number of registers needed to be cached for the GetSet functions.
+//
+#define MAX_NUM_CACHE_ELEMENTS 50
+#define MAX_NUM_CACHE_ELEMENTS_PB 3
+
+//
+// Max number of delay types (i.e. receive enable, TX DQS, etc).
+//
+#define MAX_NUM_ALGOS 20
+
+#endif // _MMRCPROJECTDEFINITIONSGENERATED_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/Bind.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/Bind.h new file mode 100644 index 0000000000..b573c90160 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/Bind.h @@ -0,0 +1,151 @@ +/** @file
+ Data type definition for MRC.
+
+ Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BIND_H_
+#define _BIND_H_
+#pragma warning (disable : 4142 )
+
+#pragma pack()
+
+#if _MSC_EXTENSIONS
+
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft* tools
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning (disable : 4214 )
+
+//
+// Disabling warnings.
+//
+#pragma warning (disable : 4213)
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning (disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning (disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
+//
+#pragma warning (disable : 4127 )
+
+//
+// Int64ShllMod32 unreferenced inline function
+//
+#pragma warning (disable : 4514 )
+
+//
+// Unreferenced formal parameter - We are object oriented, so we pass This even
+// if we don't need them.
+//
+#pragma warning (disable : 4100 )
+
+#endif
+
+#if (__STDC_VERSION__ < 199901L)
+//
+// No ANSI C 2000 stdint.h integer width declarations, so define equivalents
+//
+#if _MSC_EXTENSIONS
+//
+// use Microsoft* C complier dependent interger width types
+//
+#if defined(EFI64) || defined(EFIx64)
+typedef unsigned __int64 uint64_t;
+typedef __int64 int64_t;
+#endif
+
+typedef unsigned long uint32_t;
+typedef long int32_t;
+typedef unsigned short uint16_t;
+typedef short int16_t;
+typedef unsigned char uint8_t;
+typedef char int8_t;
+#if SIM
+
+typedef unsigned int uint32_t;
+typedef int int32_t;
+typedef unsigned short uint16_t;
+typedef short int16_t;
+typedef unsigned char uint8_t;
+typedef char my_int8_t;
+#else
+//
+// Assume standard IA-32 alignment.
+// BugBug: Need to check portability of long long
+//
+// typedef unsigned long long uint64_t;
+// typedef long long int64_t;
+typedef unsigned int uint32_t;
+typedef int int32_t;
+typedef unsigned short uint16_t;
+typedef short int16_t;
+typedef unsigned char uint8_t;
+typedef char int8_t;
+#endif
+#else
+//
+// Linux
+//
+#if !defined SIM
+typedef unsigned int uint32_t;
+typedef int int32_t;
+typedef unsigned short uint16_t;
+typedef short int16_t;
+typedef unsigned char uint8_t;
+typedef char my_int8_t;
+typedef char int8_t;
+#endif
+#endif
+#else
+//
+// Use ANSI C 2000 stdint.h integer width declarations
+//
+#include "stdint.h"
+#endif
+
+#if SIM
+
+typedef unsigned int uint32_t;
+typedef int int32_t;
+typedef unsigned short uint16_t;
+typedef short int16_t;
+typedef unsigned char uint8_t;
+typedef char my_int8_t;
+#endif
+//
+// Native integer size in stdint.h
+//
+#if defined(EFI64) || defined(EFIx64)
+typedef int64_t intn_t;
+typedef uint64_t uintn_t;
+#else
+typedef uint32_t uintn_t;
+typedef int32_t intn_t;
+#endif
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/DataTypes.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/DataTypes.h new file mode 100644 index 0000000000..93ee6d2f11 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/DataTypes.h @@ -0,0 +1,129 @@ +/** @file
+ This file include all the external data types.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DATATYPES_H_
+#define _DATATYPES_H_
+
+#ifndef __GNUC__
+#pragma warning (disable : 4214 )
+#endif
+
+#ifndef EFI_MEMORY_INIT
+#include "Bind.h"
+typedef uint8_t BOOLEAN;
+#ifndef MRC_DATA_REQUIRED_FROM_OUTSIDE
+#ifndef UINTN
+typedef uintn_t UINTN;
+#endif
+#endif
+
+#ifndef size_t
+#define size_t UINT32
+#endif
+
+#if SIM
+typedef my_int8_t INT8;
+#else
+typedef int8_t INT8;
+#endif
+typedef uint8_t UINT8;
+typedef int16_t INT16;
+typedef uint16_t UINT16;
+#ifndef INT32
+typedef int INT32;
+#endif
+#ifndef UINT32
+typedef uint32_t UINT32;
+#endif
+typedef long long INT64;
+typedef unsigned long long UINT64;
+typedef uint8_t CHAR8;
+typedef uint16_t CHAR16;
+#ifndef EFI_PHYSICAL_ADDRESS
+typedef UINTN EFI_PHYSICAL_ADDRESS;
+#endif
+#ifndef GLOBAL_REMOVE_IF_UNREFERENCED
+ //
+ // The Microsoft* C compiler can removed references to unreferenced data items
+ // if the /OPT:REF linker option is used. We defined a macro as this is a
+ // a non standard extension
+ //
+ #if _MSC_EXTENSIONS
+ #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
+ #else
+ #define GLOBAL_REMOVE_IF_UNREFERENCED
+ #endif
+#endif
+#endif
+
+typedef struct {
+ UINT32 Index;
+ UINT32 DataHigh;
+ UINT32 DataLow;
+} MSR_REG;
+
+typedef struct {
+ INT8 x;
+ INT8 y;
+} TS_LOC;
+
+//
+// Modifiers to abstract standard types to aid in debug of problems
+//
+#ifndef CONST
+#define CONST const
+#endif
+
+#ifndef STATIC
+#define STATIC static
+#endif
+
+#ifndef VOID
+#define VOID void
+#endif
+
+#ifndef VOLATILE
+#define VOLATILE volatile
+#endif
+//
+// Constants. They may exist in other build structures, so #ifndef them.
+//
+#ifndef IN
+#define IN
+#endif
+
+#ifndef OUT
+#define OUT
+#endif
+
+#ifndef TRUE
+#define TRUE ((BOOLEAN) 1 == 1)
+#endif
+
+#ifndef FALSE
+#define FALSE ((BOOLEAN) 0 == 1)
+#endif
+
+#ifndef NULL
+#define NULL ((VOID *) 0)
+#endif
+
+typedef UINT32 MMRC_STATUS;
+#define MMRC_SUCCESS 0
+#define MMRC_DATA_DIRTY 0xFFFFFFFE
+#define MMRC_FAILURE 0xFFFFFFFF
+
+#endif // DATATYPES_H
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h new file mode 100644 index 0000000000..0a7672bbfe --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h @@ -0,0 +1,250 @@ +/** @file
+ Internal and external data structures, Macros, and enumerations.
+
+ Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MMRCDATA_H_
+#define _MMRCDATA_H_
+
+#include "Spd.h"
+#include "MmrcProjectDefinitions.h"
+
+#if SIM || JTAG
+#include <stdio.h>
+#endif
+
+#if USE_64_BIT_VARIABLES
+#define UINTX UINT64
+#else
+#define UINTX UINT32
+#endif
+
+typedef UINT32 MMRC_STATUS;
+
+//
+// MRC version description.
+//
+typedef union {
+ struct{
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+ } Version;
+ struct{
+ UINT32 Major : 4; ///< Major version number
+ UINT32 DevId : 3; ///< Field that can be used to identify dev that built test BIOS
+ UINT32 TestBuild : 1; ///< Flag that indicates that BIOS was built on a dev machine
+ UINT32 Minor : 8; ///< Minor version number
+ UINT32 Rev : 8; ///< Revision number
+ UINT32 Build : 8; ///< Build number
+ } Bits;
+ UINT32 Data;
+ UINT16 Data16[2];
+ UINT8 Data8[4];
+} MrcVersion;
+
+#ifndef ABSOLUTE
+#define ABSOLUTE 1
+#define RELATIVE 2
+#endif
+
+#pragma pack(push)
+#pragma pack(1)
+
+typedef enum {
+ BootFrequency,
+ HighFrequency,
+ MaxFrequencyIndex
+} FREQUENCY_INDEX;
+
+//
+// Bit definitions
+//
+#ifndef BIT0
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#endif
+
+typedef enum {
+ Pfct = 0,
+ PfctT,
+ PfctC,
+ PfctCT,
+ PfctF,
+ PfctFT,
+ PfctFC,
+ PfctFCT,
+ PfctP,
+ PfctPT,
+ PfctPC,
+ PfctPCT,
+ PfctPF,
+ PfctPFT,
+ PfctPFC,
+ PfctPFCT,
+ MaxPfct,
+} ENUM_PCFT_TYPE;
+
+typedef struct {
+ UINT8 SpdPresent;
+ UINT8 Buffer[MAX_SPD_ADDR + 1];
+} SPD_DATA;
+
+/**
+ Final training values stored on a per blueprint level. Needs to be per blueprint
+ in case of a system with more than 1 level of memory per channel.
+
+**/
+typedef struct {
+ UINT16 Values[MAX_BLUEPRINTS][MAX_NUM_ALGOS][MAX_RANKS][MAX_STROBES];
+} TRAINING_SETTING;
+
+typedef struct {
+ UINT8 ManuIDlo;
+ UINT8 ManuIDhi;
+ UINT8 ManuLoc;
+ UINT8 ManuDateLO;
+ UINT8 ManuDateHI;
+ UINT8 SerialNumber1;
+ UINT8 SerialNumber2;
+ UINT8 SerialNumber3;
+ UINT8 SerialNumber4;
+ UINT8 DimmCount;
+} FASTBOOTDATA;
+
+//
+// BOOT_VARIABLE_NV_DATA
+// Use this structure to store NV data that changes from boot to boot.
+//
+typedef struct {
+ UINT16 ScramblerSeed[MAX_CHANNELS];
+ UINT32 SaMemCfgCrc;
+ UINT32 MrcParamsSaveRestoreCrc;
+} BOOT_VARIABLE_NV_DATA;
+
+typedef struct {
+ TRAINING_SETTING Trained_Value;
+ BOOLEAN Enabled;
+ UINT32 TotalMem;
+ UINT8 DimmCount;
+ UINT8 DimmPresent[MAX_DIMMS];
+ UINT32 SlotMem[MAX_DIMMS];
+ SPD_DATA SpdData[MAX_DIMMS];
+ UINT8 D_Ranks[MAX_DIMMS];
+ UINT8 D_DataWidth[MAX_DIMMS];
+ UINT8 D_Banks[MAX_DIMMS];
+ UINT8 D_BusWidth[MAX_DIMMS];
+ UINT8 D_Size_SPD[MAX_DIMMS];
+ UINT8 D_Size[MAX_DIMMS];
+ UINT8 D_SizeActual[MAX_DIMMS];
+ UINT8 D_Type[MAX_DIMMS];
+ UINT16 DimmFrequency[MAX_DIMMS];
+ BOOLEAN RankEnabled[MAX_RANKS];
+ BOOLEAN EccEnabled;
+ UINT32 EccStrobes;
+ UINT8 MaxDq[MAX_RANKS];
+ FASTBOOTDATA FastBootData[MAX_DIMMS];
+ UINT16 DramType;
+ UINT16 CurrentPlatform;
+ UINT16 CurrentFrequency;
+ UINT16 CurrentConfiguration;
+ UINT16 CurrentDdrType;
+ BOOLEAN ExecuteOnThisChannel;
+ UINT16 TimingData[16];
+ INT16 RMT_Data[MAX_RANKS + PSEUDO_RANKS][MAX_RMT_ELEMENTS][2];
+#if RMT_PER_BIT_MARGIN
+ INT16 RMT_DQData[MAX_RANKS + PSEUDO_RANKS][MAX_RMT_ELEMENTS][MAX_BITS*MAX_STROBES][2];
+#endif
+ UINT8 Tcl;
+ UINT8 VrefSmbAddress;
+ UINT32 PtCtl0;
+ UINT8 Dimm2DunitMapping[MAX_STROBES*8];
+ UINT8 Dimm2DunitReverseMapping[MAX_STROBES*8];
+#if SIM && DDR4_SUPPORT
+ UINT16 TbMr5;
+#endif
+#if FAULTY_PART_TRACKING
+ FAULTY_PART FaultyPart[MAX_RANKS];
+#endif
+ UINT32 WrVref[MAX_RANKS][MAX_STROBES];
+ UINT32 CaVref[MAX_RANKS];
+ UINT32 Storage[18];
+ UINT8 ASR_Supported;
+ UINT8 OdtHigh;
+ UINT16 LP4_MR0VALUE;
+ UINT16 LP4_MR4VALUE;
+} CHANNEL;
+
+typedef struct {
+ UINT32 Signature;
+ UINT16 CurrentFrequency;
+ UINT8 DVFSFreqIndex;
+ UINT16 DDR3L_MRVALUE;
+ UINT8 DDR3L_PageSize;
+ UINT32 SystemMemorySize;
+ UINT32 MrcVer;
+ UINT32 CachedValues[MAX_CHANNELS][MAX_NUM_CACHE_ELEMENTS][MAX_RANKS][MAX_STROBES];
+ UINT32 CachedValuesPB[MAX_CHANNELS][MAX_NUM_CACHE_ELEMENTS_PB][MAX_RANKS][MAX_STROBES][MAX_BITS];
+ UINT8 BusWidth;
+ CHANNEL Channel[MAX_CHANNELS];
+ UINT32 MarginCheckResultState;
+ DRAM_POLICY DramPolicyData;
+ UINT32 MuxcodeNv[MaxFrequencyIndex];
+ BOOLEAN SetupMaxPiDone[MaxFrequencyIndex];
+ UINT32 DataSize;
+} MRC_PARAMS_SAVE_RESTORE;
+
+//
+// Structure for all data that is saved to NV RAM
+// and restored on the subsequent boots
+//
+typedef struct {
+ MRC_PARAMS_SAVE_RESTORE MrcParamsSaveRestore;
+ BOOT_VARIABLE_NV_DATA BootVariableNvData;
+} MRC_NV_DATA_FRAME;
+
+#pragma pack()
+#pragma pack(pop)
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/Spd.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/Spd.h new file mode 100644 index 0000000000..828cb54315 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/Spd.h @@ -0,0 +1,22 @@ +/** @file
+ This file include all the spd data defination.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SPD_H_
+#define _SPD_H_
+
+#define MAX_SPD_ADDR 125//512 // SPD Index of highest byte used by this reference code
+
+#endif
+
|