diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-22 19:16:03 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:15:02 +0800 |
| commit | f0a77159beb39438f311993bf6cd4136aa7e02fc (patch) | |
| tree | ddcbe7a11aa068901bb91c751278e751d8da4092 /Silicon | |
| parent | 92b6719423f351e9cf5517a9413f63da57778136 (diff) | |
| download | edk2-platforms-f0a77159beb39438f311993bf6cd4136aa7e02fc.tar.xz | |
BroxtonSiPkg: Add Include
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Silicon')
35 files changed, 4579 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/ConfigBlock.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/ConfigBlock.h new file mode 100644 index 0000000000..286d4c8116 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/ConfigBlock.h @@ -0,0 +1,59 @@ +/** @file
+ Header file for Config Block Lib implementation.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include <Uefi/UefiBaseType.h>
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_GUID Guid; ///< Offset 0-15 GUID of the config block
+/** Offset 16-19
+ Total length of this config block structure or size of config block table
+ if used in table header
+**/
+ UINT32 Size;
+ UINT8 Revision; ///< Offset 20 The main revision for config block
+ UINT8 Reserved[3]; ///< Offset 21-23 Reserved for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Header of config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 GUID number for main entry of config block
+ UINT16 NumberOfBlocks; ///< Offset 24-25 Number of config blocks (N)
+ UINT16 AvailableBlocks; ///< Offset 26-27 Current number of available config blocks
+ UINT32 AvailableSize; ///< Offset 28-31 Current config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+
+#endif // _CONFIG_BLOCK_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/CseVariableStoragePpiInstanceGuid.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/CseVariableStoragePpiInstanceGuid.h new file mode 100644 index 0000000000..850a4a0a80 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/CseVariableStoragePpiInstanceGuid.h @@ -0,0 +1,22 @@ +/** @file
+ GUID for the CSE Variable Storage PPI instance.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CSE_VARIABLE_STORAGE_PPI_INSTANCE_GUID_H_
+#define _CSE_VARIABLE_STORAGE_PPI_INSTANCE_GUID_H_
+
+extern EFI_GUID gCseVariableStoragePpiInstanceGuid;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/CseVariableStorageProtocolInstanceGuid.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/CseVariableStorageProtocolInstanceGuid.h new file mode 100644 index 0000000000..81586c153d --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/CseVariableStorageProtocolInstanceGuid.h @@ -0,0 +1,22 @@ +/** @file
+ GUID for the CSE Variable Storage Protocol instance.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CSE_VARIABLE_STORAGE_PROTOCOL_INSTANCE_GUID_H_
+#define _CSE_VARIABLE_STORAGE_PROTOCOL_INSTANCE_GUID_H_
+
+extern EFI_GUID gCseVariableStorageProtocolInstanceGuid;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/PeiVariableCacheHobGuid.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/PeiVariableCacheHobGuid.h new file mode 100644 index 0000000000..470d571898 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/PeiVariableCacheHobGuid.h @@ -0,0 +1,22 @@ +/** @file
+ GUID for the the Variable Cache HOB.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_VARIABLE_CACHE_HOB_GUID_H_
+#define _PEI_VARIABLE_CACHE_HOB_GUID_H_
+
+extern EFI_GUID gPeiVariableCacheHobGuid;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/PreMemoryVariableLocationHobGuid.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/PreMemoryVariableLocationHobGuid.h new file mode 100644 index 0000000000..e00eff308a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/PreMemoryVariableLocationHobGuid.h @@ -0,0 +1,27 @@ +/** @file
+ GUID for the the Pre-Memory Location HOB.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PRE_MEMORY_VARIABLE_LOCATION_HOB_GUID_H_
+#define _PRE_MEMORY_VARIABLE_LOCATION_HOB_GUID_H_
+
+extern EFI_GUID gPreMemoryVariableLocationHobGuid;
+
+typedef struct {
+ VOID *VariableDataPtr;
+ UINT32 VariableDataSize;
+} PRE_MEMORY_VARIABLE_LOCATION_HOB;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/SpiVariableStoragePpiInstanceGuid.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/SpiVariableStoragePpiInstanceGuid.h new file mode 100644 index 0000000000..5947b6e1e5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/SpiVariableStoragePpiInstanceGuid.h @@ -0,0 +1,22 @@ +/** @file
+ GUID for the SPI Variable Storage PPI instance.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SPI_VARIABLE_STORAGE_PPI_INSTANCE_GUID_H_
+#define _SPI_VARIABLE_STORAGE_PPI_INSTANCE_GUID_H_
+
+extern EFI_GUID gSpiVariableStoragePpiInstanceGuid;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/SpiVariableStorageProtocolInstanceGuid.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/SpiVariableStorageProtocolInstanceGuid.h new file mode 100644 index 0000000000..2af1c44054 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Guid/SpiVariableStorageProtocolInstanceGuid.h @@ -0,0 +1,22 @@ +/** @file
+ GUID for the SPI Variable Storage Protocol instance.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SPI_VARIABLE_STORAGE_PROTOCOL_INSTANCE_GUID_H_
+#define _SPI_VARIABLE_STORAGE_PROTOCOL_INSTANCE_GUID_H_
+
+extern EFI_GUID gSpiVariableStorageProtocolInstanceGuid;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/AslUpdateLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/AslUpdateLib.h new file mode 100644 index 0000000000..70697efeeb --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/AslUpdateLib.h @@ -0,0 +1,150 @@ +/** @file
+ ASL dynamic update library definitions.
+ This library provides dymanic update to various ASL structures.
+ There may be different libraries for different environments (PEI, BS, RT, SMM).
+ Make sure you meet the requirements for the library (protocol dependencies, use
+ restrictions, etc).
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ASL_UPDATE_LIB_H_
+#define _ASL_UPDATE_LIB_H_
+
+//
+// Include files
+//
+#include <IndustryStandard/Acpi.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/AcpiSupport.h>
+
+//
+// AML parsing definitions
+//
+#define AML_RESRC_TEMP_END_TAG 0x0079
+
+//
+// ASL PSS package structure layout
+//
+#pragma pack (1)
+
+typedef struct {
+ UINT8 NameOp; /// 12h ;First opcode is a NameOp.
+ UINT8 PackageLead; /// 20h ;First opcode is a NameOp.
+ UINT8 NumEntries; /// 06h ;First opcode is a NameOp.
+ UINT8 DwordPrefix1; /// 0Ch
+ UINT32 CoreFrequency; /// 00h
+ UINT8 DwordPrefix2; /// 0Ch
+ UINT32 Power; /// 00h
+ UINT8 DwordPrefix3; /// 0Ch
+ UINT32 TransLatency; /// 00h
+ UINT8 DwordPrefix4; /// 0Ch
+ UINT32 BMLatency; /// 00h
+ UINT8 DwordPrefix5; /// 0Ch
+ UINT32 Control; /// 00h
+ UINT8 DwordPrefix6; /// 0Ch
+ UINT32 Status; /// 00h
+} PSS_PACKAGE_LAYOUT;
+
+#pragma pack()
+
+/**
+ Initialize the ASL update library state.
+ This must be called prior to invoking other library functions.
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+InitializeAslUpdateLib (
+ VOID
+ );
+
+/**
+ This procedure will update immediate value assigned to a Name
+
+ @param[in] AslSignature The signature of Operation Region that we want to update.
+ @param[in] Buffer Source of data to be written over original aml
+ @param[in] Length Length of data to be overwritten
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+UpdateNameAslCode(
+ IN UINT32 AslSignature,
+ IN VOID *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ This function uses the ACPI support protocol to locate an ACPI table using the .
+ It is really only useful for finding tables that only have a single instance,
+ e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc.
+ Matches are determined by finding the table with ACPI table that has
+ a matching signature and version.
+
+ @param[in] Signature Pointer to an ASCII string containing the Signature to match
+ @param[in, out] Table Updated with a pointer to the table
+ @param[in, out] Handle AcpiSupport protocol table handle for the table found
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+LocateAcpiTableBySignature (
+ IN UINT32 Signature,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ );
+
+/**
+ This function uses the ACPI support protocol to locate an ACPI SSDT table.
+ The table is located by searching for a matching OEM Table ID field.
+ Partial match searches are supported via the TableIdSize parameter.
+
+ @param[in] TableId Pointer to an ASCII string containing the OEM Table ID from the ACPI table header
+ @param[in] TableIdSize Length of the TableId to match. Table ID are 8 bytes long, this function
+ will consider it a match if the first TableIdSize bytes match
+ @param[in, out] Table Updated with a pointer to the table
+ @param[in, out] Handle AcpiSupport protocol table handle for the table found
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+LocateAcpiTableByOemTableId (
+ IN UINT8 *TableId,
+ IN UINT8 TableIdSize,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ );
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param[in] Buffer Pointer to buffer to checksum
+ @param[in] Size Number of bytes to checksum
+ @param[in] ChecksumOffset Offset to place the checksum result in
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+AcpiChecksum (
+ IN VOID *Buffer,
+ IN UINTN Size,
+ IN UINTN ChecksumOffset
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/BxtMGpioLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/BxtMGpioLib.h new file mode 100644 index 0000000000..7c521ba171 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/BxtMGpioLib.h @@ -0,0 +1,291 @@ +/** @file
+ This library provides the BxtM GPIO library definitions.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BXTP_GPIOLIB_H_
+#define _BXTP_GPIOLIB_H_
+
+#define GPIO_PADBAR 0x400
+
+#define GPIO_NORTH_COMMUNITY_LENGTH 0x698
+#define GPIO_NORTHWEST_COMMUNITY_LENGTH 0x640
+#define GPIO_WEST_COMMUNITY_LENGTH 0x550
+#define GPIO_SOUTHWEST_COMMUNITY_LENGTH 0x4F8
+#define GPIO_SOUTH_COMMUNITY_LENGTH 0x4A0
+
+// GPIO pad and offset definition as GPIO HAS
+// North community GPIO pad definition
+#define N_GPIO_0 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0400
+#define N_GPIO_1 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0408
+#define N_GPIO_2 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0410
+#define N_GPIO_3 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0418
+#define N_GPIO_4 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0420
+#define N_GPIO_5 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0428
+#define N_GPIO_6 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0430
+#define N_GPIO_7 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0438
+#define N_GPIO_8 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0440
+#define N_GPIO_9 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0448
+#define N_GPIO_10 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0450
+#define N_GPIO_11 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0458
+#define N_GPIO_12 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0460
+#define N_GPIO_13 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0468
+#define N_GPIO_14 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0470
+#define N_GPIO_15 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0478
+#define N_GPIO_16 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0480
+#define N_GPIO_17 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0488
+#define N_GPIO_18 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0490
+#define N_GPIO_19 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0498
+#define N_GPIO_20 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04A0
+#define N_GPIO_21 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04A8
+#define N_GPIO_22 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04B0
+#define N_GPIO_23 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04B8
+#define N_GPIO_24 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04C0
+#define N_GPIO_25 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04C8
+#define N_GPIO_26 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04D0
+#define N_GPIO_27 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04D8
+#define N_GPIO_28 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04E0
+#define N_GPIO_29 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04E8
+#define N_GPIO_30 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04F0
+#define N_GPIO_31 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x04F8
+#define N_GPIO_32 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0500
+#define N_GPIO_33 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0508
+#define N_GPIO_34 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0510
+#define N_GPIO_35 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0518
+#define N_GPIO_36 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0520
+#define N_GPIO_37 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0528
+#define N_GPIO_38 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0530
+#define N_GPIO_39 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0538
+#define N_GPIO_40 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0540
+#define N_GPIO_41 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0548
+#define N_GPIO_42 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0550
+#define N_GPIO_43 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0558
+#define N_GPIO_44 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0560
+#define N_GPIO_45 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0568
+#define N_GPIO_46 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0570
+#define N_GPIO_47 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0578
+#define N_GPIO_48 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0580
+#define N_GPIO_49 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0588
+#define N_GPIO_50 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0590
+#define N_GPIO_51 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0598
+#define N_GPIO_52 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05A0
+#define N_GPIO_53 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05A8
+#define N_GPIO_54 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05B0
+#define N_GPIO_55 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05B8
+#define N_GPIO_56 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05C0
+#define N_GPIO_57 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05C8
+#define N_GPIO_58 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05D0
+#define N_GPIO_59 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05D8
+#define N_GPIO_60 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05E0
+#define N_GPIO_61 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05E8
+#define N_GPIO_62 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05F0
+#define N_GPIO_63 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x05F8
+#define N_GPIO_64 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0600
+#define N_GPIO_65 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0608
+#define N_GPIO_66 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0610
+#define N_GPIO_67 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0618
+#define N_GPIO_68 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0620
+#define N_GPIO_69 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0628
+#define N_GPIO_70 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0630
+#define N_GPIO_71 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0638
+#define N_GPIO_72 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0640
+#define N_GPIO_73 (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0648
+#define N_TCK (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0650
+#define N_TRST_B (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0658
+#define N_TMS (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0660
+#define N_TDI (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0668
+#define N_CX_PMODE (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0670
+#define N_CX_PREQ_B (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0678
+#define N_JTAGX (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0680
+#define N_CX_PRDY_B (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0688
+#define N_TDO (((UINT32)GPIO_NORTH_COMMUNITY)<<16)+0x0690
+
+// Northwest community GPIO pad definition
+#define NW_PMC_SPI_FS0 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0400
+#define NW_PMC_SPI_FS1 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0408
+#define NW_PMC_SPI_FS2 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0410
+#define NW_PMC_SPI_RXD (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0418
+#define NW_PMC_SPI_TXD (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0420
+#define NW_PMC_SPI_CLK (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0428
+#define NW_PMC_UART_RXD (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0430
+#define NW_PMC_UART_TXD (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0438
+#define NW_PMIC_PWRGOOD (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0440
+#define NW_PMIC_RESET_B (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0448
+#define NW_RTC_CLK (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0450
+#define NW_PMIC_SDWN_B (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0458
+#define NW_PMIC_BCUDISW2 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0460
+#define NW_PMIC_BCUDISCRIT (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0468
+#define NW_PMIC_THERMTRIP_B (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0470
+#define NW_PMIC_STDBY (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0478
+#define NW_SVID0_ALERT_B (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0480
+#define NW_SVID0_DATA (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0488
+#define NW_SVID0_CLK (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0490
+#define NW_PMIC_I2C_SCL (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0498
+#define NW_PMIC_I2C_SDA (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04a0
+#define NW_GPIO_74 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04a8
+#define NW_GPIO_75 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04b0
+#define NW_GPIO_76 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04b8
+#define NW_GPIO_77 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04c0
+#define NW_GPIO_78 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04c8
+#define NW_GPIO_79 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04d0
+#define NW_GPIO_80 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04d8
+#define NW_GPIO_81 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04e0
+#define NW_GPIO_82 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04e8
+#define NW_GPIO_83 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04f0
+#define NW_GPIO_84 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x04f8
+#define NW_GPIO_85 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0500
+#define NW_GPIO_86 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0508
+#define NW_GPIO_87 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0510
+#define NW_GPIO_88 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0518
+#define NW_GPIO_89 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0520
+#define NW_GPIO_90 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0528
+#define NW_GPIO_91 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0530
+#define NW_GPIO_92 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0538
+#define NW_GPIO_93 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0540
+#define NW_GPIO_94 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0548
+#define NW_GPIO_95 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0550
+#define NW_GPIO_96 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0558
+#define NW_PROCHOT_B (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0560
+#define NW_GPIO_97 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0568
+#define NW_GPIO_98 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0570
+#define NW_GPIO_99 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0578
+#define NW_GPIO_100 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0580
+#define NW_GPIO_101 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0588
+#define NW_GPIO_102 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0590
+#define NW_GPIO_103 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0598
+#define NW_FST_SPI_CLK_FB (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05a0
+#define NW_GPIO_104 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05a8
+#define NW_GPIO_105 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05b0
+#define NW_GPIO_106 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05b8
+#define NW_GPIO_107 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05c0
+#define NW_GPIO_109 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05c8
+#define NW_GPIO_110 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05d0
+#define NW_GPIO_111 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05d8
+#define NW_GPIO_112 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05e0
+#define NW_GPIO_113 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05e8
+#define NW_GPIO_114 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05f0
+#define NW_GPIO_115 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x05f8
+#define NW_GPIO_116 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0600
+#define NW_GPIO_117 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0608
+#define NW_GPIO_118 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0610
+#define NW_GPIO_119 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0618
+#define NW_GPIO_120 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0620
+#define NW_GPIO_121 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0628
+#define NW_GPIO_122 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0630
+#define NW_GPIO_123 (((UINT32)GPIO_NORTHWEST_COMMUNITY)<<16)+0x0638
+
+// West community GPIO pad definition
+#define W_GPIO_124 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0400
+#define W_GPIO_125 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0408
+#define W_GPIO_126 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0410
+#define W_GPIO_127 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0418
+#define W_GPIO_128 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0420
+#define W_GPIO_129 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0428
+#define W_GPIO_130 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0430
+#define W_GPIO_131 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0438
+#define W_GPIO_132 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0440
+#define W_GPIO_133 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0448
+#define W_GPIO_134 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0450
+#define W_GPIO_135 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0458
+#define W_GPIO_136 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0460
+#define W_GPIO_137 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0468
+#define W_GPIO_138 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0470
+#define W_GPIO_139 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0478
+#define W_GPIO_140 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0480
+#define W_GPIO_141 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0488
+#define W_GPIO_142 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0490
+#define W_GPIO_143 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0498
+#define W_GPIO_144 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04a0
+#define W_GPIO_145 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04a8
+#define W_GPIO_146 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04b0
+#define W_GPIO_147 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04b8
+#define W_GPIO_148 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04c0
+#define W_GPIO_149 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04c8
+#define W_GPIO_150 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04d0
+#define W_GPIO_151 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04d8
+#define W_GPIO_152 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04e0
+#define W_GPIO_153 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04e8
+#define W_GPIO_154 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04f0
+#define W_GPIO_155 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x04f8
+#define W_MODEM_CLKREQ (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0500
+#define W_DGCLKDBG_PMC_0 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0508
+#define W_DGCLKDBG_PMC_1 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0510
+#define W_DGCLKDBG_PMC_2 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0518
+#define W_DGCLKDBG_ICLK_0 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0520
+#define W_DGCLKDBG_ICLK_1 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0528
+#define W_OSC_CLK_OUT_0 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0530
+#define W_OSC_CLK_OUT_1 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0538
+#define W_OSC_CLK_OUT_2 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0540
+#define W_OSC_CLK_OUT_3 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0548
+#define W_GPIO_209 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0550
+#define W_GPIO_210 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0558
+#define W_GPIO_211 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0560
+#define W_GPIO_212 (((UINT32)GPIO_WEST_COMMUNITY)<<16)+0x0568
+
+// Southwest community GPIO pad definition
+#define SW_GPIO_156 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0400
+#define SW_GPIO_157 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0408
+#define SW_GPIO_158 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0410
+#define SW_GPIO_159 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0418
+#define SW_GPIO_160 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0420
+#define SW_GPIO_161 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0428
+#define SW_GPIO_162 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0430
+#define SW_GPIO_163 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0438
+#define SW_GPIO_164 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0440
+#define SW_GPIO_165 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0448
+#define SW_GPIO_166 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0450
+#define SW_GPIO_167 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0458
+#define SW_GPIO_168 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0460
+#define SW_GPIO_169 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0468
+#define SW_GPIO_170 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0470
+#define SW_GPIO_171 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0478
+#define SW_GPIO_172 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0480
+#define SW_GPIO_173 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0488
+#define SW_GPIO_174 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0490
+#define SW_GPIO_175 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x0498
+#define SW_GPIO_176 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04a0
+#define SW_GPIO_177 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04a8
+#define SW_GPIO_178 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04b0
+#define SW_GPIO_179 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04b8
+#define SW_GPIO_180 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04c0
+#define SW_GPIO_181 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04c8
+#define SW_GPIO_182 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04d0
+#define SW_GPIO_183 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04d8
+#define SW_GPIO_184 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04e0
+#define SW_GPIO_185 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04e8
+#define SW_GPIO_186 (((UINT32)GPIO_SOUTHWEST_COMMUNITY)<<16)+0x04f0
+
+// South community GPIO pad definition
+#define S_GPIO_187 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0400
+#define S_GPIO_188 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0408
+#define S_GPIO_189 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0410
+#define S_GPIO_190 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0418
+#define S_GPIO_191 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0420
+#define S_GPIO_192 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0428
+#define S_GPIO_193 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0430
+#define S_GPIO_194 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0438
+#define S_GPIO_195 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0440
+#define S_GPIO_196 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0448
+#define S_GPIO_197 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0450
+#define S_GPIO_198 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0458
+#define S_GPIO_199 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0460
+#define S_GPIO_200 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0468
+#define S_GPIO_201 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0470
+#define S_GPIO_202 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0478
+#define S_GPIO_203 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0480
+#define S_GPIO_204 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0488
+#define S_GPIO_205 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0490
+#define S_GPIO_206 (((UINT32)GPIO_SOUTH_COMMUNITY)<<16)+0x0498
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/BxtPGpioLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/BxtPGpioLib.h new file mode 100644 index 0000000000..26790ed616 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/BxtPGpioLib.h @@ -0,0 +1,281 @@ +/** @file
+ This library provides the BxtP GPIO library definitions.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BXTP_GPIOLIB_H_
+#define _BXTP_GPIOLIB_H_
+
+#define GPIO_PADBAR 0x500
+
+#define GPIO_NORTH_COMMUNITY_LENGTH 0x76C
+#define GPIO_NORTHWEST_COMMUNITY_LENGTH 0x764
+#define GPIO_WEST_COMMUNITY_LENGTH 0x674
+#define GPIO_SOUTHWEST_COMMUNITY_LENGTH 0x654
+
+// GPIO pad and offset definition as GPIO HAS
+// North community GPIO pad definition
+#define N_GPIO_0 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0000 //GPIO_0
+#define N_GPIO_1 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0008 //GPIO_1
+#define N_GPIO_2 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0010 //GPIO_2
+#define N_GPIO_3 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0018 //GPIO_3
+#define N_GPIO_4 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0020 //GPIO_4
+#define N_GPIO_5 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0028 //GPIO_5
+#define N_GPIO_6 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0030 //GPIO_6
+#define N_GPIO_7 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0038 //GPIO_7
+#define N_GPIO_8 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0040 //GPIO_8
+#define N_GPIO_9 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0048 //GPIO_9
+#define N_GPIO_10 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0050 //GPIO_10
+#define N_GPIO_11 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0058 //GPIO_11
+#define N_GPIO_12 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0060 //GPIO_12
+#define N_GPIO_13 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0068 //GPIO_13
+#define N_GPIO_14 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0070 //GPIO_14
+#define N_GPIO_15 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0078 //GPIO_15
+#define N_GPIO_16 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0080 //GPIO_16
+#define N_GPIO_17 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0088 //GPIO_17
+#define N_GPIO_18 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0090 //GPIO_18
+#define N_GPIO_19 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0098 //GPIO_19
+#define N_GPIO_20 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00A0 //GPIO_20
+#define N_GPIO_21 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00A8 //GPIO_21
+#define N_GPIO_22 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00B0 //GPIO_22
+#define N_GPIO_23 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00B8 //GPIO_23
+#define N_GPIO_24 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00C0 //GPIO_24
+#define N_GPIO_25 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00C8 //GPIO_25
+#define N_GPIO_26 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00D0 //GPIO_26
+#define N_GPIO_27 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00D8 //GPIO_27
+#define N_GPIO_28 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00E0 //GPIO_28
+#define N_GPIO_29 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00E8 //GPIO_29
+#define N_GPIO_30 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00F0 //GPIO_30
+#define N_GPIO_31 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x00F8 //GPIO_31
+#define N_GPIO_32 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0100 //GPIO_32
+#define N_GPIO_33 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0108 //GPIO_33
+#define N_GPIO_34 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0110 //PWM0
+#define N_GPIO_35 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0118 //PWM1
+#define N_GPIO_36 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0120 //PWM2
+#define N_GPIO_37 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0128 //PWM3
+#define N_GPIO_38 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0130 //LPSS_UART0_RXD
+#define N_GPIO_39 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0138 //LPSS_UART0_TXD
+#define N_GPIO_40 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0140 //LPSS_UART0_RTS_B
+#define N_GPIO_41 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0148 //LPSS_UART0_CTS_B
+#define N_GPIO_42 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0150 //LPSS_UART1_RXD
+#define N_GPIO_43 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0158 //LPSS_UART1_TXD
+#define N_GPIO_44 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0160 //LPSS_UART1_RTS_B
+#define N_GPIO_45 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0168 //LPSS_UART1_CTS_B
+#define N_GPIO_46 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0170 //LPSS_UART2_RXD
+#define N_GPIO_47 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0178 //LPSS_UART2_TXD
+#define N_GPIO_48 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0180 //LPSS_UART2_RTS_B
+#define N_GPIO_49 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0188 //LPSS_UART2_CTS_B
+#define N_GPIO_62 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0190 //GP_CAMERASB00
+#define N_GPIO_63 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0198 //GP_CAMERASB01
+#define N_GPIO_64 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01A0 //GP_CAMERASB02
+#define N_GPIO_65 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01A8 //GP_CAMERASB03
+#define N_GPIO_66 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01B0 //GP_CAMERASB04
+#define N_GPIO_67 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01B8 //GP_CAMERASB05
+#define N_GPIO_68 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01C0 //GP_CAMERASB06
+#define N_GPIO_69 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01C8 //GP_CAMERASB07
+#define N_GPIO_70 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01D0 //GP_CAMERASB08
+#define N_GPIO_71 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01D8 //GP_CAMERASB09
+#define N_GPIO_72 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01E0 //GP_CAMERASB10
+#define N_GPIO_73 (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01E8 //GP_CAMERASB11
+#define N_TCK (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01F0 //TCK
+#define N_TRST_B (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x01F8 //TRST_B
+#define N_TMS (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0200 //TMS
+#define N_TDI (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0208 //TDI
+#define N_CX_PMODE (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0210 //CX_PMODE
+#define N_CX_PREQ_B (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0218 //CX_PREQ_B
+#define N_JTAGX (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0220 //JTAGX
+#define N_CX_PRDY_B (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0228 //CXPRDY_B
+#define N_TDO (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0230 //TDO
+#define N_CNV_BRI_DT (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0238 //CNV_BRI_DT
+#define N_CNV_BRI_RSP (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0240 //CNV_BRI_RSP
+#define N_CNV_RGI_DT (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0248 //CNV_RGI_DT
+#define N_CNV_RGI_RSP (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0250 //CNV_RGI_RSP
+#define N_SVID0_ALERT_B (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0258 //SVID0_ALERT_B
+#define N_SVID0_DATA (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0260 //SVID0_DATA
+#define N_SVID0_CLK (((UINT32)GPIO_MMIO_OFFSET_N)<<16)+GPIO_PADBAR+0x0268 //SVID0_CLK
+
+// Northwest community GPIO pad definition
+#define NW_GPIO_187 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0000 //HV_DDI0_DDC_SDA
+#define NW_GPIO_188 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0008 //HV_DDI0_DDC_SCL
+#define NW_GPIO_189 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0010 //HV_DDI1_DDC_SDA
+#define NW_GPIO_190 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0018 //HV_DDI1_DDC_SCL
+#define NW_GPIO_191 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0020 //DBI_SDA
+#define NW_GPIO_192 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0028 //DBI_SCL
+#define NW_GPIO_193 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0030 //PANEL0_VDDEN
+#define NW_GPIO_194 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0038 //PANEL0_BKLTEN
+#define NW_GPIO_195 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0040 //PANEL0_BKLTCTL
+#define NW_GPIO_196 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0048 //PANEL1_VDDEN
+#define NW_GPIO_197 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0050 //PANEL1_BKLTEN
+#define NW_GPIO_198 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0058 //PANEL1_BKLTCTL
+#define NW_GPIO_199 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0060 //DBI_CSX
+#define NW_GPIO_200 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0068 //DBI_RESX
+#define NW_GPIO_201 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0070 //GP_INTD_DSI_TE1
+#define NW_GPIO_202 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0078 //GP_INTD_DSI_TE2
+#define NW_GPIO_203 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0080 //USB_OC0_B
+#define NW_GPIO_204 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0088 //USB_OC1_B
+#define NW_PMC_SPI_FS0 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0090 //PMC_SPI_FS0
+#define NW_PMC_SPI_FS1 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0098 //PMC_SPI_FS1
+#define NW_PMC_SPI_FS2 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00A0 //PMC_SPI_FS2
+#define NW_PMC_SPI_RXD (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00A8 //PMC_SPI_RXD
+#define NW_PMC_SPI_TXD (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00B0 //PMC_SPI_TXD
+#define NW_PMC_SPI_CLK (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00B8 //PMC_SPI_CLK
+#define NW_PMIC_PWRGOOD (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00C0 //PMIC_PWRGOOD
+#define NW_PMIC_RESET_B (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00C8 //PMIC_RESET_B
+#define NW_GPIO_213 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00D0 //PMIC_SDWN_B
+#define NW_GPIO_214 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00D8 //PMIC_BCUDISW2
+#define NW_GPIO_215 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00E0 //PMIC_BCUDISCRIT
+#define NW_PMIC_THERMTRIP_B (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00E8 //PMIC_THERMTRIP_B
+#define NW_PMIC_STDBY (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00F0 //PMIC_STDBY
+#define NW_PROCHOT_B (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x00F8 //PROCHOT_B
+#define NW_PMIC_I2C_SCL (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0100 //PMIC_I2C_SCL
+#define NW_PMIC_I2C_SDA (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0108 //PMIC_I2C_SDA
+#define NW_GPIO_74 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0110 //AVS_I2S1_MCLK
+#define NW_GPIO_75 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0118 //AVS_I2S1_BCLK
+#define NW_GPIO_76 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0120 //AVS_I2S1_WS_SYNC
+#define NW_GPIO_77 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0128 //AVS_I2S1_SDI
+#define NW_GPIO_78 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0130 //AVS_I2S1_SDO
+#define NW_GPIO_79 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0138 //AVS_M_CLK_A1
+#define NW_GPIO_80 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0140 //AVS_M_CLK_B1
+#define NW_GPIO_81 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0148 //AVS_M_DATA_1
+#define NW_GPIO_82 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0150 //AVS_M_CLK_AB2
+#define NW_GPIO_83 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0158 //AVS_M_DATA_2
+#define NW_GPIO_84 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0160 //AVS_I2S2_MCLK
+#define NW_GPIO_85 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0168 //AVS_I2S2_BCLK
+#define NW_GPIO_86 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0170 //AVS_I2S2_WS_SYNC
+#define NW_GPIO_87 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0178 //AVS_I2S2_SDI
+#define NW_GPIO_88 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0180 //AVS_I2S2_SDO
+#define NW_GPIO_89 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0188 //AVS_I2S3_BCLK
+#define NW_GPIO_90 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0190 //AVS_I2S3_WS_SYNC
+#define NW_GPIO_91 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0198 //AVS_I2S3_SDI
+#define NW_GPIO_92 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01A0 //AVS_I2S3_SDO
+#define NW_GPIO_97 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01A8 //FST_SPI_CS0_B
+#define NW_GPIO_98 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01B0 //FST_SPI_CS1_B
+#define NW_GPIO_99 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01B8 //FST_SPI_MOSI_IO0
+#define NW_GPIO_100 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01C0 //FST_SPI_MISO_IO1
+#define NW_GPIO_101 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01C8 //FST_SPI_IO2
+#define NW_GPIO_102 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01D0 //FST_SPI_IO3
+#define NW_GPIO_103 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01D8 //FST_SPI_CLK
+#define NW_FST_SPI_CLK_FB (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01E0 //FST_SPI_CLK_FB
+#define NW_GPIO_104 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01E8 //GP_SSP_0_CLK
+#define NW_GPIO_105 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01F0 //GP_SSP_0_FS0
+#define NW_GPIO_106 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x01F8 //GP_SSP_0_FS1
+#define NW_GPIO_109 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0200 //GP_SSP_0_RXD
+#define NW_GPIO_110 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0208 //GP_SSP_0_TXD
+#define NW_GPIO_111 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0210 //GP_SSP_1_CLK
+#define NW_GPIO_112 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0218 //GP_SSP_1_FS0
+#define NW_GPIO_113 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0220 //GP_SSP_1_FS1
+#define NW_GPIO_116 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0228 //GP_SSP_1_RXD
+#define NW_GPIO_117 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0230 //GP_SSP_1_TXD
+#define NW_GPIO_118 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0238 //GP_SSP_2_CLK
+#define NW_GPIO_119 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0240 //GP_SSP_2_FS0
+#define NW_GPIO_120 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0248 //GP_SSP_2_FS1
+#define NW_GPIO_121 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0250 //GP_SSP_2_FS2
+#define NW_GPIO_122 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0258 //GP_SSP_2_RXD
+#define NW_GPIO_123 (((UINT32)GPIO_MMIO_OFFSET_NW)<<16)+GPIO_PADBAR+0x0260 //GP_SSP_2_TXD
+
+// West community GPIO pad definition
+#define W_GPIO_124 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0000 //LPSS_I2S0_SDA
+#define W_GPIO_125 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0008 //LPSS_I2S0_SCL
+#define W_GPIO_126 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0010 //LPSS_I2S1_SDA
+#define W_GPIO_127 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0018 //LPSS_I2S1_SCL
+#define W_GPIO_128 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0020 //LPSS_I2S2_SDA
+#define W_GPIO_129 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0028 //LPSS_I2S2_SCL
+#define W_GPIO_130 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0030 //LPSS_I2S3_SDA
+#define W_GPIO_131 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0038 //LPSS_I2S3_SCL
+#define W_GPIO_132 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0040 //LPSS_I2S4_SDA
+#define W_GPIO_133 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0048 //LPSS_I2S4_SCL
+#define W_GPIO_134 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0050 //LPSS_I2S5_SDA
+#define W_GPIO_135 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0058 //LPSS_I2S5_SCL
+#define W_GPIO_136 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0060 //LPSS_I2S6_SDA
+#define W_GPIO_137 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0068 //LPSS_I2S6_SCL
+#define W_GPIO_138 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0070 //LPSS_I2S7_SDA
+#define W_GPIO_139 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0078 //LPSS_I2S7_SCL
+#define W_GPIO_146 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0080 //ISH_GPIO_0
+#define W_GPIO_147 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0088 //ISH_GPIO_1
+#define W_GPIO_148 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0090 //ISH_GPIO_2
+#define W_GPIO_149 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0098 //ISH_GPIO_3
+#define W_GPIO_150 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00a0 //ISH_GPIO_4
+#define W_GPIO_151 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00a8 //ISH_GPIO_5
+#define W_GPIO_152 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00b0 //ISH_GPIO_6
+#define W_GPIO_153 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00b8 //ISH_GPIO_7
+#define W_GPIO_154 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00c0 //ISH_GPIO_8
+#define W_GPIO_155 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00c8 //ISH_GPIO_9
+#define W_GPIO_209 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00d0 //PCIE_CLKREQ0_B
+#define W_GPIO_210 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00d8 //PCIE_CLKREQ1_B
+#define W_GPIO_211 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00e0 //PCIE_CLKREQ2_B
+#define W_GPIO_212 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00e8 //PCIE_CLKREQ3_B
+#define W_OSC_CLK_OUT_0 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00f0 //OSC_CLK_OUT0
+#define W_OSC_CLK_OUT_1 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x00f8 //OSC_CLK_OUT1
+#define W_OSC_CLK_OUT_2 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0100 //OSC_CLK_OUT2
+#define W_OSC_CLK_OUT_3 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0108 //OSC_CLK_OUT3
+#define W_OSC_CLK_OUT_4 (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0110 //OSC_CLK_OUT4
+#define W_PMU_AC_PRESENT (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0118 //PMU_AC_PRESENT
+#define W_PMU_BATLOW_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0120 //PMU_BATLOW_B
+#define W_PMU_PLTRST_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0128 //PMU_PLTRST_B
+#define W_PMU_PWRBTN_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0130 //PMU_PWRBTN_B
+#define W_PMU_RESETBUTTON_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0138 //PMU_RESETBUTTON_B
+#define W_PMU_SLP_S0_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0140 //PMU_SLP_S0_B
+#define W_PMU_SLP_S3_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0148 //PMU_SLP_S3_B
+#define W_PMU_SLP_S4_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0150 //PMU_SLP_S4_B
+#define W_PMU_SUSCLK (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0158 //PMU_SUSCLK
+#define W_PMU_WAKE_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0160 //PMU_WAKE_B
+#define W_SUS_STAT_B (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0168 //SUS_STAT_B
+#define W_SUSPWRDNACK (((UINT32)GPIO_MMIO_OFFSET_W)<<16)+GPIO_PADBAR+0x0170 //SUSPWRDNACK
+
+// Southwest community GPIO pad definition
+#define SW_GPIO_205 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0000 //PCIE_WAKE0_B
+#define SW_GPIO_206 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0008 //PCIE_WAKE1_B
+#define SW_GPIO_207 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0010 //PCIE_WAKE2_B
+#define SW_GPIO_208 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0018 //PCIE_WAKE3_B
+#define SW_GPIO_156 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0020 //EMMC0_CLK
+#define SW_GPIO_157 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0028 //EMMC0_D0
+#define SW_GPIO_158 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0030 //EMMC0_D1
+#define SW_GPIO_159 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0038 //EMMC0_D2
+#define SW_GPIO_160 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0040 //EMMC0_D3
+#define SW_GPIO_161 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0048 //EMMC0_D4
+#define SW_GPIO_162 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0050 //EMMC0_D5
+#define SW_GPIO_163 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0058 //EMMC0_D6
+#define SW_GPIO_164 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0060 //EMMC0_D7
+#define SW_GPIO_165 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0068 //EMMC0_CMD0
+#define SW_GPIO_166 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0070 //SDIO_CLK
+#define SW_GPIO_167 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0078 //SDIO_D0
+#define SW_GPIO_168 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0080 //SDIO_D1
+#define SW_GPIO_169 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0088 //SDIO_D2
+#define SW_GPIO_170 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0090 //SDIO_D3
+#define SW_GPIO_171 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0098 //SDIO_CMD
+#define SW_GPIO_172 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00A0 //SDCARD_CLK
+#define SW_GPIO_179 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00D8 //SDCARD_CMD
+#define SW_GPIO_173 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00A8 //SDCARD_CLK_FB
+#define SW_GPIO_174 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00B0 //SDCARD_D0
+#define SW_GPIO_175 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00B8 //SDCARD_D1
+#define SW_GPIO_176 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00C0 //SDCARD_D2
+#define SW_GPIO_177 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00C8 //SDCARD_D3
+#define SW_GPIO_178 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00D0 //SDCARD_CD_B
+#define SW_GPIO_186 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00E0 //SDCARD_LVL_WP
+#define SW_GPIO_182 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00E8 //EMMC0_STROBE
+#define SW_GPIO_183 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00F0 //SDIO_PWR_DOWN_B
+#define SW_SMB_ALERTB (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x00F8 //SMB_ALERTB
+#define SW_SMB_CLK (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0100 //SMB_CLK
+#define SW_SMB_DATA (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0108 //SMB_DATA
+#define SW_LPC_ILB_SERIRQ (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0110 //LPC_ILB_SERIRQ
+#define SW_LPC_CLKOUT0 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0118 //LPC_CLKOUT0
+#define SW_LPC_CLKOUT1 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0120 //LPC_CLKOUT1
+#define SW_LPC_AD0 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0128 //LPC_AD0
+#define SW_LPC_AD1 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0130 //LPC_AD1
+#define SW_LPC_AD2 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0138 //LPC_AD2
+#define SW_LPC_AD3 (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0140 //LPC_AD3
+#define SW_LPC_CLKRUN (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0148 //LPC_CLKRUN
+#define SW_LPC_FRAMEB (((UINT32)GPIO_MMIO_OFFSET_SW)<<16)+GPIO_PADBAR+0x0150 //LPC_FRAMEB
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/ConfigBlockLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/ConfigBlockLib.h new file mode 100644 index 0000000000..b9675be4d0 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/ConfigBlockLib.h @@ -0,0 +1,91 @@ +/** @file
+ Header file for Config Block Lib implementation.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+ Create config block table
+
+ @param[in] NumberOfBlocks Number of Config Blocks.
+
+ @retval Size Size of Config Block Table Header and Offset Table.
+
+**/
+UINT32
+EFIAPI
+GetSizeOfConfigBlockTableHeaders (
+ IN UINT16 NumberOfBlocks
+ );
+
+/**
+ Create config block table
+
+ @param[out] ConfigBlockTableAddress On return, points to a pointer to the beginning of Config Block Table Address.
+ @param[in] NumberOfBlocks Number of Config Blocks.
+ @param[in] TotalSize Max size to be allocated for the Config Block Table.
+
+ @retval EFI_INVALID_PARAMETER Invalid Parameter.
+ @retval EFI_OUT_OF_RESOURCES Out of resources.
+ @retval EFI_SUCCESS Successfully created Config Block Table at ConfigBlockTableAddress.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+ OUT VOID **ConfigBlockTableAddress,
+ IN UINT16 NumberOfBlocks,
+ IN UINT32 TotalSize
+ );
+
+/**
+ Add config block into config block table structure.
+
+ @param[in] ConfigBlockTableAddress A pointer to the beginning of Config Block Table Address.
+ @param[out] ConfigBlockAddress On return, points to a pointer to the beginning of Config Block Address.
+
+ @retval EFI_OUT_OF_RESOURCES Config Block Table is full and cannot add new Config Block or
+ Config Block Offset Table is full and cannot add new Config Block.
+ @retval EFI_SUCCESS Successfully added Config Block.
+
+**/
+EFI_STATUS
+EFIAPI
+AddConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ OUT VOID **ConfigBlockAddress
+ );
+
+/**
+ Retrieve a specific Config Block data by GUID.
+
+ @param[in] ConfigBlockTableAddress A pointer to the beginning of Config Block Table Address.
+ @param[in] ConfigBlockGuid A pointer to the GUID uses to search specific Config Block.
+ @param[out] ConfigBlockAddress On return, points to a pointer to the beginning of Config Block Address.
+
+ @retval EFI_NOT_FOUND Could not find the Config Block.
+ @retval EFI_SUCCESS Config Block found and return.
+
+**/
+EFI_STATUS
+EFIAPI
+GetConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ IN EFI_GUID *ConfigBlockGuid,
+ OUT VOID **ConfigBlockAddress
+ );
+
+#endif // _CONFIG_BLOCK_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/GpioLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/GpioLib.h new file mode 100644 index 0000000000..cfbbb7761c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/GpioLib.h @@ -0,0 +1,651 @@ +/** @file
+ This library provides the GPIO library definitions.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include "BxtPGpioLib.h"
+
+// GPIO Community Port ID definition
+#define GPIO_SOUTHWEST_COMMUNITY 0xC0
+#define GPIO_SOUTH_COMMUNITY 0xC2
+#define GPIO_NORTHWEST_COMMUNITY 0xC4
+#define GPIO_NORTH_COMMUNITY 0xC5
+#define GPIO_WEST_COMMUNITY 0xC7
+
+//
+// GPIO Community Port ID definition
+//
+#define GPIO_MMIO_OFFSET_SW 0xC0
+#define GPIO_MMIO_OFFSET_S 0xC2
+#define GPIO_MMIO_OFFSET_NW 0xC4
+#define GPIO_MMIO_OFFSET_N 0xC5
+#define GPIO_MMIO_OFFSET_W 0xC7
+
+#define BXT_GPIO_PAD_CONF0_OFFSET 0x0
+#define BXT_GPIO_PAD_CONF1_OFFSET 0x4
+#define NA 0xFF
+
+#define ALL_COMMUNITY_GPIO_PIN_NUM 248
+
+// GPIO pad DW0 MASK
+#define PAD_DW0_MASK 0xF961E0FE ///< bit 27, 24, 22, 21, 16:13, 7:1 are RO, mask bit [31:28] as they are modified as usual, special operation for them if need.
+// GPIO pad DW1 MASK
+#define PAD_DW1_MASK 0xFFFC00FF ///< bit [17:14],[13:10],[9:8] are R/W
+
+//
+// BXTM GPIO Groups
+// Use below for functions from GPIO Lib which
+// require GpioGroup as argument
+//
+#define GPIO_BXTM_GROUP_0 0x0100 ///< SOUTH GPIO pin 0 ~ 19 belong to BXTM GROUP0
+#define GPIO_BXTM_GROUP_1 0x0101 ///< SOUTHWEST GPIO pin 0 ~ 23 belong to BXTM GROUP1
+#define GPIO_BXTM_GROUP_2 0x0102 ///< WEST GPIO pin 0 ~ 23 belong to BXTM GROUP2
+#define GPIO_BXTM_GROUP_4 0x0104 ///< NORTHWEST GPIO pin 21 ~ 23 belong to BXTM GROUP4
+#define GPIO_BXTM_GROUP_5 0x0105 ///< NORTH GPIO pin 32 ~ 55 belong to BXTM GROUP8
+#define GPIO_BXTM_GROUP_6 0x0106 ///< NORTHWEST GPIO pin 64 ~ 71 belong to BXTM GROUP6
+#define GPIO_BXTM_GROUP_7 0x0107 ///< NORTH GPIO pin 0 ~ 23 belong to BXTM GROUP7
+#define GPIO_BXTM_GROUP_8 0x0108 ///< NORTH GPIO pin 32 ~ 55 belong to BXTM GROUP8
+#define GPIO_BXTM_GROUP_9 0x0109 ///< NORTH GPIO pin 64 ~ 73 belong to BXTM GROUP9
+
+//
+// BXTP GPIO Groups
+// Use below for functions from GPIO Lib which
+// require GpioGroup as argument
+//
+#define GPIO_BXTP_GROUP_0 0x0200 ///< SOUTHWEST GPIO pin 0 ~ 31 belong to BXTP GROUP0
+#define GPIO_BXTP_GROUP_1 0x0201 ///< SOUTHWEST GPIO pin 32 ~ 42 belong to BXTP GROUP1
+#define GPIO_BXTP_GROUP_2 0x0202 ///< WEST GPIO pin 0 ~ 25 belong to BXTP GROUP2
+#define GPIO_BXTP_GROUP_4 0x0204 ///< NORTHWEST GPIO pin 0 ~ 17 belong to BXTP GROUP4
+#define GPIO_BXTP_GROUP_5 0x0205 ///< NORTHWEST GPIO pin 32 ~ 63 belong to BXTP GROUP5
+#define GPIO_BXTP_GROUP_6 0x0206 ///< NORTHWEST GPIO pin 64 ~ 76 belong to BXTP GROUP6
+#define GPIO_BXTP_GROUP_7 0x0207 ///< NORTH GPIO pin 0 ~ 31 belong to BXTP GROUP7
+#define GPIO_BXTP_GROUP_8 0x0208 ///< NORTH GPIO pin 32 ~ 61 belong to BXTP GROUP8
+
+//
+// For any GpioGroup usage in code use GPIO_GROUP type
+//
+typedef UINT32 GPIO_GROUP;
+
+#define GPIO_GET_GROUP_INDEX(Group) (Group & 0xFF)
+
+#define R_GPIO_MISCCFG 0x10 ///< Miscellaneous Configuration
+#define B_GPIO_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16)
+#define N_GPIO_MISCCFG_GPE0_DW2 16
+#define B_GPIO_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12)
+#define N_GPIO_MISCCFG_GPE0_DW1 12
+#define B_GPIO_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8)
+#define N_GPIO_MISCCFG_GPE0_DW0 8
+#define B_GPIP_MISCCFG (BIT0|BIT1) ///< Enable participation in dynamic local & partition clock gating
+
+#define PAD_OWNERSHIP_0 0x20
+#define V_PAD_OWNERSHIP_MASK 0x03
+#define V_PAD_OWNERSHIP_HOST 0x00
+#define HOSTSW_OWNERSHIP_0 0x80
+#define GPI_IS_0 0x100
+#define GPI_IE_0 0x110
+#define GPI_GPE_STS_0 0x120
+#define GPI_GPE_EN_0 0x130
+#define GPI_SMI_STS_0 0x140
+#define GPI_SMI_EN_0 0x150
+#define EVOUTEN_0 0x210
+#define EVMAP_0 0x220
+
+#define EVENT_MUX_SIZE 16 ///< MUX is 16:1 on Broxton
+#define WAKE_EVENT_NUM 16 ///< 16 direct IRQ wake events are supported on Broxton in North and Northwest communities.
+
+typedef enum {
+ Native = 0xff,
+ GPIO = 0, ///< Native, no need to set PAD_VALUE
+ GPI = 1, ///< GPI, input only in PAD_VALUE
+ GPO = 2, ///< GPO, output only in PAD_VALUE
+ HI_Z = 3,
+} GPIO_En;
+
+typedef enum {
+ LO = 0,
+ HI = 1,
+} GPO_D4;
+
+/*
+ Mapping to CONF0 bit 27:24
+ Note: Assume "Direct Irq En" is not set, unless specially notified
+*/
+typedef enum {
+ P_NONE = 0, ///< Pull None
+ P_5K_L = 2, ///< Pull Down 5K
+ P_20K_L = 4, ///< Pull Down 20K
+ P_1K_H = 9, ///< Pull Up 1K
+ P_2K_H = 11, ///< Pull Up 2K
+ P_20K_H = 12, ///< Pull Up 20K
+ P_5K_H = 10, ///< Pull Up 5K
+ P_1K2K_H = 13, ///< Pull Up 1K
+ Native_control = 15
+} PULL_TYPE;
+
+typedef enum {
+ M0 = 0,
+ M1,
+ M2,
+ M3,
+ M4,
+ M5
+} ModeList;
+
+typedef enum {
+ Level = 0,
+ Edge = 1,
+ INT_DIS = 2,
+ BothEdge = 3,
+} INT_Type;
+
+typedef enum {
+ SOUTH = GPIO_SOUTH_COMMUNITY,
+ WEST = GPIO_WEST_COMMUNITY,
+ NORTHWEST = GPIO_NORTHWEST_COMMUNITY,
+ SOUTHWEST = GPIO_SOUTHWEST_COMMUNITY,
+ NORTH = GPIO_NORTH_COMMUNITY
+} coms;
+
+typedef enum {
+ IOAPIC = 8 ,
+ SCI = 4,
+ SMI = 2,
+ NMI = 1,
+ NONE = 0,
+} GPIO_Route;
+
+/*
+ InvertRxTx 7:4
+ 0 - No Inversion
+ 1 - Inversion
+ [0] RX Enable
+ [1] TX Enable
+ [2] RX Data
+ [3] TX Data
+*/
+typedef enum {
+ No_invert = 0,
+ Inverted = 1,
+} InvertRX;
+
+typedef enum {
+ ACPI_D = 0, // ACPI driver
+ GPIO_D = 1, // GPIO driver
+} HOSTSW;
+
+/*
+ I/O Standby State
+*/
+typedef enum {
+ Last_Value = 0, ///< 0 = Latch last value driven on TX, TX Enable and RX Enable
+ D0RxDRx0I = 1, ///< 1 = Drive 0 with RX disabled and RX drive 0 internally
+ D0RxDRx1I = 2, ///< 2 = Drive 0 with RX disabled and RX drive 1 internally
+ D1RxDRx0I = 3, ///< 3 = Drive 1 with RX disabled and RX drive 0 internally
+ D1RxDRx1I = 4, ///< 4 = Drive 1 with RX disabled and RX drive 1 internally
+ D0RxE = 5, ///< 5 = Drive 0 with RX enabled
+ D1RxE = 6, ///< 6 = Drive 1 with RX enabled
+ HizRx0I = 7, ///< 7 = Hi-Z with RX drive 0 internally
+ HizRx1I = 8, ///< 8 = Hi-Z with RX drive 1 internally
+ TxDRxE = 9, ///< 9 = TX Disabled and RX Enabled (i.e. wake or interrupt)
+ IOS_Masked = 15, ///< 15 = IO Standby signal is masked for this pad.
+} IOSSTATE;
+
+/*
+ I/O Standby Termination
+*/
+typedef enum {
+ SAME = 0, ///< 0 = Same as functional pull
+ DisPuPd = 1, ///< 1 = Disable Pullup and Pulldown
+ EnPd = 2, ///< 2 = Enable Pulldown
+ EnPu = 3, ///< 3 = Enable Pullup
+} IOSTERM;
+
+/*
+ Wake enable or disable for direct IRQ GPIO pin
+*/
+typedef enum {
+ Wake_Disabled = FALSE,
+ Wake_Enabled = TRUE,
+} WAKE_CAPABLE;
+
+typedef enum
+{
+ Host_Gpio_Mode = 0,
+ CSME_Gpio_Mode = 1,
+ ISH_Gpio_Mode = 2,
+ IE_Gpio_mode = 3,
+} GPIO_PAD_OWNERSHIP;
+
+typedef union {
+ UINT32 padCnf0;
+ struct {
+ UINT32 GPIOTxState:1; ///< 0 GPIO TX State
+ UINT32 GPIORxState:1; ///< 1 GPIO RX State, RO
+ UINT32 Reserved1:6; ///< 2-7 Reserved, RO
+ UINT32 GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8]
+ UINT32 PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc.
+ UINT32 Reserved2:4; ///< 13-16 Reserved, RO
+ UINT32 GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17]
+ UINT32 RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO
+ UINT32 RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion
+ UINT32 PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT
+ UINT32 RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge
+ UINT32 Reserved3:1; ///< 27 RO
+ UINT32 RXRAW1:1; ///< 28 Override the RX to 1
+ UINT32 RXPadStSel:1; ///< 29 RX Pad State Select
+ UINT32 PadRstCfg:2; ///< 30-31 Pad Reset Config
+ } r;
+} BXT_CONF_PAD0;
+
+typedef union {
+ UINT32 padCnf1;
+ struct {
+ UINT32 IntSel:7; ///< 0-6 Interrupt Select. RO
+ UINT32 Reserved:1; ///< 7 Reserved.
+ UINT32 IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW
+ UINT32 Term:4; ///< 10-13 Termination,
+ ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu;
+ ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination
+ UINT32 IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW
+ UINT32 CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO
+ } r;
+} BXT_CONF_PAD1;
+
+typedef struct {
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT8 Community;
+ UINT16 MMIO_ADDRESS;
+ BOOLEAN HostSw;
+ BOOLEAN WakeEnabled; ///< Wake enable for direct IRQ pin
+ CHAR16 *pad_name; ///< GPIO Pin Name for debug purpose
+} BXT_GPIO_PAD_INIT;
+
+typedef struct {
+ UINT32 CommAndOffset;
+ CHAR16* pad_name;
+} BXT_GPIO_PAD_TABLE;
+
+typedef struct {
+ UINT32 CommAndOffset;
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT8 HostSw;
+ BOOLEAN WakeEnabled;
+} BXT_GPIO_CONFIG;
+
+typedef union {
+ UINT32 DW;
+ struct {
+ UINT32 Community: 8;
+ UINT32 Offset: 12;
+ UINT32 HostSw: 1;
+ UINT32 DirectIrqWake: 1;
+ UINT32 Reserved0: 10;
+ } r;
+} GPIO_CONFIG_SMIP_HALF0;
+
+typedef union {
+ UINT32 DW;
+ struct {
+ UINT32 padConfig0: 20; ///< GPIO Pad DW0's R/W bits: [0], [8:12], [17:26], [28:31]
+ UINT32 padConfig1: 10; ///< GPIO pad DW1's R/W bits:[8:17]
+ UINT32 Reserved0: 2;
+ } r;
+} GPIO_CONFIG_SMIP_HALF1;
+
+typedef struct {
+ GPIO_CONFIG_SMIP_HALF0 Half0;
+ GPIO_CONFIG_SMIP_HALF1 Half1;
+} GPIO_CONFIG_SMIP;
+
+// product all items of BXT_GPIO_PAD_INIT
+#define BXT_GPIO_PAD_CONF(pad_name, PMode, GPIO_Config, HostSw, GPO_STATE, INT_Trigger, WakeEnabled, Term_H_L, Inverted, GPI_ROUT, IOSState, IOSTerm, MMIO_Offset, Community ) { \
+ {((((INT_Trigger) != NA) ? ((UINT32) INT_Trigger << 25) : (UINT32)INT_DIS << 25 ) | (((Inverted) != NA) ? ((UINT32) Inverted << 23) : (UINT32)No_invert << 23) | (((GPI_ROUT) != NA) ? ((UINT32) GPI_ROUT << 17) : (UINT32)NONE << 17) | ((UINT32) PMode << 10) | (((GPIO_Config) != NA) ? ((UINT32) GPIO_Config << 8 ): (UINT32)0 << 8) | (((GPO_STATE) == HI ) ? HI : LO))}, \
+ {(((IOSState != NA) ? ((UINT32) IOSState << 14 ) : Last_Value) | (((Term_H_L) != NA) ? ((UINT32) Term_H_L << 10) : P_NONE) | ((IOSTerm != NA) ? ((UINT32) IOSTerm << 8) : SAME))}, \
+ Community, \
+ (MMIO_Offset != NA) ? (MMIO_Offset) : 0, \
+ ((HostSw == NA)||(HostSw == ACPI_D))? ACPI_D : GPIO_D,\
+ WakeEnabled,\
+ pad_name \
+ }
+
+
+#define SMIP_Config0_Convert(SmipPadConfig0) ( \
+ (((UINT32)SmipPadConfig0 & (BIT16 | BIT17 | BIT18 | BIT19)) << 12) | \
+ (((UINT32)SmipPadConfig0 & (0xFFC0)) << 11) | \
+ (((UINT32)SmipPadConfig0 & (BIT1 | BIT2 | BIT3 |BIT4 | BIT5)) << 7) | \
+ ((UINT32)SmipPadConfig0 & (BIT0)) \
+ )
+
+#define SMIP_Config1_Convert(SmipPadConfig1) ( \
+ ((UINT32)SmipPadConfig1 & 0x3FF) << 8 \
+ )
+
+/**
+ Common interface to write an 32-bit GPIO register.
+
+ @param[in] Community Community Port ID definition.
+ SouthWest Community: 0xC0
+ South Community : 0xC2
+ NorthWest Community: 0xC4
+ North Community : 0xC5
+ West Community : 0xC7
+ @param[in] Offset The GPIO register to write.
+ @param[in] Value The value to write.
+
+ @retval EFI_SUCCESS Write GPIO register successfully.
+
+**/
+EFI_STATUS
+GpioWrite (
+ IN UINT8 Community,
+ IN UINT16 Offset,
+ IN UINT32 Value
+ );
+
+/**
+ Common interface to read an 32-bit GPIO register.
+
+ @param[in] Community Community Port ID definition.
+ SouthWest Community: 0xC0
+ South Community : 0xC2
+ NorthWest Community: 0xC4
+ North Community : 0xC5
+ West Community : 0xC7
+ @param[in] Offset The GPIO register to read.
+
+ @retval UINT32 The 32-bit value read from side band.
+
+**/
+UINT32
+GpioRead (
+ IN UINT8 Community,
+ IN UINT16 Offset
+ );
+
+/**
+ Common interface to read an 32-bit specific GPIO pad register.
+
+ It is recommand to use the definition of GPIO pad in GpioLib.h
+ e.g. GpioPadRead (N_GPIO_20)
+
+ @param[in] CommAndOffset It contains GPIO community and offset.
+
+ @retval UINT32 The 32-bit value read from GpioRead operation.
+
+**/
+UINT32
+GpioPadRead (
+ IN UINT32 CommAndOffset
+ );
+
+/**
+ Common interface to write an 32-bit to a specific GPIO pad register.
+
+ It is recommand to use the definition of GPIO pad in GpioLib.h
+ e.g. GpioPadWrite (N_GPIO_20, 0xXXXXXXXX)
+
+ @param[in] CommAndOffset It contains GPIO community and offset.
+ @param[in] Value The value to write.
+
+ @retval EFI_SUCCESS Write to a specific GPIO pad register successfully.
+ @retval Others Status depends on GpioWrite operation.
+
+**/
+EFI_STATUS
+GpioPadWrite(
+ IN UINT32 CommAndOffset,
+ IN UINT32 Value
+ );
+
+/**
+ Set GPIO PAD DW 0 and 1 registers for South/West/SouthWest/North/NorthWest GPIO communities.
+
+ @param[in] Gpio_Pin_Num GPIO Pin Number to configure.
+ @param[in] Gpio_Conf_Data Data array of default setting for each GPIO communities.
+
+**/
+VOID
+GpioPadConfigTable (
+ IN UINT32 Gpio_Pin_Num,
+ IN BXT_GPIO_PAD_INIT *Gpio_Conf_Data
+ );
+
+/**
+ Program SMIP GPIO PAD DW 0 and 1 registers for South/West/SouthWest/North/NorthWest GPIO communities.
+
+ @param[in] Gpio_Pin_Num GPIO Pin Number to configure.
+ @param[in] Gpio_Smip_Conf_Data Data array from SMIP setting for each GPIO communities.
+
+**/
+VOID
+GpioSmipPadConfigTable (
+ IN UINT32 Gpio_Pin_Num,
+ IN GPIO_CONFIG_SMIP* Gpio_Smip_Conf_Data
+ );
+
+/**
+ Set GPIO PAD DW 0 and 1 registers for South/West/SouthWest/North/NorthWest GPIO communities.
+
+ @param[in] Gpio_Conf_Data The structure contains GPIO community and pad 0/1 value.
+
+**/
+VOID
+GpioPadConfigItem (
+ IN BXT_GPIO_CONFIG Gpio_Conf_Data
+ );
+
+/**
+ This procedure will get GPIO pad input inversion value
+
+ @param[in] GpioPad GPIO pad
+ @param[out] InvertState GPIO inversion state
+ 0: No input inversion, 1: Inverted input
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+GpioGetInputInversion (
+ IN UINT32 GpioPad,
+ OUT UINT32 *InvertState
+ );
+
+/**
+ This procedure will set GPIO pad input inversion value
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value GPIO inversion value
+
+ @retval EFI_SUCCESS Set GPIO pad input inversion value successfully.
+ @retval Others Status depends on GpioPadWrite operation.
+
+**/
+EFI_STATUS
+GpioSetInputInversion (
+ IN UINT32 GpioPad,
+ IN UINT64 Value
+ );
+
+/**
+ This procedure is used to clear SMI STS for a specified Pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval Others Status depends on GpioWrite operation.
+
+**/
+EFI_STATUS
+GpioClearGpiSmiSts (
+ IN UINT32 GpioPad
+ );
+
+/**
+ This procedure is used by ScSmiDispatcher and will clear
+ all GPI SMI Status bits
+
+ @retval EFI_SUCCESS The function completed successfully
+
+**/
+EFI_STATUS
+GpioClearAllGpiSmiSts (
+ VOID
+ );
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI. Relation between Index and GpioPad number is:
+ Index = GpioGroup + 24 * GpioPad
+
+ @param[in] Index GPI SMI number
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiSmiEnRegAddress Address of GPI SMI Enable register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+
+**/
+
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiSmiEnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ );
+
+/**
+ This procedure will set GPIO output level
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Output value
+ 0: OutputLow, 1: OutputHigh
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval Others Status depends on GpioPadWrite operation.
+
+**/
+EFI_STATUS
+GpioSetOutputValue (
+ IN UINT32 GpioPad,
+ IN UINT32 Value
+ );
+
+/**
+ This procedure will get GPIO input level
+
+ @param[in] GpioPad GPIO pad
+ @param[out] InputVal GPIO Input value
+ 0: InputLow, 1: InpuHigh
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval Others Status depends on GpioPadRead operation.
+
+**/
+EFI_STATUS
+GpioGetInputValue (
+ IN UINT32 GpioPad,
+ OUT UINT32 *InputVal
+ );
+
+/**
+ This procedure is used to register GPI SMI dispatch function.
+
+ @param[in] GpioPad GPIO pad
+ @param[out] GpiNum GPI number
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+GpioGetGpiSmiNum (
+ IN UINT32 GpioPad,
+ OUT UINT64 *GpiNum
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+
+**/
+EFI_STATUS
+GpioLockPadCfg (
+ IN UINT32 GpioPad
+ );
+
+/**
+ This procedure will set PadCfgLockTx for selected pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+
+**/
+EFI_STATUS
+GpioLockPadCfgTx (
+ IN UINT32 GpioPad
+ );
+
+/**
+ This procedure will set Group to GPE mapping.
+
+ @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
+ @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
+ @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number.
+
+**/
+EFI_STATUS
+GpioSetGroupToGpeDwX (
+ IN GPIO_GROUP GroupToGpeDw0,
+ IN GPIO_GROUP GroupToGpeDw1,
+ IN GPIO_GROUP GroupToGpeDw2
+ );
+
+VOID
+PrintGpioPadTitle(
+ VOID
+ );
+
+VOID
+DumpGpioPadRegisters(
+ IN UINT32 CommAndOffset,
+ IN UINT16 *PadName
+ );
+
+VOID
+DumpGpioCommunityRegisters(
+ IN UINT8 community
+ );
+
+VOID
+DumpGpioPadTable(
+ IN UINT32 Gpio_Pin_Size,
+ IN BXT_GPIO_PAD_INIT* Gpio_Conf_Data
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/MmPciLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/MmPciLib.h new file mode 100644 index 0000000000..9f8d901e2a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/MmPciLib.h @@ -0,0 +1,37 @@ +/** @file
+ Get PCI Express address library implementation.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MM_PCI_LIB_H_
+#define _MM_PCI_LIB_H_
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+
+**/
+UINTN
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+ );
+
+#endif // _MM_PCI_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PeiDxeSmmMmPciLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PeiDxeSmmMmPciLib.h new file mode 100644 index 0000000000..925cc716a7 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PeiDxeSmmMmPciLib.h @@ -0,0 +1,37 @@ +/** @file
+ Get Pci Express address library implementation.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_DXE_SMM_MM_PCI_LIB_H_
+#define _PEI_DXE_SMM_MM_PCI_LIB_H_
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+
+**/
+UINTN
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+ );
+
+#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PeiSiPolicyLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PeiSiPolicyLib.h new file mode 100644 index 0000000000..0aa867addc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PeiSiPolicyLib.h @@ -0,0 +1,55 @@ +/** @file
+ Prototype of the PeiSiPolicyLib library.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SI_POLICY_LIB_H_
+#define _PEI_SI_POLICY_LIB_H_
+
+#include <Ppi/SiPolicyPpi.h>
+
+/**
+ SiCreatePolicyDefaults creates the default setting of Silicon Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SiPolicyPpi The pointer to get Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SiCreatePolicyDefaults (
+ OUT SI_POLICY_PPI **SiPolicyPpi
+ );
+
+/**
+ SiInstallPolicyPpi installs SiPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+#endif // _PEI_SI_POLICY_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h new file mode 100644 index 0000000000..905211bc70 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h @@ -0,0 +1,236 @@ +/** @file
+ Base IPC library implementation.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMC_IPC_LIB_
+#define _PMC_IPC_LIB_
+
+//
+// IPC Register Offsets to PMC BAR0 (IPC1: 0x0000 ~ 0xFFF; GCR: 0x1000 ~ 0x1FFF)
+//
+#define R_IPC_CMD_OFFSET 0x00
+#define R_IPC_STS_OFFSET 0x04
+#define R_IPC_SPTR_OFFSET 0x08
+#define R_IPC_DPTR_OFFSET 0x0C
+#define R_IPC_WBUF_OFFSET 0x80
+#define R_IPC_RBUF_OFFSET 0x90
+#define S_IPC_RWBUF_SIZE 16
+
+//
+// IPC_CMD type
+//
+typedef enum {
+ IPC_CMD_NONE,
+ IPC_CMD_READ,
+ IPC_CMD_WRITE,
+ IPC_CMD_MAX
+} IPC_CMD_TYPE;
+
+//
+// IPC_CMD register
+//
+typedef union {
+ struct {
+ UINT32 CommandId :8;
+ UINT32 Msi :1;
+ UINT32 Reserved1 :3;
+ UINT32 SubCmdId :4;
+ UINT32 Size :8;
+ UINT32 Reserved2 :8;
+ } Bits;
+ UINT32 Uint32;
+} IPC_COMMAND;
+
+//
+// IPC_STS register
+//
+typedef union {
+ struct {
+ UINT32 Busy :1;
+ UINT32 Error :1;
+ UINT32 Reserved1 :2;
+ UINT32 CmdId :4;
+ UINT32 IndicatorId :8;
+ UINT32 ErrCode :8;
+ UINT32 Reserved2 :8;
+ } Bits;
+ UINT32 Uint32;
+} IPC_STATUS;
+
+///
+/// IPC command opcodes
+///
+/// @note: These commands need to double-confirm since FAS has conflicting definitions
+///
+
+#define IPC_CMD_ID_CAPSULE_UPDATE_RESET 0xE5 ///< PMC Capsule Update Reset
+#define IPC_SUBCMD_ID_CAPSULE_UPDATE_RESET 0x00 ///< Reserved, ignore by PMC
+
+#define IPC_CMD_ID_PMC_VER 0xE7 ///< PMC FW version
+#define IPC_SUBCMD_ID_PMC_VER_READ 0x00 ///< Read PMC FW version
+
+#define IPC_CMD_ID_EMI_RFI_SUPPORT 0xE8 ///< PMC EMI/RFI Support, Note that this command is not valid on BXT-A
+#define IPC_SUBCMD_ID_SSC_APPLY_NOW 0x01 ///< Apply the SSC setting immidiately
+#define IPC_SUBCMD_ID_SSC_DO_NOT_APPLY_NOW 0x00 ///< Apply the SSC setting on next cold reset or s0ix exit
+
+#define IPC_CMD_ID_TELEMETRY 0xEB ///< Cmds used to read and write PMC telemetry registers
+#define IPC_SUBID_TELEMETRY_EVENT_READ 0x00 ///< Reads a TELEM_EVENT register
+#define IPC_SUBID_TELEMETRY_EVENT_WRITE 0x01 ///< Writes a TELEM_EVENT register
+
+#define IPC_SUBID_TELEMETRY_INFO_READ 0x02 ///< Reads the TELEM_INFO register
+
+#define IPC_SUBID_TELEMETRY_TRACE_READ 0x03 ///< Read MBB_TELEM_TRACE_MASK register
+#define IPC_SUBID_TELEMETRY_TRACE_WRITE 0x04 ///< Writes the MBB_TELEM_TRACE_MASK register
+
+#define IPC_SUBID_TELEMETRY_TRACE_CTL_READ 0x05 ///< Reads the MBB_TELEM_CONTROL register
+#define IPC_SUBID_TELEMETRY_TRACE_CTL_WRITE 0x06 ///< Writes the MBB_TELEM_CONTROL register
+
+#define IPC_SUBID_TELEMETRY_EVENT_CTL_READ 0x07 ///< Reads the TELEM_EVENT_CTL register
+#define IPC_SUBID_TELEMETRY_EVENT_CTL_WRITE 0x08 ///< Writes the TELEM_EVENT_CTL register
+
+#define IPC_CMD_ID_SOUTH_IP_UNGATE 0xE9 ///< Control South IP powergating for Visa Programming
+#define IPC_SUBCMD_ID_SOUTH_IP_ALLOW_GATING 0x0 ///< South IP allow gating
+#define IPC_SUBCMD_ID_SOUTH_IP_UN_GATING 0x1 ///< South IP Ungate
+
+#define IPC_CMD_ID_FW_MSG_CTRL 0xEA ///< Read and write the PMC FW_MSG_CTL register
+#define IPC_SUBCMD_ID_FW_MSG_CTRL_READ 0x0 ///< Read PMC FW_MSG_CTL register (1 byte returned from PMC)
+#define IPC_SUBCMD_ID_FW_MSG_CTRL_WRITE 0x1 ///< Write PMC FW_MSG_CTL register (1 byte written to PMC)
+
+#define IPC_CMD_ID_PM_DEBUG 0xEC ///< Cmds supported for PM debug
+#define IPC_SUBCMD_ID_LPSS_DEBUG_UART_ENABLE 0X0B ///< LPSS Debug UART Enable
+#define IPC_SUBCMD_ID_LPSS_DEBUG_UART_DISABLE 0X0C ///< LPSS Debug UART Disable
+#define IPC_SUBCMD_ID_PM_DEBUG_LTR_IGNORE_REPORT 0x0D ///< LTR Report (IP to report is specified via IPC_WBUF)
+#define IPC_SUBCMD_ID_PM_DEBUG_LTR_IGNORE_READ 0x0E ///< LTR ignore read
+#define IPC_SUBCMD_ID_PM_DEBUG_LTR_IGNORE_WRITE 0x0F ///< LTR ignore write
+
+#define IPC_CMD_ID_PHY_CFG 0xEE ///< Used by BIOS to communicate mphy configuration information, which MPHY is specified in IPC_WBUF
+#define IPC_SUBCMD_ID_PHY_CFG_COMPLETE 0x00 ///< PHY configuration is complete
+#define IPC_SUBCMD_ID_PHY_WILL_NOT_CFG 0x01 ///< PHY will not be configured
+
+#define IPC_CMD_ID_USB3P3 0xF0 ///< Cause PMC to turn on, off USB 3.3V rail
+#define IPC_SUBCMD_ID_USB3P3_OFF 0x00 ///< Turn off USB 3.3V rail
+#define IPC_SUBCMD_ID_USB3P3_ON 0x01 ///< Turn on USB 3.3V rail
+
+#define IPC_CMD_ID_BLACKLIST_SEL 0xEF ///< PMIC Blacklist Select IPC1
+#define IPC_SUBCMD_BLACKLIST_IAIns 0x00 ///< Use IA Insecure Blacklist to filter PMIC Accesses
+#define IPC_SUBCMD_BLACKLIST_IASec 0x02 ///< Use IA Secure Blacklist to filter PMIC Accesses
+
+#define IPC_CMD_ID_PMIC 0xFF ///< PMIC Register read and write
+#define IPC_SUBCMD_ID_PMIC_READ 0x00 ///< PMIC Register write
+#define IPC_SUBCMD_ID_PMIC_WRITE 0x01 ///< PMIC Register read
+#define IPC_SUBCMD_ID_PMIC_READ_MOD_WRITE 0x02 ///< PMIC Register read-modify-write
+
+#define INVALID_IPC_CMD 0x80000000
+
+typedef enum
+{
+ ipcStsCode_none = 0, ///< 0, No error
+ ipcStsCode_cmdNotSupported, ///< 1, IPC_CMD.CMD_ID is correct, but there is a problem in formatting of the other IPC_CMD fields. Example: wrong IPC_CMD.SIZE.
+ ipcStsCode_cmdNotServiced, ///< 2, IPC_CMD is correct, but service you asked for is permanently disabled (fused off, blacklisted, etc).
+ ipcStsCode_unableToServiceNow, ///< 3, IPC_CMD is correct, but PMC cannot service at this time. Example: command which can only be called once, or can only happen at a particular time.
+ ipcStsCode_cmdInvalid, ///< 4, IPC_CMD.CMD_ID is invalid
+ ipcStsCode_cmdFailed, ///< 5, Attempted to service the command, but it failed for some reason! Example: pmic access failed/timed out.
+} ipcStsCode_t;
+
+#pragma pack(1)
+typedef struct {
+ UINT16 Address;
+ UINT8 Value;
+} IPC_CMD_ID_PMIC_READ_WRITE_FORMAT;
+
+typedef struct {
+ UINT16 Address;
+ UINT8 Value;
+ UINT8 Mask;
+} IPC_CMD_ID_PMIC_READ_MODIFY_WRITE_FORMAT;
+
+typedef union {
+ IPC_CMD_ID_PMIC_READ_WRITE_FORMAT ReadWrite[5];
+ IPC_CMD_ID_PMIC_READ_MODIFY_WRITE_FORMAT ReadModifyWrite[4];
+ UINT32 Uint32[4];
+} IPC_CMD_ID_PMIC_BUFFER;
+#pragma pack()
+
+/**
+ Checks the IPC channel is available for a new request
+
+ @retval EFI_SUCCESS Ready for a new IPC
+ @retval EFI_NOT_READY Not ready for a new IPC
+
+**/
+RETURN_STATUS
+EFIAPI
+ReadyForNewIpc (
+ VOID
+ );
+
+/**
+ Sends an IPC from the x86 CPU to the PMC and waits for the PMC to process the
+ specified opcode.
+
+ @param[in] MessageId The message identifier to send in the IPC packet.
+
+**/
+RETURN_STATUS
+EFIAPI
+IpcSendCommand (
+ IN UINT32 MessageId
+ );
+
+/**
+ Sends an IPC from the x86 CPU to the PMC and waits for the PMC to process the
+ specified opcode.
+
+ @param[in] Command The Command identifier to send in the IPC packet.
+ @param[in] SubCommand The SubCommand identifier to send in the IPC packet.
+ @param[in, out] Buffer Pointer to buffer associated with MessageId. This is an optional
+ patrametert that may be NULL for some MessageId values.
+ @param[in, out] BufferSize The size, in bytes, of Buffer. Ignored if Buffer is NULL.
+
+**/
+RETURN_STATUS
+EFIAPI
+IpcSendCommandEx (
+ IN UINT32 Command,
+ IN UINT8 SubCommand,
+ IN OUT VOID *Buffer, OPTIONAL
+ IN OUT UINTN BufferSize
+ );
+
+/**
+ Sends an IPC from the x86 CPU to the PMC and waits for the PMC to process the
+ specified opcode.
+
+ !! Use it only when you are sure that IPC PCI config space is no longer valid !!
+
+ @param[in] PciBar0 PCI config BAR0 for IPC.
+ @param[in] Command The Command identifier to send in the IPC packet.
+ @param[in] SubCommand The SubCommand identifier to send in the IPC packet.
+ @param[in, out] Buffer Pointer to buffer associated with MessageId. This is an optional
+ patrametert that may be NULL for some MessageId values.
+ @param[in, out] BufferSize The size, in bytes, of Buffer. Ignored if Buffer is NULL.
+
+**/
+RETURN_STATUS
+EFIAPI
+IpcSendCommandBar0Ex (
+ IN UINT32 PciBar0,
+ IN UINT32 Command,
+ IN UINT8 SubCommand,
+ IN OUT VOID *Buffer, OPTIONAL
+ IN OUT UINTN BufferSize
+ );
+
+#endif // __BXT_PMC_IPC_LIB__
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SiPolicyLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SiPolicyLib.h new file mode 100644 index 0000000000..eacf179569 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SiPolicyLib.h @@ -0,0 +1,67 @@ +/** @file
+ Prototype of the SiPolicyLib library.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_LIB_H_
+#define _SI_POLICY_LIB_H_
+
+#include <Ppi/SiPolicyPpi.h>
+
+/**
+ Print whole SI_POLICY_PPI and serial out.
+
+ @param[in] SiPolicyPpi The RC Policy PPI instance
+
+**/
+VOID
+EFIAPI
+SiPrintPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ SiCreatePolicyDefaults creates the default setting of Silicon Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SiPolicyPpi The pointer to get Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SiCreatePolicyDefaults (
+ OUT SI_POLICY_PPI **SiPolicyPpi
+ );
+
+/**
+ SiInstallPolicyPpi installs SiPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+#endif // _PEI_SI_POLICY_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SideBandLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SideBandLib.h new file mode 100644 index 0000000000..1d8b828724 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SideBandLib.h @@ -0,0 +1,297 @@ +/** @file
+ Prototype of the SideBandLib library.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SB_LIB_H_
+#define _SB_LIB_H_
+
+/**
+ General SideBandLib Information
+
+ Note: IOSF-SideBand prior to v2.0 is not supported.
+
+ All future versions will be supported with backward support to v2.0. The latest
+ version supported is specified in VERSION_IOSF_SIDEBAND_SUPPORT.
+
+ Note: IOSF-SideBand access via MMIO is not valid prior to SBREG_BAR (P2SB BAR)
+ being set. By calling the generic SideBandRead() and SideBandWrite() library
+ functions, the appropriate method will be used based on SBREG_BAR availability.
+
+ In the case SBREG_BAR is not set, the SBMI (SideBand Message Interface) functions
+ will be used which read/write to SideBand using private PCI CFG registers in P2SB.
+
+**/
+
+#define VERSION_IOSF_SIDEBAND_SUPPORT 2.0 ///< Guaranteed IOSF-SideBand Supported Version
+
+//
+// Internal Library Defines
+//
+#define P2SB_SBI_ADDR 0xD0
+#define P2SB_SBI_DATA 0xD4
+#define P2SB_SBI_STAT 0xD8
+#define P2SB_SBI_RID 0xDA
+#define P2SB_SBI_EXTADDR 0xDC
+
+#define B_ADDR_DEST_PORT_MASK (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | \
+ BIT25 | BIT24)
+#define B_ADDR_OFFSET_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | \
+ BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | \
+ BIT2 | BIT1 | BIT0)
+#define B_ADDR_RSVD_MASK (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_ADDR_ROOT_MASK (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_STAT_INITIATE_MASK BIT0
+#define B_STAT_INITRDY_MASK BIT0
+#define B_STAT_OPCODE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | \
+ BIT9 | BIT8)
+#define B_STAT_POSTED_MASK BIT7
+#define B_STAT_RSVD_RESP (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1)
+#define V_INITIATE 0x01
+#define V_INITRDY 0x01
+#define V_OPCODE_CFGRD 0x04
+#define V_OPCODE_CFGWR 0x05
+#define V_OPCODE_CRRD 0x06
+#define V_OPCODE_CRWR 0x07
+#define V_OPCODE_IORD 0x02
+#define V_OPCODE_IOWR 0x03
+#define V_OPCODE_MRD 0x00
+#define V_OPCODE_MWR 0x01
+#define V_POSTED 0x01
+#define V_RID_FBE 0xF000
+#define V_RSVD_RESP 0x00
+#define V_RID_BAR_DBC 0x05
+
+//
+// Main SideBand Interface Functions
+//
+
+/**
+ Determines whether to call a SideBand read via MMIO or SBMI (MMCFG) based on whether
+ SBREG_REG is set up.
+
+ This is the standard Read function that should be used for SideBand transactions.
+
+ For MMIO Access:
+ In a single MMIO transaction, the "SBREG_BAR" is used
+ to form a system address to access chipset registers.
+ Transactions using this method will read using Private Control Register opcode CRRd(06h).
+ All accesses using this method must be DWORD aligned DWORDs.
+
+ For SBMI Access: Refer to SideBandSbmiRead32()
+
+ @param[in] TargetPortId Target port to read.
+ @param[in] TargetRegister Target register to read.
+
+ @retval UINT32 The value read from Target Register.
+
+**/
+UINT32
+EFIAPI
+SideBandRead32 (
+ IN UINT8 TargetPortId,
+ IN UINT16 TargetRegister
+ );
+
+/**
+ Determines whether to call a SideBand write via MMIO or SBMI (MMCFG) based on whether
+ SBREG_REG is set up.
+
+ This is the standard Write function that should be used for SideBand transactions.
+
+ For MMIO Access:
+ In a single MMIO transaction, the "SBREG_BAR" is used
+ to form a system address to access chipset registers.
+ Transactions using this method will write using Private Control Register opcode CRWr(07h).
+ All accesses using this method must be DWORD aligned DWORDs.
+ For SBMI Access: Refer to SideBandSbmiWrite32()
+
+ @param[in] TargetPortId Target port to write.
+ @param[in] TargetRegister Target register to write.
+ @param[in] Value The value to write.
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+SideBandWrite32 (
+ IN UINT8 TargetPortId,
+ IN UINT16 TargetRegister,
+ IN UINT32 Value
+ );
+
+/**
+ Determines whether to call SideBand operations via MMIO or SBMI (MMCFG) based on whether
+ SBREG_REG is set up.
+
+ This is the standard AndThenOr function that should be used for SideBand transactions.
+
+ Reads the value in the Target Register of the Target Port Id, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by AndData, and writes the
+ 32-bit value to the configuration register specified by Target Register.
+
+ @param[in] TargetPortId Target port to read/write.
+ @param[in] TargetRegister Target register to read/write.
+ @param[in] AndData The value to AND with Target Register data.
+ @param[in] OrData The value to OR with Target Register data.
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+SideBandAndThenOr32 (
+ IN UINT8 TargetPortId,
+ IN UINT16 TargetRegister,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+//
+// Special Case SideBand Interface Functions
+//
+
+/**
+ This function is reserved for special case sideband access:
+ Non-private control register opcode
+
+ In multiple MMIO transactions, this access method uses a mechanism provided in PCI
+ Configuration space to send IOSF-SB messages. This method should be used prior to
+ full PCI enumeration. Since multiple messages are sent this method is not thread-safe
+ but this is not an issue for single-threaded IAFW.
+
+ Transactions using this method will read using the OpCode parameter.
+
+ All accesses using this method must be DWORD aligned DWORDs.
+
+ @param[in] TargetPortId Target port to read.
+ @param[in] TargetRegister Target register to read.
+ @param[in] OpCode Opcode to use.
+ @param[in] Bar Target register access BAR.
+
+ @retval The value read from Target Register.
+
+**/
+UINT32
+EFIAPI
+SideBandReadReserved32 (
+ IN UINT8 TargetPortId,
+ IN UINT16 TargetRegister,
+ IN UINT8 OpCode,
+ IN UINT8 Bar
+ );
+
+/**
+ This function is reserved for special case sideband access:
+ Non-private control register opcode
+
+ In multiple MMIO transactions, this access method uses a mechanism provided in PCI
+ Configuration space to send IOSF-SB messages. This method should be used prior to
+ full PCI enumeration. Since multiple messages are sent this method is not thread-safe
+ but this is not an issue for single-threaded IAFW.
+
+ Transactions using this method will write using the OpCode parameter.
+
+ All accesses using this method must be DWORD aligned DWORDs.
+
+ @param[in] TargetPortId Target port to write.
+ @param[in] TargetRegister Target register to write.
+ @param[in] OpCode Opcode to use.
+ @param[in] Bar Target register access BAR.
+ @param[in] Value The value to write.
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+SideBandWriteReserved32 (
+ IN UINT8 TargetPortId,
+ IN UINT16 TargetRegister,
+ IN UINT8 OpCode,
+ IN UINT8 Bar,
+ IN UINT32 Value
+ );
+
+/**
+ This function is reserved for special case sideband access:
+ Non-private control register opcode
+
+ Reads the value in the Target Register of the Target Port Id, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by AndData, and writes the
+ 32-bit value to the configuration register specified by Target Register.
+
+ @param[in] TargetPortId Target port to read/write.
+ @param[in] TargetRegister Target register to read/write.
+ @param[in] ReadOpCode Opcode to use for read.
+ @param[in] WriteOpCode Opcode to use for write.
+ @param[in] Bar Target register access BAR.
+ @param[in] AndData The value to AND with Target Register data.
+ @param[in] OrData The value to OR with Target Register data.
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+SideBandAndThenOrReserved32 (
+ IN UINT8 TargetPortId,
+ IN UINT16 TargetRegister,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+//
+// Helper Functions
+//
+/**
+ Returns if SideBand access using MMIO is valid.
+
+ @param None.
+
+ @retval BOOLEAN Returns true if SideBand access via P2SB MMIO is valid else returns false
+
+**/
+BOOLEAN
+EFIAPI
+SideBandMmioValid (
+ VOID
+ );
+
+/**
+ Library utility function.
+
+ Returns the MMIO Address used to access the register over P2SB.
+
+ This function doesn't check if SB MMIO is enabled or not. Caller has to make sure
+ SB MMIO is enabled, this is exposed to meet timing constraints of SDQ protocol in less than 10us
+
+ @param[in] TargetPortId Target port.
+ @param[in] TargetRegister Target register
+
+ @retval UINT32 The MMIO address to access TargetRegister in TargetPortId with P2SB.
+
+**/
+UINT32
+EFIAPI
+GetSideBandMmioAddress (
+ IN UINT8 TargetPortId,
+ IN UINT16 TargetRegister
+ );
+
+#endif // _SB_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SteppingLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SteppingLib.h new file mode 100644 index 0000000000..c14911bba5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/SteppingLib.h @@ -0,0 +1,89 @@ +/** @file
+ Get Soc ID library implementation.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _STEPPING_LIB_H_
+#define _STEPPING_LIB_H_
+
+///
+/// BXT Series
+///
+typedef enum {
+ Bxt = 0x00,
+ Bxt1,
+ BxtX,
+ BxtP,
+ BxtSeriesMax = 0xFF
+} BXT_SERIES;
+
+///
+/// Silicon Steppings
+///
+typedef enum {
+ BxtA0 = 0x00,
+ BxtA1,
+ BxtB0 = 0x10,
+ BxtB1,
+ BxtB2,
+ BxtC0,
+ BxtXA0 = 0x20,
+ BxtPA0 = 0x40,
+ BxtPB0 = 0x50,
+ BxtPB1,
+ BxtPB2,
+ BxtSteppingMax = 0xFF
+} BXT_STEPPING;
+
+///
+/// BXT E0 FIB Types
+///
+typedef enum {
+ BxtHardFib = 0x00,
+ BxtSoftFib = 0x02,
+ BxtNoFib = 0xFF
+} BXT_FIB_TYPE;
+
+/**
+ Return SOC series type
+
+ @retval BXT_SERIES SOC series type
+
+**/
+BXT_SERIES
+EFIAPI
+GetBxtSeries (
+ VOID
+ );
+
+/**
+ This procedure will get Soc Stepping
+
+ @retval Soc Stepping
+
+**/
+
+BXT_STEPPING
+EFIAPI
+BxtStepping (
+ VOID
+ );
+
+BXT_FIB_TYPE
+EFIAPI
+GetFibType (
+ VOID
+ );
+
+#endif // _STEPPING_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/VariableNvmStorageLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/VariableNvmStorageLib.h new file mode 100644 index 0000000000..99d785c6d1 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/VariableNvmStorageLib.h @@ -0,0 +1,312 @@ +/** @file
+ Variable NVM Storage Helper library.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VARIABLE_NVM_STORAGE_LIB_H_
+#define _VARIABLE_NVM_STORAGE_LIB_H_
+
+#include <Uefi.h>
+#include <Guid/VariableFormat.h>
+#include <VariableNvmStorageFormat.h>
+
+/**
+ Returns a pointer of type VARIABLE_NVM_STORE_HEADER to a buffer containing
+ the header of an empty variable store.
+
+ @param[out] VarStoreHeader Pointer to the Variable Store Header.
+
+ @retval EFI_SUCCESS The variable store was created successfully.
+ @retval Others An error occurred creating the variable store.
+
+**/
+EFI_STATUS
+CreateEmptyVariableStore (
+ OUT VARIABLE_NVM_STORE_HEADER *VarStoreHeader
+ );
+
+/**
+ Gets the pointer to the first variable header in the given variable header region.
+
+ @param[in] VarStoreHeader Pointer to the Variable Store Header.
+
+ @return Pointer to the first variable header
+
+**/
+VARIABLE_NVM_HEADER *
+GetStartPointer (
+ IN VARIABLE_NVM_STORE_HEADER *VarStoreHeader
+ );
+
+/**
+ This code gets the pointer to the last variable header in the variable header region.
+
+ @param[in] VarStoreHeader Pointer to the Variable Store Header.
+
+ @return VARIABLE_NVM_HEADER* pointer to last unavailable Variable Header.
+
+**/
+VARIABLE_NVM_HEADER *
+GetEndPointer (
+ IN VARIABLE_NVM_STORE_HEADER *VarStoreHeader
+ );
+
+/**
+ This code checks if the variable header is valid or not.
+
+ @param[in] Variable Pointer to the Variable Header.
+ @param[in] VariableStoreEnd Pointer to the end of the Variable Store
+
+ @retval TRUE Variable header is valid.
+ @retval FALSE Variable header is not valid.
+
+**/
+BOOLEAN
+IsValidVariableHeader (
+ IN VARIABLE_NVM_HEADER *Variable,
+ IN VARIABLE_NVM_HEADER *VariableStoreEnd
+ );
+
+/**
+ This code checks if the variable header is valid or not.
+
+ @param[in] VarStoreHeader Pointer to the Variable Store Header.
+ @param[out] IsAuthenticatedStore Indicates whether this store is authenticated.
+
+ @retval EFI_SUCCESS The authenticated status of the store was successfully determined.
+ @retval EFI_INVALID_PARAMETER An invalid parameter was passed to the function.
+
+**/
+EFI_STATUS
+IsAuthenticatedVariableStore (
+ IN VARIABLE_NVM_STORE_HEADER *VarStoreHeader,
+ OUT BOOLEAN *IsAuthenticatedStore
+ );
+
+/**
+ This code gets the size of the variable header.
+
+ @param[in] AuthFlag Authenticated variable flag.
+
+ @return Size of variable header in bytes in type UINTN.
+
+**/
+UINTN
+GetVariableHeaderSize (
+ IN BOOLEAN AuthFlag
+ );
+
+/**
+ This code gets the size of the name of the variable.
+
+ @param[in] Variable Pointer to the Variable Header.
+ @param[in] AuthFlag Authenticated variable flag.
+
+ @return Size of variable in bytes in type UINTN.
+
+**/
+UINTN
+NameSizeOfVariable (
+ IN VARIABLE_NVM_HEADER *Variable,
+ IN BOOLEAN AuthFlag
+ );
+
+/**
+ This code gets the size of the variable data.
+
+ @param[in] Variable Pointer to the Variable Header.
+ @param[in] AuthFlag Authenticated variable flag.
+
+ @return Size of variable in bytes in type UINTN.
+
+**/
+UINTN
+DataSizeOfVariable (
+ IN VARIABLE_NVM_HEADER *Variable,
+ IN BOOLEAN AuthFlag
+ );
+
+/**
+ This code gets the pointer to the variable name.
+
+ @param[in] Variable Pointer to the Variable Header.
+ @param[in] AuthFlag Authenticated variable flag.
+
+ @return A CHAR16* pointer to Variable Name.
+
+**/
+CHAR16 *
+GetVariableNamePtr (
+ IN VARIABLE_NVM_HEADER *Variable,
+ IN BOOLEAN AuthFlag
+ );
+
+/**
+ This code gets the pointer to the variable guid.
+
+ @param[in] Variable Pointer to the Variable Header.
+ @param[in] AuthFlag Authenticated variable flag.
+
+ @return A EFI_GUID* pointer to Vendor Guid.
+
+**/
+EFI_GUID *
+GetVendorGuidPtr (
+ IN VARIABLE_NVM_HEADER *Variable,
+ IN BOOLEAN AuthFlag
+ );
+
+/**
+ This code gets the pointer to the variable data.
+
+ This is an "offset" that is interpreted as needed based on the caller's requirements.
+
+ @param[in] Variable Pointer to the Variable Header.
+ @param[in] StoreInfo Pointer to a Variable Store Info structure for this variable.
+
+ @return A UINT32 value representing the offset to the variable data.
+
+**/
+UINT32
+GetVariableDataPtr (
+ IN VARIABLE_NVM_HEADER *Variable,
+ IN VARIABLE_NVM_STORE_INFO *StoreInfo
+ );
+
+/**
+ This code gets the pointer to the next variable header.
+
+ @param[in] StoreInfo Pointer to variable store info structure.
+ @param[in] VariableHeader Pointer to the Variable Header.
+
+ @return A VARIABLE_NVM_HEADER* pointer to next variable header.
+
+**/
+VARIABLE_NVM_HEADER *
+GetNextVariablePtr (
+ IN VARIABLE_NVM_STORE_INFO *StoreInfo,
+ IN VARIABLE_NVM_HEADER *VariableHeader
+ );
+
+/**
+ Get variable store status.
+
+ @param[in] VarStoreHeader Pointer to the Variable Store Header.
+
+ @retval EfiRaw Variable store is raw
+ @retval EfiValid Variable store is valid
+ @retval EfiInvalid Variable store is invalid
+
+**/
+VARIABLE_STORE_STATUS
+GetVariableStoreStatus (
+ IN VARIABLE_NVM_STORE_HEADER *VarStoreHeader
+ );
+
+/**
+ Compare two variable names.
+
+ @param[in] StoreInfo Pointer to variable store info structure.
+ @param[in] Name1 Pointer to one variable name.
+ @param[in] Name2 Pointer to another variable name.
+ @param[in] NameSize Variable name size.
+
+ @retval TRUE Name1 and Name2 are identical.
+ @retval FALSE Name1 and Name2 are not identical.
+
+**/
+BOOLEAN
+CompareVariableName (
+ IN VARIABLE_NVM_STORE_INFO *StoreInfo,
+ IN CONST CHAR16 *Name1,
+ IN CONST CHAR16 *Name2,
+ IN UINTN NameSize
+ );
+
+/**
+ This function compares a variable with the variable entry in the database.
+
+ @param[in] StoreInfo Pointer to variable store info structure.
+ @param[in] Variable Pointer to the variable in our database
+ @param[in] VariableHeader Pointer to the Variable Header that has consecutive content.
+ @param[in] VariableName Name of the variable to compare to 'Variable'
+ @param[in] VendorGuid GUID of the variable to compare to 'Variable'
+ @param[out] PtrTrack Variable Track Pointer structure that contains Variable Information.
+
+ @retval EFI_SUCCESS Found match variable
+ @retval EFI_NOT_FOUND Variable not found
+
+**/
+EFI_STATUS
+CompareWithValidVariable (
+ IN VARIABLE_NVM_STORE_INFO *StoreInfo,
+ IN VARIABLE_NVM_HEADER *Variable,
+ IN VARIABLE_NVM_HEADER *VariableHeader,
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VendorGuid,
+ OUT VARIABLE_NVM_POINTER_TRACK *PtrTrack
+ );
+
+/**
+ Validate the provided variable header.
+
+ @param[in] StoreInfo Pointer to variable store info structure.
+ @param[in] Variable Pointer to the Variable Header.
+ @param[out] VariableHeader Pointer to Pointer to the Variable Header that has consecutive content.
+
+ @retval TRUE Variable header is valid.
+ @retval FALSE Variable header is not valid.
+
+**/
+BOOLEAN
+GetVariableHeader (
+ IN VARIABLE_NVM_STORE_INFO *StoreInfo,
+ IN VARIABLE_NVM_HEADER *Variable,
+ OUT VARIABLE_NVM_HEADER **VariableHeader
+ );
+
+/**
+ Copy the variable name to the output buffer.
+
+ @param[in] StoreInfo Pointer to variable store info structure.
+ @param[in] NameOrData Pointer to the variable name/data that may not be consecutive.
+ @param[in] Size Variable name/data size.
+ @param[out] Buffer Pointer to output buffer to hold the variable name/data.
+
+**/
+VOID
+GetVariableName (
+ IN VARIABLE_NVM_STORE_INFO *StoreInfo,
+ IN UINT8 *Name,
+ IN UINTN Size,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Compares two EFI_TIME data structures.
+
+ @param[in] FirstTime A pointer to the first EFI_TIME data.
+ @param[in] SecondTime A pointer to the second EFI_TIME data.
+
+ @retval TRUE The FirstTime is not later than the SecondTime.
+ @retval FALSE The FirstTime is later than the SecondTime.
+
+**/
+BOOLEAN
+VariableNvmCompareTimeStamp (
+ IN EFI_TIME *FirstTime,
+ IN EFI_TIME *SecondTime
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/VariableStorageSelectorLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/VariableStorageSelectorLib.h new file mode 100644 index 0000000000..a52c519cc5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/VariableStorageSelectorLib.h @@ -0,0 +1,47 @@ +/** @file
+ Variable Storage Selector Library.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VARIABLE_STORAGE_SELECTOR_LIB_H_
+#define _VARIABLE_STORAGE_SELECTOR_LIB_H_
+
+#include <Uefi.h>
+
+/**
+ Gets the variable storage instance ID for the variable storage instance
+ that is used to store a given variable
+
+ @param[in] VariableName A pointer to a null-terminated string that is
+ the variable's name.
+ @param[in] VariableGuid A pointer to an EFI_GUID that is the variable's
+ GUID. The combination of VariableGuid and
+ VariableName must be unique.
+ @param[in] AtDxe True if in DXE. False if in PEI.
+ @param[out] VariableStorageId The ID for the variable storage instance that
+ stores a given variable
+
+ @retval EFI_SUCCESS Variable storage instance id was retrieved
+
+**/
+EFI_STATUS
+EFIAPI
+GetVariableStorageId (
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VendorGuid,
+ IN BOOLEAN AtDxe,
+ OUT EFI_GUID *VariableStorageId
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/PcieRegs.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/PcieRegs.h new file mode 100644 index 0000000000..6126f94c85 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/PcieRegs.h @@ -0,0 +1,276 @@ +/** @file
+ Register names for PCIE standard register.
+
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCIE_REGS_H_
+#define _PCIE_REGS_H_
+
+#include <IndustryStandard/Pci30.h>
+
+//
+// PCI type 0 Header
+//
+#define R_PCI_PI_OFFSET 0x09
+#define R_PCI_SCC_OFFSET 0x0A
+#define R_PCI_BCC_OFFSET 0x0B
+
+//
+// PCI type 1 Header
+//
+#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Register
+#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordinate Bus Number
+#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondary Bus Number
+#define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary Bus Number
+#define B_PCI_BRIDGE_BNUM_SBBN_SCBN (B_PCI_BRIDGE_BNUM_SBBN | B_PCI_BRIDGE_BNUM_SCBN)
+
+#define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and Limit Register
+
+#define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base and Limit Register
+#define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory Limit
+#define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory Base
+
+#define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable Memory Base and Limit Register
+#define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///< Prefetchable Memory Limit
+#define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit Indicator
+#define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///< Prefetchable Memory Base
+#define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit Indicator
+
+#define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable Memory Base Upper 32-Bit Register
+#define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF
+
+#define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable Memory Limit Upper 32-Bit Register
+#define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF
+
+//
+// PCIE capabilities register
+//
+#define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID
+#define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capability Capability ID Pointer
+
+//
+// PCI Express Capability List Register (CAPID:10h)
+//
+#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Capabilities Register (Offset 02h)
+#define S_PCIE_XCAP 2
+#define B_PCIE_XCAP_SI BIT8 ///< Slot Implemented
+#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
+#define N_PCIE_XCAP_DT 4
+
+#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabilities Register (Offset 04h)
+#define S_PCIE_DCAP 4
+#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptable Latency
+#define N_PCIE_DCAP_E1AL 9
+#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable Latency
+#define N_PCIE_DCAP_E0AL 6
+#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Supported
+
+#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control Register (Offset 08h)
+#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size
+#define N_PCIE_DCTL_MPS 5
+#define B_PCIE_DCTL_URE BIT3 ///< Unsupported Request Reporting Enable
+#define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Reporting Enable
+#define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Error Reporting Enable
+#define B_PCIE_DCTL_CEE BIT0 ///< Correctable Error Reporting Enable
+
+#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilities Register (Offset 0Ch)
+#define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optionality Compliance
+#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power Management
+#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///< L1 Exit Latency
+#define N_PCIE_LCAP_EL1 15
+#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///< L0s Exit Latency
+#define N_PCIE_LCAP_EL0 12
+#define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Active State Power Management (ASPM) Support
+#define B_PCIE_LCAP_APMS_L0S BIT10
+#define B_PCIE_LCAP_APMS_L1 BIT11
+#define N_PCIE_LCAP_APMS 10
+#define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum Link Width
+#define N_PCIE_LCAP_MLW 4
+#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed
+#define V_PCIE_LCAP_MLS_GEN3 3
+
+#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control Register (Offset 10h)
+#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock Power Management
+#define B_PCIE_LCTL_ES BIT7 ///< Extended Synch
+#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration
+#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link
+#define B_PCIE_LCTL_LD BIT4 ///< Link Disable
+#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Active State Power Management (ASPM) Control
+#define V_PCIE_LCTL_ASPM_L0S 1
+#define V_PCIE_LCTL_ASPM_L1 2
+#define V_PCIE_LCTL_ASPM_L0S_L1 3
+
+#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Register (Offset 12h)
+#define B_PCIE_LSTS_LA BIT13 ///< Data Link Layer Link Active
+#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Configuration
+#define B_PCIE_LSTS_LT BIT11 ///< Link Training
+#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated Link Width
+#define N_PCIE_LSTS_NLW 4
+#define V_PCIE_LSTS_NLW_1 0x0010
+#define V_PCIE_LSTS_NLW_2 0x0020
+#define V_PCIE_LSTS_NLW_4 0x0040
+#define B_PCIE_LSTS_CLS 0x000F ///< Current Link Speed
+#define V_PCIE_LSTS_CLS_GEN1 1
+#define V_PCIE_LSTS_CLS_GEN2 2
+#define V_PCIE_LSTS_CLS_GEN3 3
+
+#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilities Register (Offset 14h)
+#define S_PCIE_SLCAP 4
+#define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical Slot Number
+#define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Power Limit Scale
+#define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Power Limit Value
+#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable
+#define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surprise
+
+#define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control Register (Offset 18h)
+#define S_PCIE_SLCTL 2
+#define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Interrupt Enable
+#define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detect Changed Enable
+
+#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Register (Offset 1Ah)
+#define S_PCIE_SLSTS 2
+#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State
+#define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detect Changed
+
+#define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control Register (Offset 1Ch)
+#define S_PCIE_RCTL 2
+#define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt Enable
+#define B_PCIE_RCTL_SFE BIT2 ///< System Error on Fatal Error Enable
+#define B_PCIE_RCTL_SNE BIT1 ///< System Error on Non-Fatal Error Enable
+#define B_PCIE_RCTL_SCE BIT0 ///< System Error on Correctable Error Enable
+
+#define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Register (Offset 20h)
+#define S_PCIE_RSTS 4
+
+#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabilities 2 Register (Offset 24h)
+#define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBFF Supported
+#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported
+
+#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control 2 Register (Offset 28h)
+#define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBFF Enable
+#define N_PCIE_DCTL2_OBFFEN 13
+#define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled
+#define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using WAKE# signaling
+#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism Enable
+#define B_PCIE_DCTL2_CTD BIT4 ///< Completion Timeout Disable
+#define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0) ///< Completion Timeout Value
+#define V_PCIE_DCTL2_CTV_DEFAULT 0x0
+#define V_PCIE_DCTL2_CTV_40MS_50MS 0x5
+#define V_PCIE_DCTL2_CTV_160MS_170MS 0x6
+#define V_PCIE_DCTL2_CTV_400MS_500MS 0x9
+#define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA
+
+#define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2 Register (Offset 30h)
+#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed
+#define V_PCIE_LCTL2_TLS_GEN1 1
+#define V_PCIE_LCTL2_TLS_GEN2 2
+#define V_PCIE_LCTL2_TLS_GEN3 3
+
+//
+// PCI Power Management Capability (CAPID:01h)
+//
+#define R_PCIE_PMC_OFFSET 0x02 ///< Power Management Capabilities Register
+#define S_PCIE_PMC 2
+#define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) ///< PME Support
+#define B_PCIE_PMC_PMEC BIT3 ///< PME Clock
+
+#define R_PCIE_PMCS_OFFST 0x04 ///< Power Management Status/Control Register
+#define S_PCIE_PMCS 4
+#define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clock Control Enable
+#define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support
+#define B_PCIE_PMCS_PMES BIT15 ///< PME_Status
+#define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable
+#define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset
+#define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power State
+#define V_PCIE_PMCS_PS_D0 0
+#define V_PCIE_PMCS_PS_D3H 3
+
+//
+// PCIE Extension Capability Register
+//
+#define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next Capability Offset
+#define N_PCIE_EXCAP_NCO 20
+#define V_PCIE_EXCAP_NCO_LISTEND 0
+#define B_PCIE_EXCAP_CV 0x000F0000 ///< Capability Version
+#define N_PCIE_EXCAP_CV 16
+#define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capability ID
+
+//
+// Advanced Error Reporting Capability (CAPID:0001h)
+//
+#define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID
+#define R_PCIE_EX_UEM_OFFSEST 0x08 ///< Uncorrectable Error Mask Register
+#define B_PCIE_EX_UEM_CT BIT14 ///< Completion Timeout Mask
+
+//
+// ACS Extended Capability (CAPID:000Dh)
+//
+#define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID
+#define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability Register
+//#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control Register (NOTE: register size in PCIE spce is not match the PCH register size)
+
+//
+// Secondary PCI Express Extended Capability Header (CAPID:0019h)
+//
+#define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID
+#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3 Register
+#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equalization
+#define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan 1 Equalization Control Register (Offset 0Ch)
+#define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream Port Lane 1 Transmitter Preset
+#define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///< Downstream Port Lane 1 Transmitter Preset
+#define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream Port Transmitter Preset
+#define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///< Downstream Port Transmitter Preset
+#define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lane 3 Equalization Control Register (Offset 10h)
+#define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream Port Lane 3 Transmitter Preset
+#define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///< Downstream Port Lane 3 Transmitter Preset
+#define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream Port Lane 2 Transmitter Preset
+#define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///< Downstream Port Lane 2 Transmitter Preset
+
+//
+// L1 Sub-States Extended Capability Register (CAPID:001Eh)
+//
+#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID
+#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States Capabilities
+#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States Control 1
+#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States Control 2
+#define N_PCIE_EX_L1SCTL2_POWT 3
+
+//
+// PTM Extended Capability Register (CAPID:001Fh)
+//
+#define V_PCIE_EX_PTM_CID 0x001F ///< Capability ID
+#define R_PCIE_EX_PTMCAPR_OFFSET 0x04 ///< PTM Capabilities
+#define B_PCIE_EX_PTMCAPR_PTMRC BIT2 ///< PTM Root Capable
+#define B_PCIE_EX_PTMCAPR_PTMRSPC BIT1 ///< PTM Responder Capable
+#define R_PCIE_EX_PTMCTLR_OFFSET 0x08 ///< PTM Control Register
+
+//
+// Base Address Offset
+//
+#define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address Register 0
+#define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address Register 1
+#define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address Register 2
+#define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address Register 3
+#define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address Register 4
+#define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address Register 5
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/BiosReservedMemory.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/BiosReservedMemory.h new file mode 100644 index 0000000000..b53210a11e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/BiosReservedMemory.h @@ -0,0 +1,47 @@ +/** @file
+ Common header file shared by all source files.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __BIOS_RESERVED_MEMORY_H__
+#define __BIOS_RESERVED_MEMORY_H__
+
+//
+// BIOS reserved memory config
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Pram;
+} BIOS_RESERVED_MEMORY_CONFIG;
+
+#pragma pack()
+
+typedef struct _PEI_BIOS_RESERVED_MEMORY_POLICY_PPI PEI_BIOS_RESERVED_MEMORY_POLICY_PPI;
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_BIOS_RESERVED_MEMORY_POLICY) (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BIOS_RESERVED_MEMORY_POLICY_PPI *This,
+ IN OUT BIOS_RESERVED_MEMORY_CONFIG *BiosReservedMemoryPolicy
+ );
+
+typedef struct _PEI_BIOS_RESERVED_MEMORY_POLICY_PPI {
+ GET_BIOS_RESERVED_MEMORY_POLICY GetBiosReservedMemoryPolicy;
+} PEI_BIOS_RESERVED_MEMORY_POLICY_PPI;
+
+extern EFI_GUID gBiosReservedMemoryPolicyPpiGuid;
+
+#endif //__BIOS_RESERVED_MEMORY_H__
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h new file mode 100644 index 0000000000..0d9b1d6e01 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h @@ -0,0 +1,72 @@ +/** @file
+ Dram Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DRAM_POLICY_PPI_H_
+#define _DRAM_POLICY_PPI_H_
+
+#define DRAM_POLICY_NUMBER_CHANNELS 4
+#define DRAM_POLICY_NUMBER_BITS 32
+#define DRAM_POLICY_NUMBER_SPD_ADDRESSES 2
+
+#pragma pack(push,1)
+
+typedef struct {
+ UINT8 RankEnable;
+ UINT8 DeviceWidth;
+ UINT8 DramDensity;
+ UINT8 Option;
+ UINT8 OdtConfig;
+ UINT8 TristateClk1;
+ UINT8 Mode2N;
+ UINT8 OdtLevels;
+} DRP_DRAM_POLICY;
+
+typedef struct {
+ UINT8 Package;
+ UINT8 Profile;
+ UINT8 MemoryDown;
+ UINT8 DDR3LPageSize;
+ UINT8 DDR3LASR;
+ EFI_PHYSICAL_ADDRESS MrcTrainingDataPtr;
+ EFI_PHYSICAL_ADDRESS MrcBootDataPtr;
+ UINT8 ScramblerSupport;
+ UINT16 ChannelHashMask;
+ UINT16 SliceHashMask;
+ UINT8 InterleavedMode;
+ UINT8 ChannelsSlicesEnabled; /// bit0 = SliceEnabled; bit1 = channelEnabled
+ UINT8 MinRefRate2xEnabled;
+ UINT8 DualRankSupportEnabled;
+ UINT16 SystemMemorySizeLimit;
+ UINT16 LowMemMaxVal;
+ UINT16 HighMemMaxVal;
+ UINT8 DisableFastBoot;
+ UINT8 RmtMode;
+ UINT8 RmtCheckRun;
+ UINT16 RmtMarginCheckScaleHighThreshold;
+ UINT32 MsgLevelMask;
+ UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];
+ UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
+ DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS];
+ UINT8 DebugMsgLevel;
+ UINT8 reserved[13];
+} DRAM_POLICY_PPI;
+
+#pragma pack(pop)
+
+extern EFI_GUID gDramPolicyPpiGuid;
+
+#endif // _DRAM_POLICY_PPI_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/ReadOnlyVariablePreMemoryDescriptorPpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/ReadOnlyVariablePreMemoryDescriptorPpi.h new file mode 100644 index 0000000000..05fa80fe9a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/ReadOnlyVariablePreMemoryDescriptorPpi.h @@ -0,0 +1,29 @@ +/** @file
+ This file declares the Read Only Variable Pre-Memory Descriptor PPI
+ This PPI stores the descriptor address for the readonly variable PPI.
+ When the PPI is shadowed into permanent memory a unique instance of
+ READ_ONLY_VARIABLE2_PPI can be discovered using this PPI.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_READ_ONLY_VARIABLE_PRE_MEMORY_DESC_PPI_H_
+#define _PEI_READ_ONLY_VARIABLE_PRE_MEMORY_DESC_PPI_H_
+
+extern EFI_GUID gReadOnlyVariablePreMemoryDescriptorPpiGuid;
+
+typedef struct {
+ EFI_PEI_PPI_DESCRIPTOR *PreMemoryDescriptor;
+} READ_ONLY_VARIABLE_PRE_MEMORY_DESCRIPTOR_PPI;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/SiPolicyPpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/SiPolicyPpi.h new file mode 100644 index 0000000000..f50bb30972 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/SiPolicyPpi.h @@ -0,0 +1,29 @@ +/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include <SiPolicy.h>
+
+extern EFI_GUID gSiPolicyPpiGuid;
+
+typedef struct _SI_POLICY SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/VariableStoragePpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/VariableStoragePpi.h new file mode 100644 index 0000000000..5339f6b938 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/VariableStoragePpi.h @@ -0,0 +1,135 @@ +/** @file
+ This file declares the Variable Storage PPI
+ This PPI abstracts read-only access to the UEFI variable store on a
+ NVM (Non-Volatile Memory) device during the PEI phase.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_VARIABLE_STORAGE_PPI_H_
+#define _PEI_VARIABLE_STORAGE_PPI_H_
+
+extern EFI_GUID gVariableStoragePpiGuid;
+
+///
+/// Revision
+///
+#define PEI_VARIABLE_STORAGE_PPI_REVISION 1
+
+typedef struct _VARIABLE_STORAGE_PPI VARIABLE_STORAGE_PPI;
+
+/**
+ Retrieves a PPI instance-specific GUID.
+ Returns a unique GUID per VARIABLE_STORAGE_PPI instance.
+
+ @param[out] VariableGuid A pointer to an EFI_GUID that is this PPI instance's GUID.
+
+ @retval EFI_SUCCESS The data was returned successfully.
+ @retval EFI_INVALID_PARAMETER A required parameter is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_VARIABLE_STORAGE_GET_ID)(
+ OUT EFI_GUID *InstanceGuid
+ );
+
+/**
+ This service retrieves a variable's value using its name and GUID.
+
+ Read the specified variable from the UEFI variable store. If the Data
+ buffer is too small to hold the contents of the variable,
+ the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
+ required buffer size to obtain the data.
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PPI.
+ @param[in] VariableName A pointer to a null-terminated string that is the variable's name.
+ @param[in] VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of
+ VariableGuid and VariableName must be unique.
+ @param[out] Attributes If non-NULL, on return, points to the variable's attributes.
+ @param[in, out] DataSize On entry, points to the size in bytes of the Data buffer.
+ On return, points to the size of the data returned in Data.
+ @param[out] Data Points to the buffer which will hold the returned variable value.
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable could not be found.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data.
+ DataSize is updated with the size required for
+ the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_VARIABLE_STORAGE_GET_VARIABLE)(
+ IN CONST VARIABLE_STORAGE_PPI *This,
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VariableGuid,
+ OUT UINT32 *Attributes,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data
+ );
+
+/**
+ Return the next variable name and GUID.
+
+ This function is called multiple times to retrieve the VariableName
+ and VariableGuid of all variables currently available in the system.
+ On each call, the previous results are passed into the interface,
+ and, on return, the interface returns the data for the next
+ interface. When the entire variable list has been returned,
+ EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PPI.
+
+ @param[in, out] VariableNameSize On entry, points to the size of the buffer pointed to by
+ VariableName. On return, the size of the variable name buffer.
+ @param[in, out] VariableName On entry, a pointer to a null-terminated string that is the
+ variable's name. On return, points to the next variable's
+ null-terminated name string.
+ @param[in, out] VariableGuid On entry, a pointer to an EFI_GUID that is the variable's GUID.
+ On return, a pointer to the next variable's GUID.
+ @param[out] VariableAttributes A pointer to the variable attributes.
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable could not be found.
+ @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the resulting
+ data. VariableNameSize is updated with the size
+ required for the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid or
+ VariableNameSize is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_VARIABLE_STORAGE_GET_NEXT_VARIABLE_NAME)(
+ IN CONST VARIABLE_STORAGE_PPI *This,
+ IN OUT UINTN *VariableNameSize,
+ IN OUT CHAR16 *VariableName,
+ IN OUT EFI_GUID *VariableGuid,
+ OUT UINT32 *VariableAttributes
+ );
+
+///
+/// Variable Storage PPI
+/// Interface functions for variable NVM storage access in PEI phase.
+///
+struct _VARIABLE_STORAGE_PPI {
+ PEI_VARIABLE_STORAGE_GET_ID GetId; ///< Retrieves a PPI instance-specific GUID
+ PEI_VARIABLE_STORAGE_GET_VARIABLE GetVariable; ///< Retrieves a variable's value given its name and GUID
+ PEI_VARIABLE_STORAGE_GET_NEXT_VARIABLE_NAME GetNextVariableName; ///< Return the next variable name and GUID
+};
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageLib.h new file mode 100644 index 0000000000..34100b83ab --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageLib.h @@ -0,0 +1,325 @@ +/** @file
+ CSE Variable Storage Library.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CSE_VARIABLE_STORAGE_LIB_H_
+#define _CSE_VARIABLE_STORAGE_LIB_H_
+
+#include <Base.h>
+#include <Uefi.h>
+#include <VariableNvmStorageFormat.h>
+
+#define CSE_VARIABLE_NVM_ALIGNMENT 16
+#define CSE_MAX_NVM_FILE_NAME_LENGTH 48
+#define CSE_PRIMARY_NVM_MAX_DATA_FILES 256
+
+// Temp Dev Note (@todo) - Make the maximums below a PCD
+#define CSE_MAX_FILE_DATA_SIZE SIZE_64KB
+
+#define CSE_PRE_MEMORY_FILE_MAX_STORE_SIZE (SIZE_64KB - SIZE_16KB)
+#define CSE_PRIMARY_NVM_MAX_STORE_SIZE SIZE_512KB
+
+#define CSE_PRIMARY_NVM_DATA_FILE_PREFIX "NVS/VAR_"
+
+#define CSE_PRE_MEMORY_FILE_STORE_OFFSET 0
+#define CSE_PRIMARY_NVM_FILE_STORE_OFFSET 0
+
+//
+// Variable store file options provided by CSE (platform specific)
+//
+typedef enum {
+ CseVariableFileTypePreMemoryFile, ///< A special file available in pre-memory
+ CseVariableFileTypePrimaryIndexFile, ///< The primary store on CSE NVM
+ CseVariableFileTypeMax ///< End of CSE variable store file types
+} CSE_VARIABLE_FILE_TYPE;
+
+typedef enum {
+ CseVariableHeci1Protocol, ///< HECI1 protocol
+ CseVariableHeci2Protocol ///< HECI2 protocol
+} CSE_VARIABLE_HECI_PROTOCOL;
+
+#pragma pack(push, 1)
+
+typedef struct {
+ BOOLEAN FileEnabled; ///< Indicates if the file is enabled (used for variable storage)
+ BOOLEAN FileStoreEstablished; ///< Indicates whether the CSE NVM variable store has been established.
+ UINT32 FileStoreMaximumSize; ///< The maximum size of this variable store
+ CHAR8 *FileName; ///< Name of the CSE NVM file
+ EFI_GUID *IndexFileDataGuid; ///< Pointer to the GUID of the HOB that contains the index file data read in PEI for this variable store
+ EFI_PHYSICAL_ADDRESS HeaderRegionBase; ///< Memory address of the base of the variable header region
+ ///< kept in memory to search for variables.
+} CSE_VARIABLE_FILE_INFO;
+
+#pragma pack(pop)
+
+/**
+ Prints bytes in a buffer.
+ Temp Dev Note: Only used for temporary testing.
+
+ @param[in] Data8 A pointer to the memory buffer to print.
+ @param[in] DataSize The size of data to print from the buffer.
+
+ @retval None
+
+**/
+VOID
+TemporaryDebugDumpBufferData (
+ IN UINT8 *Data8,
+ IN UINTN DataSize
+ );
+
+/**
+ Creates variable stores if in DXE and necessary. Loads the variable data region
+ from CSE NVM needed to find variables.
+
+ @param[in,out] CseVariableFileInfo A pointer to a structure that contains information the CSE files available.
+ @param[in] AtDxeRuntime Determines how this function should allocate memory.
+ Caller passes TRUE if in DXE and FALSE for pre-DXE (PEI).
+
+ @retval EFI_SUCCESS The variable store was established successfully.
+ @retval Others The variable store could not be established.
+
+**/
+EFI_STATUS
+EFIAPI
+EstablishAndLoadCseVariableStores (
+ IN OUT CSE_VARIABLE_FILE_INFO **CseVariableFileInfo,
+ IN BOOLEAN AtDxeRuntime
+ );
+
+/**
+ Initializes the global variable structures for CSE storage modules.
+
+ @param[in] AtDxeRuntime Determines how this function should allocate memory.
+ Caller passes TRUE if in DXE and FALSE for pre-DXE (PEI).
+
+ @retval EFI_SUCCESS The global variables were initialized successfully.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory resources needed for allocation were available.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCseStorageGlobalVariableStructures (
+ IN OUT CSE_VARIABLE_FILE_INFO **CseVariableFileInfo,
+ IN BOOLEAN AtDxeRuntime
+ );
+
+/**
+ Returns the next available variable in the given CSE variable stores.
+
+ @param[in] VariableName Pointer to variable name.
+ @param[in] VendorGuid Variable Vendor Guid.
+ @param[in] CseVariableFileInfo A pointer to a structure that contains information the CSE files available.
+ @param[out] VariablePtr Pointer to variable header address.
+ @param[out] IsAuthVariable Indicates if the variable returned is an authenticated variable.
+
+ @retval EFI_SUCCESS Found the specified variable.
+ @retval EFI_NOT_FOUND Not found.
+
+**/
+EFI_STATUS
+EFIAPI
+GetNextCseVariableName (
+ IN CHAR16 *VariableName,
+ IN EFI_GUID *VariableGuid,
+ IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo,
+ OUT VARIABLE_NVM_HEADER **VariablePtr,
+ OUT BOOLEAN *IsAuthVariable
+ );
+
+/**
+ Reads data from a CSE NVM file into a specified memory buffer.
+
+ @param[in] CseFileName The name of the CSE file used in the read operation.
+ @param[in] FileOffset The offset to begin reading in the CSE file.
+ @param[out] Data A pointer to a buffer that is the destination for the read.
+ @param[out] DataSize The length in bytes of data to read from the file.
+ @param[in] HeciProtocolSelector The HECI protocol to use to write the file.
+ If not specified, the protocol will be determined internally.
+
+ @retval EFI_SUCCESS The file was read successfully.
+ @retval Others An error occurred reading the file.
+
+**/
+EFI_STATUS
+EFIAPI
+ReadCseNvmFile (
+ IN CHAR8 *CseFileName,
+ IN UINT32 FileOffset,
+ OUT UINT8 *Data,
+ OUT UINTN *DataSize,
+ IN CSE_VARIABLE_HECI_PROTOCOL *HeciProtocolSelector OPTIONAL
+ );
+
+/**
+ Writes data in a memory buffer to a specified CSE NVM file.
+
+ @param[in] CseFileName The name of the CSE file used in the write operation.
+ @param[in] FileOffset The offset to begin writing in the CSE file.
+ @param[in] Data A pointer to a buffer of data to write to the file.
+ @param[in] DataSize The length in bytes of data to write to the file.
+ @param[in] HeciProtocolSelector The HECI protocol to use to write the file.
+ If not specified, the protocol will be determined internally.
+ @param[in] Truncate If true, the file will be truncated.
+
+ @retval EFI_SUCCESS The file was updated successfully.
+ @retval Others An error occurred updating the file.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateCseNvmFile (
+ IN CHAR8 *CseFileName,
+ IN UINT32 FileOffset,
+ IN UINT8 *Data,
+ IN UINTN DataSize,
+ IN BOOLEAN Truncate,
+ IN CSE_VARIABLE_HECI_PROTOCOL *HeciProtocolSelector OPTIONAL
+ );
+
+/**
+ Creates an empty variable store on the CSE NVM file specified.
+
+ @param[in] StoreFileName A pointer to the string representing the CSE file name containing this store.
+ @param[in] Offset The offset from the beginning of the CSE NVM file to the first byte of the store.
+ @param[out] StoreSize The size of the variable store created / found will be written to this pointer.
+
+ @retval EFI_SUCCESS The variable store was created successfully.
+ @retval Others The variable store could not be created.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateCseNvmVariableStore (
+ IN CHAR8 *StoreFileName,
+ IN UINT32 Offset,
+ OUT UINTN *StoreSize
+ );
+
+/**
+ Returns the file name for a CSE data file at the specified offset (file number).
+
+ @param[in] DataOffset The file number on CSE NVM (each data file is an "offset")
+ @param[out] CseVariableDataFileName The CSE file name.
+
+ @retval EFI_INVALID_PARAMETER A valid buffer was not passed to fill with the file name.
+ @retval EFI_SUCCESS File name was successfully created and copied to the buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+BuildCseDataFileName (
+ IN UINT32 DataOffset,
+ OUT CHAR8 *CseVariableDataFileName
+ );
+
+/**
+ Finds the variable in CSE NVM.
+ This code finds the variable in the CSE NVM variable stores enabled.
+
+ If VariableName is an empty string, then we just return the first
+ qualified variable without comparing VariableName and VendorGuid.
+
+ @param[in] VariableName Name of the variable to be found.
+ @param[in] VendorGuid Vendor GUID to be found.
+ @param[in] CseVariableFileInfo A pointer to an array of structures that contains information the CSE files available.
+ @param[out] PtrTrack VARIABLE_NVM POINTER_TRACK structure for output,
+ including the range searched and the target position.
+
+ @retval EFI_INVALID_PARAMETER If VariableName is not an empty string, while
+ VendorGuid is NULL.
+ @retval EFI_SUCCESS Variable successfully found.
+ @retval EFI_NOT_FOUND Variable not found
+
+**/
+EFI_STATUS
+EFIAPI
+FindVariable (
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VendorGuid,
+ IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo,
+ OUT VARIABLE_NVM_POINTER_TRACK *VariablePtrTrack
+ );
+
+/**
+ Finds deleted variables in the specified CSE NVM variable store.
+
+ If VariableName is an empty string, then we just return the first
+ qualified variable without comparing VariableName and VendorGuid.
+
+ @param[in] VariableName Name of the variable to be found.
+ @param[in] VendorGuid Vendor GUID to be found.
+ @param[in] VariableStore Pointer to a VARIABLE_NVM_STORE_HEADER structure which
+ is the variable store to search.
+ @param[in,out] VariableTrack Ptr Pointer to a variable NVM tracking structure which points
+ current pointer to the variable if found.
+
+ @retval EFI_INVALID_PARAMETER If VariableName is not an empty string, while
+ VendorGuid is NULL.
+ @retval EFI_SUCCESS Variable successfully found.
+ @retval EFI_NOT_FOUND Variable not found
+
+**/
+EFI_STATUS
+EFIAPI
+FindDeletedVariable (
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VendorGuid,
+ IN VARIABLE_NVM_STORE_HEADER *VariableStorePtr,
+ IN OUT VARIABLE_NVM_POINTER_TRACK *VariablePtrTrack
+ );
+
+/**
+ Retrieves a variable's value using its name and GUID.
+
+ Read the specified variable from the CSE NVM variable store. If the Data
+ buffer is too small to hold the contents of the variable,
+ the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
+ required buffer size to obtain the data.
+
+ Note: It is the caller's responsibility to extensively validate the input parameters.
+
+ @param[in] CseVariableFileInfo A pointer to an array of structures that contains information the CSE files available.
+ @param[in] VariableName A pointer to a null-terminated string that is the variable's name.
+ @param[in] VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of
+ VariableGuid and VariableName must be unique.
+ @param[out] Attributes If non-NULL, on return, points to the variable's attributes.
+ @param[in, out] DataSize On entry, points to the size in bytes of the Data buffer.
+ On return, points to the size of the data returned in Data.
+ @param[out] Data Points to the buffer which will hold the returned variable value.
+ @param[out] VariableHeader A pointer to the variable header.
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable could not be found.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data.
+ DataSize is updated with the size required for
+ the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+GetCseVariable (
+ IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo,
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VariableGuid,
+ OUT UINT32 *Attributes OPTIONAL,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data,
+ OUT VARIABLE_NVM_HEADER *VariableHeader OPTIONAL
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageSelectorLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageSelectorLib.h new file mode 100644 index 0000000000..f1b5cb2019 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageSelectorLib.h @@ -0,0 +1,105 @@ +/** @file
+ CSE Variable Storage Selector Library.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CSE_VARIABLE_STORAGE_SELECTOR_LIB_H_
+#define _CSE_VARIABLE_STORAGE_SELECTOR_LIB_H_
+
+#include <Uefi.h>
+
+#include <Library/CseVariableStorageLib.h>
+#include <Protocol/Heci.h>
+
+#define CSE_PRIMARY_NVM_FILE_STORE_OFFSET 0
+
+//
+// Variable store options provided by CSE (platform specific)
+//
+typedef enum {
+ VariableStoreTypeHostMemoryBuffer, ///< A variable store that resides in host memory
+ VariableStoreTypeNv, ///< General NVM provided by CSE
+ VariableStoreTypeMax ///< End of CSE variable store types
+} CSE_VARIABLE_STORE_TYPE;
+
+/**
+ Returns the CSE NVM file used for the requested variable.
+
+ @param[in] VariableName Name of the variable.
+ @param[in] VendorGuid Guid of the variable.
+ @param[in] CseVariableFileInfo An array of pointers to CSE
+ variable file information.
+
+ @return The type of CSE NVM file used for this variable.
+
+**/
+CSE_VARIABLE_FILE_TYPE
+EFIAPI
+GetCseVariableStoreFileType (
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VendorGuid,
+ IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo
+ );
+
+/**
+ Returns the base offset for variable services in the CSE NVM file
+ specified for this file type.
+
+ @param[in] CseVariableFileType The type of the CSE NVM file.
+ @param[out] CseFileOffset The offset to base a variable store
+ in the CSE file for this variable.
+
+ @retval EFI_SUCCESS Offset successfully returned for the variable.
+ @retval Others An error occurred.
+
+**/
+EFI_STATUS
+EFIAPI
+GetCseVariableStoreFileOffset (
+ IN CSE_VARIABLE_FILE_TYPE CseVariableFileType,
+ OUT UINT32 *CseFileOffset
+ );
+
+/**
+ Returns the HECI protocol used to access the CSE NVM file based on the current point in the boot.
+
+ @param[out] Heci2Protocol A pointer to the HECI2 protocol if it is active.
+ If HECI1 is active, the value is NULL.
+
+ @return CSE_VARIABLE_HECI_PROTOCOL The HECI protocol to currently use.
+
+**/
+CSE_VARIABLE_HECI_PROTOCOL
+EFIAPI
+GetCseHeciProtocol (
+ OUT EFI_HECI_PROTOCOL **Heci2Protocol
+ );
+
+/**
+ Returns the HECI protocol used to access the CSE NVM file based on a given varaible.
+
+ @param[in] VariableName Name of the variable.
+ @param[in] VendorGuid Guid of the variable.
+
+ @return CSE_VARIABLE_HECI_PROTOCOL The HECI protocol to currently use.
+
+**/
+CSE_VARIABLE_HECI_PROTOCOL
+EFIAPI
+GetCseVariableHeciProtocol (
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VendorGuid
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/MmioDevice.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/MmioDevice.h new file mode 100644 index 0000000000..a54a72fa2e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/MmioDevice.h @@ -0,0 +1,93 @@ +/** @file
+ MMIO device protocol as defined in the UEFI 2.x.x specification.
+
+ The MMIO device protocol defines a memory mapped I/O device
+ for use by the system.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __MMIO_DEVICE_H__
+#define __MMIO_DEVICE_H__
+
+///
+/// Protocol to define for the MMIO device
+//
+typedef struct {
+ ///
+ /// Address of a GUID
+ ///
+ EFI_GUID *Guid;
+
+ ///
+ /// Context for the protocol
+ ///
+ VOID *Context;
+} EFI_MMIO_DEVICE_PROTOCOL_ITEM;
+
+
+typedef struct _EFI_MMIO_DEVICE_PROTOCOL EFI_MMIO_DEVICE_PROTOCOL;
+
+///
+/// The MMIO device protocol defines a memory mapped I/O device
+/// for use by the system.
+///
+struct _EFI_MMIO_DEVICE_PROTOCOL {
+ ///
+ /// Pointer to an ACPI_EXTENDED_HID_DEVICE_PATH structure
+ /// containing HID/HidStr and CID/CidStr values.
+ ///
+ /// See the note below associated with the UnitIdentification
+ /// field.
+ ///
+ ACPI_HID_DEVICE_PATH *AcpiPath;
+
+ ///
+ /// Allow the use of a shared template for the AcpiPath.
+ ///
+ /// If this value is non-zero UID value then the AcpiPath must
+ /// be a template which contains only the HID/HidStr and CID/CidStr
+ /// values. The UID/UidStr values in the AcpiPath must be zero!
+ //
+ /// If this value is zero then the AcpiPath is not shared and
+ /// must contain either a non-zero UID value or a UidStr value.
+ ///
+ UINT32 UnitIdentification;
+
+ ///
+ /// Hardware revision - ACPI _HRV value
+ ///
+ UINT32 HardwareRevision;
+
+ ///
+ /// Pointer to a data structure containing the controller
+ /// resources and configuration. At a minimum this points
+ /// to an EFI_PHYSICAL_ADDRESS for the base address of the
+ /// MMIO device.
+ ///
+ VOID *DriverResources;
+
+ ///
+ /// Number of protocols in the array
+ ///
+ UINTN ProtocolCount;
+
+ ///
+ /// List of protocols to define
+ ///
+ EFI_MMIO_DEVICE_PROTOCOL_ITEM *ProtocolArray;
+};
+
+extern EFI_GUID gEfiMmioDeviceProtocolGuid;
+
+#endif // __MMIO_DEVICE_H__
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/SiPolicyProtocol.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/SiPolicyProtocol.h new file mode 100644 index 0000000000..ad3257aa31 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/SiPolicyProtocol.h @@ -0,0 +1,57 @@ +/** @file
+ Protocol used for specifying platform related Silicon information and policy setting.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_PROTOCOL_H_
+#define _SI_POLICY_PROTOCOL_H_
+
+#include <IndustryStandard/Hsti.h>
+
+//
+// DXE_SI_POLICY_PROTOCOL revisions
+//
+#define DXE_SI_POLICY_PROTOCOL_REVISION_1 1
+
+extern EFI_GUID gDxeSiPolicyProtocolGuid;
+
+
+/**
+ The protocol allows the platform code to publish a set of configuration information that the
+ Silicon drivers will use to configure the processor in the DXE phase.
+ This Policy Protocol needs to be initialized for Silicon configuration.
+ @note The Protocol has to be published before processor DXE drivers are dispatched.
+**/
+typedef struct {
+ /**
+ This member specifies the revision of the Si Policy protocol. This field is used to indicate backward
+ compatible changes to the protocol. Any such changes to this protocol will result in an update in the revision number.
+
+ <b>Revision 1</b>:
+ - Initial version
+ **/
+
+ UINT8 Revision;
+/**
+ This member describes a pointer to Hsti results from previous boot. In order to mitigate the large performance cost
+ of performing all of the platform security tests on each boot, we can save the results across boots and retrieve
+ and point this policy to them prior to the launch of HstiSiliconDxe. Logic should be implemented to not populate this
+ upon major platform changes (i.e changes to setup option or platform hw)to ensure that results accurately reflect the
+ configuration of the platform.
+**/
+ ADAPTER_INFO_PLATFORM_SECURITY *Hsti; ///< This is a pointer to Hsti results from previous boot
+ UINTN HstiSize; ///< Size of results, if setting Hsti policy to point to previous results
+} DXE_SI_POLICY_PROTOCOL;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/VariableStorageProtocol.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/VariableStorageProtocol.h new file mode 100644 index 0000000000..ee5dc3dae3 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Protocol/VariableStorageProtocol.h @@ -0,0 +1,325 @@ +/** @file
+ This file declares the Variable Storage Protocol.
+
+ This protocol abstracts read-only access to the UEFI variable store
+ on a NVM (Non-Volatile Memory) device during the Runtime DXE phase.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VARIABLE_STORAGE_PROTOCOL_H_
+#define _VARIABLE_STORAGE_PROTOCOL_H_
+
+extern EFI_GUID gVariableStorageProtocolGuid;
+
+///
+/// Revision
+///
+#define VARIABLE_STORAGE_PROTOCOL_REVISION 1
+
+typedef struct _VARIABLE_STORAGE_PROTOCOL VARIABLE_STORAGE_PROTOCOL;
+
+/**
+ Retrieves a protocol instance-specific GUID.
+
+ Returns a unique GUID per VARIABLE_STORAGE_PROTOCOL instance.
+
+ @param[out] VariableGuid A pointer to an EFI_GUID that is this protocol instance's GUID.
+
+ @retval EFI_SUCCESS The data was returned successfully.
+ @retval EFI_INVALID_PARAMETER A required parameter is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_GET_ID)(
+ OUT EFI_GUID *InstanceGuid
+ );
+
+/**
+ This service retrieves a variable's value using its name and GUID.
+
+ Read the specified variable from the UEFI variable store. If the Data
+ buffer is too small to hold the contents of the variable,
+ the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
+ required buffer size to obtain the data.
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PROTOCOL.
+ @param[in] VariableName A pointer to a null-terminated string that is the variable's name.
+ @param[in] VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of
+ VariableGuid and VariableName must be unique.
+ @param[out] Attributes If non-NULL, on return, points to the variable's attributes.
+ @param[in, out] DataSize On entry, points to the size in bytes of the Data buffer.
+ On return, points to the size of the data returned in Data.
+ @param[out] Data Points to the buffer which will hold the returned variable value.
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable could not be found.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data.
+ DataSize is updated with the size required for
+ the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_GET_VARIABLE)(
+ IN CONST VARIABLE_STORAGE_PROTOCOL *This,
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VariableGuid,
+ OUT UINT32 *Attributes,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data
+ );
+
+/**
+ This service retrieves an authenticated variable's value using its name and GUID.
+
+ Read the specified authenticated variable from the UEFI variable store. If the Data
+ buffer is too small to hold the contents of the variable,
+ the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
+ required buffer size to obtain the data.
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PROTOCOL.
+ @param[in] VariableName A pointer to a null-terminated string that is the variable's name.
+ @param[in] VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of
+ VariableGuid and VariableName must be unique.
+ @param[out] Attributes If non-NULL, on return, points to the variable's attributes.
+ @param[in, out] DataSize On entry, points to the size in bytes of the Data buffer.
+ On return, points to the size of the data returned in Data.
+ @param[out] Data Points to the buffer which will hold the returned variable value.
+ @param[out] KeyIndex Index of associated public key in database
+ @param[out] MonotonicCount Associated monotonic count value to protect against replay attack
+ @param[out] TimeStamp Associated TimeStamp value to protect against replay attack
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable could not be found.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data.
+ DataSize is updated with the size required for
+ the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_GET_AUTHENTICATED_VARIABLE)(
+ IN CONST VARIABLE_STORAGE_PROTOCOL *This,
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VariableGuid,
+ OUT UINT32 *Attributes,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data,
+ OUT UINT32 *KeyIndex,
+ OUT UINT64 *MonotonicCount,
+ OUT EFI_TIME *TimeStamp
+ );
+
+/**
+ Return the next variable name and GUID.
+
+ This function is called multiple times to retrieve the VariableName
+ and VariableGuid of all variables currently available in the system.
+ On each call, the previous results are passed into the interface,
+ and, on return, the interface returns the data for the next
+ interface. When the entire variable list has been returned,
+ EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PROTOCOL.
+
+ @param[in, out] VariableNameSize On entry, points to the size of the buffer pointed to by
+ VariableName. On return, the size of the variable name buffer.
+ @param[in, out] VariableName On entry, a pointer to a null-terminated string that is the
+ variable's name. On return, points to the next variable's
+ null-terminated name string.
+ @param[in, out] VariableGuid On entry, a pointer to an EFI_GUID that is the variable's GUID.
+ On return, a pointer to the next variable's GUID.
+ @param[out] VariableAttributes A pointer to the variable attributes.
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable could not be found.
+ @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the resulting
+ data. VariableNameSize is updated with the size
+ required for the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid or
+ VariableNameSize is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_GET_NEXT_VARIABLE_NAME)(
+ IN CONST VARIABLE_STORAGE_PROTOCOL *This,
+ IN OUT UINTN *VariableNameSize,
+ IN OUT CHAR16 *VariableName,
+ IN OUT EFI_GUID *VariableGuid,
+ OUT UINT32 *VariableAttributes
+ );
+
+/**
+ Returns information on the amount of space available in the variable store. If the amount of data that can be written
+ depends on if the platform is in Pre-OS stage or OS stage, the AtRuntime parameter should be used to compute usage.
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PROTOCOL.
+ @param[in] AtRuntime TRUE is the platform is in OS Runtime, FALSE if still in Pre-OS stage
+ @param[out] VariableStoreSize The total size of the NV storage. Indicates the maximum amount
+ of data that can be stored in this NV storage area.
+ @param[out] CommonVariablesTotalSize The total combined size of all the common UEFI variables that are
+ stored in this NV storage area. Excludes variables with the
+ EFI_VARIABLE_HARDWARE_ERROR_RECORD attribute set.
+ @param[out] HwErrVariablesTotalSize The total combined size of all the UEFI variables that have the
+ EFI_VARIABLE_HARDWARE_ERROR_RECORD attribute set and which are
+ stored in this NV storage area. Excludes all other variables.
+
+ @retval EFI_INVALID_PARAMETER Any of the given parameters are NULL
+ @retval EFI_SUCCESS Space information returned successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_GET_STORAGE_USAGE)(
+ IN CONST VARIABLE_STORAGE_PROTOCOL *This,
+ IN BOOLEAN AtRuntime,
+ OUT UINT32 *VariableStoreSize,
+ OUT UINT32 *CommonVariablesTotalSize,
+ OUT UINT32 *HwErrVariablesTotalSize
+ );
+
+/**
+ Returns whether this NV storage area supports storing authenticated variables or not
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PROTOCOL.
+ @param[out] AuthSupported TRUE if this NV storage area can store authenticated variables,
+ FALSE otherwise
+
+ @retval EFI_SUCCESS AuthSupported was returned successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_GET_AUTHENTICATED_SUPPORT)(
+ IN CONST VARIABLE_STORAGE_PROTOCOL *This,
+ OUT BOOLEAN *AuthSupported
+ );
+
+/**
+ Returns whether this NV storage area is ready to accept calls to SetVariable() or not
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PROTOCOL.
+
+ @retval TRUE The NV storage area is ready to accept calls to SetVariable()
+ @retval FALSE The NV storage area is not ready to accept calls to SetVariable()
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *VARIABLE_STORAGE_WRITE_SERVICE_IS_READY)(
+ IN CONST VARIABLE_STORAGE_PROTOCOL *This
+ );
+
+/**
+ A callback to be invoked by the VARIABLE_STORAGE_PROTOCOL to indicate to the core variable driver that
+ the WriteServiceIsReady() function is now returning TRUE instead of FALSE.
+
+ The VARIABLE_STORAGE_PROTOCOL is required to call this function as quickly as possible after the core
+ variable driver invokes RegisterWriteServiceReadyCallback() to set the callback.
+
+ @retval EFI_SUCCESS Change to WriteServiceIsReady() status was processed successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_WRITE_SERVICE_READY_CALLBACK)(
+ VOID
+ );
+
+/**
+ Sets the callback to be invoked when the VARIABLE_STORAGE_PROTOCOL is ready to accept calls to SetVariable()
+
+ The VARIABLE_STORAGE_PROTOCOL is required to invoke the callback as quickly as possible after the core
+ variable driver invokes RegisterWriteServiceReadyCallback() to set the callback.
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PROTOCOL.
+ @param[in] CallbackFunction The callback function
+
+ @retval EFI_SUCCESS The callback function was sucessfully registered
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_REGISTER_WRITE_SERVICE_READY_CALLBACK)(
+ IN CONST VARIABLE_STORAGE_PROTOCOL *This,
+ IN VARIABLE_STORAGE_WRITE_SERVICE_READY_CALLBACK CallbackFunction
+ );
+
+/**
+ This code sets a variable's value using its name and GUID.
+
+ Caution: This function may receive untrusted input.
+ This function may be invoked in SMM mode, and datasize and data are external input.
+ This function will do basic validation, before parsing the data.
+ This function will parse the authentication carefully to avoid security issues, like
+ buffer overflow, integer overflow.
+ This function will check attribute carefully to avoid authentication bypass.
+
+ @param[in] This A pointer to this instance of the VARIABLE_STORAGE_PROTOCOL.
+ @param[in] VariableName Name of Variable to be found.
+ @param[in] VendorGuid Variable vendor GUID.
+ @param[in] Attributes Attribute value of the variable found
+ @param[in] DataSize Size of Data found. If size is less than the
+ data, this value contains the required size.
+ @param[in] Data Data pointer.
+ @param[in] AtRuntime TRUE is the platform is in OS Runtime, FALSE if still in Pre-OS stage
+ @param[in] KeyIndex If writing an authenticated variable, the public key index
+ @param[in] MonotonicCount If writing a monotonic counter authenticated variable, the counter value
+ @param[in] TimeStamp If writing a timestamp authenticated variable, the timestamp value
+
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_SUCCESS Set successfully.
+ @retval EFI_OUT_OF_RESOURCES Resource not enough to set variable.
+ @retval EFI_NOT_FOUND Not found.
+ @retval EFI_WRITE_PROTECTED Variable is read-only.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *VARIABLE_STORAGE_SET_VARIABLE)(
+ IN CONST VARIABLE_STORAGE_PROTOCOL *This,
+ IN CHAR16 *VariableName,
+ IN EFI_GUID *VendorGuid,
+ IN UINT32 Attributes,
+ IN UINTN DataSize,
+ IN VOID *Data,
+ IN BOOLEAN AtRuntime,
+ IN UINT32 KeyIndex OPTIONAL,
+ IN UINT64 MonotonicCount OPTIONAL,
+ IN EFI_TIME *TimeStamp OPTIONAL
+ );
+
+///
+/// Variable Storage Protocol
+/// Interface functions for variable NVM storage access in DXE phase.
+///
+struct _VARIABLE_STORAGE_PROTOCOL {
+ VARIABLE_STORAGE_GET_ID GetId; ///< Retrieves a protocol instance-specific GUID
+ VARIABLE_STORAGE_GET_VARIABLE GetVariable; ///< Retrieves a variable's value given its name and GUID
+ VARIABLE_STORAGE_GET_AUTHENTICATED_VARIABLE GetAuthenticatedVariable; ///< Retrieves an authenticated variable's value given its name and GUID
+ VARIABLE_STORAGE_GET_NEXT_VARIABLE_NAME GetNextVariableName; ///< Return the next variable name and GUID
+ VARIABLE_STORAGE_GET_STORAGE_USAGE GetStorageUsage; ///< Returns information on storage usage in the variable store
+ VARIABLE_STORAGE_GET_AUTHENTICATED_SUPPORT GetAuthenticatedSupport; ///< Returns whether this NV storage area supports authenticated variables
+ VARIABLE_STORAGE_SET_VARIABLE SetVariable; ///< Sets a variable's value using its name and GUID.
+ VARIABLE_STORAGE_WRITE_SERVICE_IS_READY WriteServiceIsReady; ///< Indicates if SetVariable() is ready or not
+ VARIABLE_STORAGE_REGISTER_WRITE_SERVICE_READY_CALLBACK RegisterWriteServiceReadyCallback; ///< Sets the callback to notify that SetVariable() is ready
+};
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/SiPolicy.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/SiPolicy.h new file mode 100644 index 0000000000..49c8597754 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/SiPolicy.h @@ -0,0 +1,92 @@ +/** @file
+ Intel reference code configuration policies.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_H_
+#define _SI_POLICY_H_
+
+/**
+ Silicon Policy revision number
+ Any backwards compatible changes to this structure will result in an update in the revision number
+
+ Revision 1: Initial version
+ Revision 2: Updated version
+ Add OsSelection
+**/
+#define SI_POLICY_REVISION 2
+
+///
+/// OS Selection
+///
+typedef enum {
+ SiWindows = 0,
+ SiAndroid = 1,
+ SiWin7 = 2,
+ SiLinux = 3
+} SI_OS_SELECTION;
+
+/**
+ The Silicon Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+**/
+struct _SI_POLICY {
+ /**
+ This member specifies the revision of the Silicon Policy. This field is used to indicate backward
+ compatible changes to the policy structure. Any such changes to this policy structure will result in an update
+ in the revision number.
+ **/
+ UINT8 Revision;
+ ///
+ /// Platform specific common policies that used by several silicon components.
+ ///
+ ///
+ /// This member determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS
+ /// Type 14 - Group Associations structure - item type.
+ /// FVI structure uses it as SMBIOS OEM type to provide version information.
+ ///
+ UINT8 FviSmbiosType;
+ ///
+ /// Reports if EC is present or not.
+ ///
+ BOOLEAN EcPresent;
+ ///
+ /// Temp Bus Number range available to be assigned to each root port and its downstream
+ /// devices for initialization of these devices before PCI Bus enumeration.
+ ///
+ UINT8 TempPciBusMin;
+ UINT8 TempPciBusMax;
+ ///
+ /// Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers.
+ /// Minimum size is 2MB bytes
+ ///
+ UINT32 TempMemBaseAddr;
+ ///
+ /// Size of allocated temp MMIO space
+ ///
+ UINT32 TempMemSize;
+ ///
+ /// Temporary IO Base Address for PCI devices to be used to initialize IO registers.
+ ///
+ UINT16 TempIoBaseAddr;
+ ///
+ /// Size of temporary IO space
+ ///
+ UINT16 TempIoSize;
+ UINT32 OsSelection : 2;
+ UINT32 RsvdBits :30; ///< Reserved bits
+ UINT32 Reserved[7];
+};
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/SiPolicyHob.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/SiPolicyHob.h new file mode 100644 index 0000000000..8e1b0b20db --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/SiPolicyHob.h @@ -0,0 +1,27 @@ +/** @file
+ Silicon Policy HOB is used for gathering platform
+ related Intel silicon information and policy setting.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_HOB_H_
+#define _SI_POLICY_HOB_H_
+
+#include "SiPolicy.h"
+
+extern EFI_GUID gSiPolicyHobGuid;
+
+typedef CONST struct _SI_POLICY SI_POLICY_HOB;
+
+#endif // _SI_POLICY_HOB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/VariableNvmStorageFormat.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/VariableNvmStorageFormat.h new file mode 100644 index 0000000000..4e37242857 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/VariableNvmStorageFormat.h @@ -0,0 +1,130 @@ +/** @file
+ This file contains common declarations for Variable Storage data structures.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VARIABLE_STORAGE_FORMAT_H_
+#define _VARIABLE_STORAGE_FORMAT_H_
+
+#define VARIABLE_NVM_STORE_REVISION_1_0 0x1
+
+#define NVM_HEADER_ALIGNMENT 4
+#define NVM_HEADER_ALIGN(a) (((UINTN) (a) + NVM_HEADER_ALIGNMENT - 1) & (~(UINTN)(NVM_HEADER_ALIGNMENT - 1)))
+
+//
+// Calculates the minimal pad bytes needed to make the current pad size satisfy the alignment requirement.
+//
+#define NVM_GET_PAD_SIZE(a) (((~a) + 1) & (NVM_HEADER_ALIGNMENT - 1)) ///< Bytes for alignment padding higher in memory
+#define NVM_GET_PAD_SIZE_N(a) (((~a) - 1) & (NVM_HEADER_ALIGNMENT - 1)) ///< Bytes for alignment padding lower in memory
+
+#pragma pack (push, 1)
+
+//
+// Variable Store Header
+//
+// This table is at the beginning of every variable store.
+//
+typedef struct {
+ EFI_GUID Signature; ///< Signature to identify this table
+ UINT32 Size; ///< Length in bytes of this entire header
+ UINT8 Revision; ///< Revision of this header
+ UINT8 Checksum; ///< Checksum of this header
+ UINT8 Format; ///< Format of the variable store
+ UINT8 State; ///< Indicates the current state of the variable store
+ UINT32 VariableDataTotalLength; ///< Length in bytes of all variable data in this store
+ UINT32 VariableHeaderTotalEntries; ///< Total number of variable headers in this store
+ UINT32 VariableHeaderTotalLength; ///< Length in bytes of all variable headers in this store
+ UINT32 VariableHeaderOffset; ///< Offset, in bytes, from the beginning of this header
+ ///< to the first variable header
+} VARIABLE_NVM_STORE_HEADER;
+
+//
+// Variable Header
+//
+// This header maintains all meta data associated with a variable.
+//
+typedef struct {
+ UINT16 StartId; ///< Variable data section start identifier
+ UINT8 Reserved; ///< Reserved field
+ UINT8 State; ///< State of the variable
+ UINT32 Attributes; ///< Variable attributes
+ UINT32 NameSize; ///< Length in bytes of the variable name string
+ UINT32 DataSize; ///< Length in bytes of the variable data region
+ UINT32 DataOffset; ///< Offset in bytes from the beginning of this
+ ///< structure to the corresponding data section
+ EFI_GUID VendorGuid; ///< Unique identifier for the variable vendor
+} VARIABLE_NVM_HEADER;
+
+//
+// Authenticated Variable Header
+//
+typedef struct {
+ UINT16 StartId; ///< Variable data section start identifier
+ UINT8 Reserved; ///< Reserved field
+ UINT8 State; ///< State of the variable
+ UINT32 Attributes; ///< Variable attributes
+ UINT32 NameSize; ///< Length in bytes of the variable name string
+ UINT32 DataSize; ///< Length in bytes of the variable data region
+ UINT32 DataOffset; ///< Offset in bytes from the beginning of this
+ ///< structure to the corresponding data section
+ EFI_GUID VendorGuid; ///< Unique identifier for the variable vendor
+ UINT64 MonotonicCount; ///< Associated monotonic count value to protect against replay attack
+ EFI_TIME TimeStamp; ///< Associated TimeStamp value to protect against replay attack
+ UINT32 PubKeyIndex; ///< Index of associated public key in database
+} AUTHENTICATED_VARIABLE_NVM_HEADER;
+
+//
+// Variable Index Table
+//
+// This table tracks distance between variable headers.
+//
+typedef struct {
+ UINT16 Length; ///< Length of the index table
+ UINT16 GoneThrough; ///< Entries gone through when searching
+ VARIABLE_NVM_HEADER *EndPtr; ///< Last variable in the variable header region
+ VARIABLE_NVM_HEADER *StartPtr; ///< First variable in the variable header region
+ //
+ // This field is used to store the distance
+ // of two neighboring VAR_ADDED type variables.
+ // The meaning of this field is implementation-
+ // dependent.
+ //
+} VARIABLE_NVM_INDEX_TABLE;
+
+//
+// Variable Store Info
+//
+// Associates an index table with a corresponding variable store.
+//
+typedef struct {
+ VARIABLE_NVM_STORE_HEADER *VariableStoreHeader; ///< Header for the NVM variable store
+ VARIABLE_NVM_INDEX_TABLE *IndexTable; ///< Pointer to the variable header region index table
+ BOOLEAN AuthFlag; ///< Indicates if the store contains authenticated variables
+} VARIABLE_NVM_STORE_INFO;
+
+//
+// Variable Pointer Tracking Structure
+//
+// This structure is used to track variable header pointers and information.
+//
+typedef struct {
+ VARIABLE_NVM_HEADER *CurrPtr;
+ VARIABLE_NVM_HEADER *StartPtr;
+ VARIABLE_NVM_HEADER *EndPtr;
+ VARIABLE_NVM_HEADER *InDeletedTransitionPtr;
+} VARIABLE_NVM_POINTER_TRACK;
+
+#pragma pack (pop)
+
+#endif
+
|