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authorzwei4 <david.wei@intel.com>2018-02-14 10:44:03 +0800
committerzwei4 <david.wei@intel.com>2018-02-14 10:44:03 +0800
commita123644d1b1eb4068bc8bb41360ab04515e8a760 (patch)
tree2e31ef126fe42273f2113297d773fbe64b56e9dc /Silicon
parentd0adfa023b9d9d2e2b0c4c1e4e60e620bb1d227d (diff)
downloadedk2-platforms-a123644d1b1eb4068bc8bb41360ab04515e8a760.tar.xz
IDTP9180 PMIC Power Sequence Configuration.
Change Bit 2 (SUSPWRDNACKCFG) of Power Sequence Configuration register (offset 0x2A) to 1. If SUSPWRDNACKCFG is 0, SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSPWRDNACK goes high in S4 state. If SUSPWRDNACKCFG is 1, PMIC responses to SUSPWRDNACK signal. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Silicon')
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc15
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc6
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h2
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c2
4 files changed, 22 insertions, 3 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc
index 4ae0803022..1a9da7729e 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc
@@ -1,7 +1,7 @@
## @file
# Component description file for the Broxton RC DXE drivers.
#
-# Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -41,3 +41,16 @@ $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf {
}
!endif
+$(PLATFORM_SI_PACKAGE)/SouthCluster/Smbus/Dxe/PchSmbusDxe.inf {
+ <PcdsPatchableInModule>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xFFFFFFFF
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+ <LibraryClasses>
+!if $(TARGET) != RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+ <BuildOptions>
+ ICC:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+ GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
+ }
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc
index ff36dccd49..935691a295 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc
@@ -1,7 +1,7 @@
## @file
# Component description file for the Broxton RC DXE libraries.
#
-# Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -33,3 +33,7 @@
HeciMsgLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.inf
SeCLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/SeCLib/SeCLib.inf
+#
+# SMBus
+#
+ ScSmbusCommonLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/PeiDxeSmmScSmbusCommonLib.inf
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
index 5e226a80d4..6218de8ddf 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
@@ -92,7 +92,7 @@ typedef struct _SMBUS_INSTANCE {
//
// Driver global data
//
-SMBUS_INSTANCE *mSmbusContext;
+extern SMBUS_INSTANCE *mSmbusContext;
//
// Prototypes
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c
index 6ae16f3439..021cf26c93 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c
@@ -17,6 +17,8 @@
extern EFI_GUID gEfiSmbusArpMapGuid;
+SMBUS_INSTANCE *mSmbusContext;
+
/**
Execute an SMBus operation