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authorAlan Ott <alan@softiron.com>2017-08-20 15:33:34 -0400
committerLeif Lindholm <leif.lindholm@linaro.org>2017-08-21 18:00:20 +0100
commit03159ba83bd6b01843bd42ffec0e3c3e6fb12429 (patch)
tree4548eb87d45cf39ffcb8ad93f6eb8c2e3d126f7b /Silicon
parent4b89d86fee1e9929c306cbb5f57db39353e52191 (diff)
downloadedk2-platforms-03159ba83bd6b01843bd42ffec0e3c3e6fb12429.tar.xz
Silicon/AMD/Styx: Use PcdSataPortMode properly for two controllers
The previous implementation used only the lower bits for both the first and second SATA controller, when the upper bits should have been used for the second SATA controller. Also ASSERT that SataChPerSerdes is 2, because the even/odd logic doesn't work if it's not. Signed-off-by: Alan Ott <alan@softiron.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon')
-rw-r--r--Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c
index 78c6819138..ea49cae989 100644
--- a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c
+++ b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c
@@ -109,10 +109,15 @@ InitializeSataController (
SataChPerSerdes = FixedPcdGet8 (PcdSataNumChPerSerdes);
- for (PortNum = 0; PortNum < SataPortCount; PortNum += SataChPerSerdes) {
+ //
+ // SataChPerSerdes must be 2 for the Even/Odd logic in the loop below
+ //
+ ASSERT(SataChPerSerdes == 2);
+
+ for (PortNum = StartPort; PortNum < SataPortCount + StartPort; PortNum += SataChPerSerdes) {
EvenPort = (UINT32)(FixedPcdGet32 (PcdSataPortMode) >> (PortNum * 2)) & 3;
OddPort = (UINT32)(FixedPcdGet32 (PcdSataPortMode) >> ((PortNum+1) * 2)) & 3;
- SataPhyInit ((StartPort + PortNum) / SataChPerSerdes, EvenPort, OddPort);
+ SataPhyInit (PortNum / SataChPerSerdes, EvenPort, OddPort);
}
//