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| author | Hao Wu <hao.a.wu@intel.com> | 2016-10-25 13:35:54 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-12-16 11:48:08 +0800 |
| commit | 0f16be6d9eef371d6ed1e45422748ae0fb49652f (patch) | |
| tree | e2048fc100110487b8a9f901720111f370404b7e /UefiCpuPkg/Include/Register/Msr/P6Msr.h | |
| parent | 7dede0a219859dccf21b622d205a9b8801e4a078 (diff) | |
| download | edk2-platforms-0f16be6d9eef371d6ed1e45422748ae0fb49652f.tar.xz | |
UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update MSR header files of processors (excluding Goldmont and Skylake
processors) according to Intel(R) 64 and IA-32 Architectures Software
Developer's Manual, Volume 3, September 2016, Chapter 35
Model-Specific-Registers (MSR).
Summary of incompatible changes:
General:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header
files has been removed or renamed to IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS)
in processor-specific header files have been removed or renamed to
IA32_MC{X}_{XXX} (like IA32_MC4_STATUS)
Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in
SDM are still kept in processor-specific header files.
HaswellMsr.h:
1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed
Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE'
in SDM.
Since the MSR definition is the same with architectural MSR, we remove it.
SandyBridgeMsr.h:
1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields
0:3
Bit description change from 'Core {X} select' to 'Slice {X} select' for
bit 0:3 in SDM.
SilvermontMsr.h:
1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed
Bit description for this MSR is totally changed in SDM, we modify the
structure definition to align with it.
XeonDMsr.h:
1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY
and MSR_PKG_C10_RESIDENCY have been removed
Those 3 MSRs are not defined for this processor in SDM, we remove them.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Diffstat (limited to 'UefiCpuPkg/Include/Register/Msr/P6Msr.h')
| -rw-r--r-- | UefiCpuPkg/Include/Register/Msr/P6Msr.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/Register/Msr/P6Msr.h index a196330dd7..ef908001c1 100644 --- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h @@ -17,7 +17,7 @@ @par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.21.
**/
@@ -27,7 +27,7 @@ #include <Register/ArchitecturalMsr.h>
/**
- See Section 35.20, "MSRs in Pentium Processors.".
+ See Section 35.22, "MSRs in Pentium Processors.".
@param ECX MSR_P6_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -46,7 +46,7 @@ /**
- See Section 35.20, "MSRs in Pentium Processors.".
+ See Section 35.22, "MSRs in Pentium Processors.".
@param ECX MSR_P6_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
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