Add Local APIC Library class defining APIs for common Local APIC operations. Add two Local APIC library instances, one is for xAPIC mode only, the other is for x2APIC capable processors which have xAPIC and x2APIC modes.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10814 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 437 insertions, 0 deletions

diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
new file mode 100644
index 0000000000..58e3474e88
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -0,0 +1,270 @@
+/** @file

+  Public include file for Local APIC library.

+

+  Local APIC library assumes local APIC is enabled. It does not

+  handles cases where local APIC is disabled.

+

+  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef __LOCAL_APIC_LIB_H__

+#define __LOCAL_APIC_LIB_H__

+

+#define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.

+#define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.

+

+/**

+  Get the current local APIC mode.

+

+  If local APIC is disabled, then ASSERT.

+

+  @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.

+  @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.

+**/

+UINTN

+EFIAPI

+GetApicMode (

+  VOID

+  );

+

+/**

+  Set the current local APIC mode.

+

+  If the specified local APIC mode is not valid, then ASSERT.

+  If the specified local APIC mode can't be set as current, then ASSERT.

+

+  @param ApicMode APIC mode to be set.

+**/

+VOID

+EFIAPI

+SetApicMode (

+  IN UINTN  ApicMode

+  );

+

+/**

+  Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.

+

+  In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.

+  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, 

+  the 32-bit local APIC ID is returned as initial APIC ID.

+

+  @return  32-bit initial local APIC ID of the executing processor.

+**/

+UINT32

+EFIAPI

+GetInitialApicId (

+  VOID

+  );

+

+/**

+  Get the local APIC ID of the executing processor.

+

+  @return  32-bit local APIC ID of the executing processor.

+**/

+UINT32

+EFIAPI

+GetApicId (

+  VOID

+  );

+

+/**

+  Send a SMI IPI to a specified target processor.

+

+  This function returns after the IPI has been accepted by the target processor. 

+

+  @param  ApicId   Specify the local APIC ID of the target processor.

+**/

+VOID

+EFIAPI

+SendSmiIpi (

+  IN UINT32          ApicId

+  );

+

+/**

+  Send a SMI IPI to all processors excluding self.

+

+  This function returns after the IPI has been accepted by the target processors. 

+**/

+VOID

+EFIAPI

+SendSmiIpiAllExcludingSelf (

+  VOID

+  );

+

+/**

+  Send an INIT IPI to a specified target processor.

+

+  This function returns after the IPI has been accepted by the target processor. 

+

+  @param  ApicId   Specify the local APIC ID of the target processor.

+**/

+VOID

+EFIAPI

+SendInitIpi (

+  IN UINT32          ApicId

+  );

+

+/**

+  Send an INIT IPI to all processors excluding self.

+

+  This function returns after the IPI has been accepted by the target processors. 

+**/

+VOID

+EFIAPI

+SendInitIpiAllExcludingSelf (

+  VOID

+  );

+

+/**

+  Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.

+

+  This function returns after the IPI has been accepted by the target processor. 

+

+  if StartupRoutine >= 1M, then ASSERT.

+  if StartupRoutine is not multiple of 4K, then ASSERT.

+

+  @param  ApicId          Specify the local APIC ID of the target processor.

+  @param  StartupRoutine  Points to a start-up routine which is below 1M physical

+                          address and 4K aligned.

+**/

+VOID

+EFIAPI

+SendInitSipiSipi (

+  IN UINT32          ApicId,

+  IN UINT32          StartupRoutine

+  );

+

+/**

+  Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.

+

+  This function returns after the IPI has been accepted by the target processors. 

+

+  if StartupRoutine >= 1M, then ASSERT.

+  if StartupRoutine is not multiple of 4K, then ASSERT.

+

+  @param  StartupRoutine    Points to a start-up routine which is below 1M physical

+                            address and 4K aligned.

+**/

+VOID

+EFIAPI

+SendInitSipiSipiAllExcludingSelf (

+  IN UINT32          StartupRoutine

+  );

+

+/**

+  Programming Virtual Wire Mode.

+

+  This function programs the local APIC for virtual wire mode following

+  the example described in chapter A.3 of the MP 1.4 spec.

+

+  IOxAPIC is not involved in this type of virtual wire mode.

+**/

+VOID

+EFIAPI

+ProgramVirtualWireMode (

+  VOID

+  );

+

+/**

+  Get the divide value from the DCR (Divide Configuration Register) by which

+  the processor's bus clock is divided to form the time base for the APIC timer.

+

+  @return The divide value is one of 1,2,4,8,16,32,64,128.

+**/

+UINTN

+EFIAPI

+GetApicTimerDivisor (

+  VOID

+  );

+

+/**

+  Read the initial count value from the init-count register.

+

+  @return The initial count value read from the init-count register.

+**/

+UINT32

+EFIAPI

+GetApicTimerInitCount (

+  VOID

+  );

+

+/**

+  Read the current count value from the current-count register.

+

+  @return The current count value read from the current-count register.

+**/

+UINT32

+EFIAPI

+GetApicTimerCurrentCount (

+  VOID

+  );

+

+/**

+  Initialize the local APIC timer.

+

+  The local APIC timer is initialized and enabled.

+

+  @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.

+                       If it is 0, then use the current divide value in the DCR.

+  @param InitCount     The initial count value.

+  @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.

+  @param Vector        The timer interrupt vector number.

+**/

+VOID

+EFIAPI

+InitializeApicTimer (

+  IN UINTN   DivideValue,

+  IN UINT32  InitCount,

+  IN BOOLEAN PeriodicMode,

+  IN UINT8   Vector

+  );

+

+/**

+  Enable the local APIC timer interrupt.

+**/

+VOID

+EFIAPI

+EnableApicTimerInterrupt (

+  VOID

+  );

+

+/**

+  Disable the local APIC timer interrupt.

+**/

+VOID

+EFIAPI

+DisableApicTimerInterrupt (

+  VOID

+  );

+

+/**

+  Get the local APIC timer interrupt state.

+

+  @retval TRUE  The local APIC timer interrupt is enabled.

+  @retval FALSE The local APIC timer interrupt is disabled.

+**/

+BOOLEAN

+EFIAPI

+GetApicTimerInterruptState (

+  VOID

+  );

+

+/**

+  Send EOI to the local APIC.

+**/

+VOID

+EFIAPI

+SendApicEoi (

+  VOID

+  );

+

+#endif

+

diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
new file mode 100644
index 0000000000..7535ef50e9
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -0,0 +1,167 @@
+/** @file

+  IA32 Local APIC Definitions.

+

+  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef __LOCAL_APIC_H__

+#define __LOCAL_APIC_H__

+

+//

+// Definitions for IA32 architectural MSRs

+//

+#define MSR_IA32_APIC_BASE_ADDRESS              0x1B

+

+//

+// Definitions for CPUID instruction

+//

+#define CPUID_VERSION_INFO                      0x1

+#define CPUID_EXTENDED_FUNCTION                 0x80000000

+#define CPUID_VIR_PHY_ADDRESS_SIZE              0x80000008

+

+//

+// Definition for Local APIC registers and related values

+//

+#define XAPIC_ID_OFFSET                         0x0

+#define XAPIC_EOI_OFFSET                        0x0b0

+#define XAPIC_ICR_DFR_OFFSET                    0x0e0

+#define XAPIC_SPURIOUS_VECTOR_OFFSET            0x0f0

+#define XAPIC_ICR_LOW_OFFSET                    0x300

+#define XAPIC_ICR_HIGH_OFFSET                   0x310

+#define XAPIC_LVT_TIMER_OFFSET                  0x320

+#define XAPIC_LINT0_VECTOR_OFFSET               0x350

+#define XAPIC_LINT1_VECTOR_OFFSET               0x360

+#define XAPIC_TIMER_INIT_COUNT_OFFSET           0x380

+#define XAPIC_TIMER_CURRENT_COUNT_OFFSET        0x390

+#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0

+

+#define X2APIC_MSR_BASE_ADDRESS                 0x800

+#define X2APIC_MSR_ICR_ADDRESS                  0x830

+

+#define LOCAL_APIC_DELIVERY_MODE_FIXED           0

+#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1

+#define LOCAL_APIC_DELIVERY_MODE_SMI             2

+#define LOCAL_APIC_DELIVERY_MODE_NMI             4

+#define LOCAL_APIC_DELIVERY_MODE_INIT            5

+#define LOCAL_APIC_DELIVERY_MODE_STARTUP         6

+#define LOCAL_APIC_DELIVERY_MODE_EXTINT          7

+

+#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND       0

+#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF               1

+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2

+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3

+

+typedef union {

+  struct {

+    UINT64  Reserved0:8;   ///< Reserved.

+    UINT64  Bsp:1;         ///< Processor is BSP.

+    UINT64  Reserved1:1;   ///< Reserved.

+    UINT64  Extd:1;        ///< Enable x2APIC mode.

+    UINT64  En:1;          ///< xAPIC global enable/disable.

+    UINT64  ApicBase:52;   ///< APIC Base physical address. The actual field width depends on physical address width.

+  } Bits;

+  UINT64    Uint64;

+} MSR_IA32_APIC_BASE;

+

+//

+// Low half of Interrupt Command Register (ICR).

+//

+typedef union {

+  struct {

+    UINT32  Vector:8;                ///< The vector number of the interrupt being sent.

+    UINT32  DeliveryMode:3;          ///< Specifies the type of IPI to be sent.

+    UINT32  DestinationMode:1;       ///< 0: physical destination mode, 1: logical destination mode.

+    UINT32  DeliveryStatus:1;        ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.

+    UINT32  Reserved0:1;             ///< Reserved.

+    UINT32  Level:1;                 ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.

+    UINT32  TriggerMode:1;           ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.

+    UINT32  Reserved1:2;             ///< Reserved.

+    UINT32  DestinationShorthand:2;  ///< A shorthand notation to specify the destination of the interrupt.

+    UINT32  Reserved2:12;            ///< Reserved.

+  } Bits;

+  UINT32    Uint32;

+} LOCAL_APIC_ICR_LOW;

+

+//

+// High half of Interrupt Command Register (ICR)

+//

+typedef union {

+  struct {

+    UINT32  Reserved0:24;   ///< Reserved.

+    UINT32  Destination:8;  ///< Specifies the target processor or processors in xAPIC mode.

+  } Bits;

+  UINT32    Uint32;         ///< Destination field expanded to 32-bit in x2APIC mode.

+} LOCAL_APIC_ICR_HIGH;

+

+//

+// Spurious-Interrupt Vector Register (SVR)

+//

+typedef union {

+  struct {

+    UINT32  SpuriousVector:8;           ///< Spurious Vector.

+    UINT32  SoftwareEnable:1;           ///< APIC Software Enable/Disable.

+    UINT32  FocusProcessorChecking:1;   ///< Focus Processor Checking.

+    UINT32  Reserved0:2;                ///< Reserved.

+    UINT32  EoiBroadcastSuppression:1;  ///< EOI-Broadcast Suppression.

+    UINT32  Reserved1:19;               ///< Reserved.

+  } Bits;

+  UINT32    Uint32;

+} LOCAL_APIC_SVR;

+

+//

+// Divide Configuration Register (DCR)

+//

+typedef union {

+  struct {

+    UINT32  DivideValue1:2;  ///< Low 2 bits of the divide value.

+    UINT32  Reserved0:1;     ///< Always 0.

+    UINT32  DivideValue2:1;  ///< Highest 1 bit of the divide value.

+    UINT32  Reserved1:28;    ///< Reserved.

+  } Bits;

+  UINT32    Uint32;

+} LOCAL_APIC_DCR;

+

+//

+// LVT Timer Register

+//

+typedef union {

+  struct {

+    UINT32  Vector:8;          ///< The vector number of the interrupt being sent.

+    UINT32  Reserved0:4;       ///< Reserved.

+    UINT32  DeliveryStatus:1;  ///< 0: Idle, 1: send pending.

+    UINT32  Reserved1:3;       ///< Reserved.

+    UINT32  Mask:1;            ///< 0: Not masked, 1: Masked.

+    UINT32  TimerMode:1;       ///< 0: One-shot, 1: Periodic.

+    UINT32  Reserved2:14;      ///< Reserved.

+  } Bits;

+  UINT32    Uint32;

+} LOCAL_APIC_LVT_TIMER;

+

+//

+// LVT LINT0/LINT1 Register

+//

+typedef union {

+  struct {

+    UINT32  Vector:8;            ///< The vector number of the interrupt being sent.

+    UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.

+    UINT32  Reserved0:1;         ///< Reserved.

+    UINT32  DeliveryStatus:1;    ///< 0: Idle, 1: send pending.

+    UINT32  InputPinPolarity:1;  ///< Interrupt Input Pin Polarity.

+    UINT32  RemoteIrr:1;         ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.

+    UINT32  TriggerMode:1;       ///< 0:edge, 1:level.

+    UINT32  Mask:1;              ///< 0: Not masked, 1: Masked.

+    UINT32  Reserved1:15;        ///< Reserved.

+  } Bits;

+  UINT32    Uint32;

+} LOCAL_APIC_LVT_LINT;

+

+#endif

+