diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-22 17:11:19 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:14:50 +0800 |
| commit | 2cc68ed95f4e6a5b6256a6cc1e9f6a585a7d2ba7 (patch) | |
| tree | e6f0cc497ee0f06782388ab114fd2f3d37bddcc5 /UefiCpuPkg/Include | |
| parent | a6747ab91782ba4309b5f12301c8b43b1b4702dd (diff) | |
| download | edk2-platforms-2cc68ed95f4e6a5b6256a6cc1e9f6a585a7d2ba7.tar.xz | |
UefiCpuPkg: Move to new location
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'UefiCpuPkg/Include')
33 files changed, 0 insertions, 49004 deletions
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h deleted file mode 100644 index 12e9692c5c..0000000000 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ /dev/null @@ -1,160 +0,0 @@ -/** @file
-Definitions for CPU S3 data.
-
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _ACPI_CPU_DATA_H_
-#define _ACPI_CPU_DATA_H_
-
-//
-// Register types in register table
-//
-typedef enum {
- Msr,
- ControlRegister,
- MemoryMapped,
- CacheControl
-} REGISTER_TYPE;
-
-//
-// Element of register table entry
-//
-typedef struct {
- REGISTER_TYPE RegisterType;
- UINT32 Index;
- UINT8 ValidBitStart;
- UINT8 ValidBitLength;
- UINT64 Value;
-} CPU_REGISTER_TABLE_ENTRY;
-
-//
-// Register table definition, including current table length,
-// allocated size of this table, and pointer to the list of table entries.
-//
-typedef struct {
- //
- // The number of valid entries in the RegisterTableEntry buffer
- //
- UINT32 TableLength;
- UINT32 NumberBeforeReset;
- //
- // The size, in bytes, of the RegisterTableEntry buffer
- //
- UINT32 AllocatedSize;
- //
- // The initial APIC ID of the CPU this register table applies to
- //
- UINT32 InitialApicId;
- //
- // Buffer of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be
- // allocated below 4GB from memory of type EfiACPIMemoryNVS.
- //
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
-} CPU_REGISTER_TABLE;
-
-//
-// Data structure that is required for ACPI S3 resume. This structure must be
-// allocated below 4GB from memory of type EfiACPIMemoryNVS. The PCD
-// PcdCpuS3DataAddress must be set to the physical address where this structure
-// is allocated
-//
-typedef struct {
- //
- // Physical address of 4KB buffer allocated below 1MB from memory of type
- // EfiReservedMemoryType. The buffer is not required to be initialized, but
- // it is recommended that the buffer be zero-filled. This buffer is used to
- // wake APs during an ACPI S3 resume.
- //
- EFI_PHYSICAL_ADDRESS StartupVector;
- //
- // Physical address of structure of type IA32_DESCRIPTOR. This structure must
- // be allocated below 4GB from memory of type EfiACPIMemoryNVS. The
- // IA32_DESCRIPTOR structure provides the base address and length of a GDT
- // The buffer for GDT must also be allocated below 4GB from memory of type
- // EfiACPIMemoryNVS. The GDT must be filled in with the GDT contents that are
- // used during an ACPI S3 resume. This is typically the contents of the GDT
- // used by the boot processor when the platform is booted.
- //
- EFI_PHYSICAL_ADDRESS GdtrProfile;
- //
- // Physical address of structure of type IA32_DESCRIPTOR. This structure must
- // be allocated below 4GB from memory of type EfiACPIMemoryNVS. The
- // IA32_DESCRIPTOR structure provides the base address and length of an IDT.
- // The buffer for IDT must also be allocated below 4GB from memory of type
- // EfiACPIMemoryNVS. The IDT must be filled in with the IDT contents that are
- // used during an ACPI S3 resume. This is typically the contents of the IDT
- // used by the boot processor when the platform is booted.
- //
- EFI_PHYSICAL_ADDRESS IdtrProfile;
- //
- // Physical address of a buffer that is used as stacks during ACPI S3 resume.
- // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This
- // structure must be allocated below 4GB from memory of type EfiACPIMemoryNVS.
- //
- EFI_PHYSICAL_ADDRESS StackAddress;
- //
- // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume.
- //
- UINT32 StackSize;
- //
- // The number of CPUs. If a platform does not support hot plug CPUs, then
- // this is the number of CPUs detected when the platform is booted, regardless
- // of being enabled or disabled. If a platform does support hot plug CPUs,
- // then this is the maximum number of CPUs that the platform supports.
- //
- UINT32 NumberOfCpus;
- //
- // Physical address of structure of type MTRR_SETTINGS that contains a copy
- // of the MTRR settings that are compatible with the MTRR settings used by
- // the boot processor when the platform was booted. These MTRR settings are
- // used during an ACPI S3 resume. This structure must be allocated below 4GB
- // from memory of type EfiACPIMemoryNVS.
- //
- EFI_PHYSICAL_ADDRESS MtrrTable;
- //
- // Physical address of an array of CPU_REGISTER_TABLE structures, with
- // NumberOfCpus entries. This array must be allocated below 4GB from memory
- // of type EfiACPIMemoryNVS. If a register table is not required, then the
- // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.
- // If TableLength is > 0, then elements of RegisterTableEntry are used to
- // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,
- // before SMBASE relocation is performed.
- //
- EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;
- //
- // Physical address of an array of CPU_REGISTER_TABLE structures, with
- // NumberOfCpus entries. This array must be allocated below 4GB from memory
- // of type EfiACPIMemoryNVS. If a register table is not required, then the
- // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.
- // If TableLength is > 0, then elements of RegisterTableEntry are used to
- // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,
- // after SMBASE relocation is performed.
- //
- EFI_PHYSICAL_ADDRESS RegisterTable;
- //
- // Physical address of a buffer that contains the machine check handler that
- // is used during an ACPI S3 Resume. This buffer must be allocated below 4GB
- // from memory of type EfiACPIMemoryNVS. In order for this machine check
- // handler to be active on an AP during an ACPI S3 resume, the machine check
- // vector in the IDT provided by IdtrProfile must be initialized to transfer
- // control to this physical address.
- //
- EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase;
- //
- // The size, in bytes, of the machine check handler that is used during an
- // ACPI S3 Resume. If this field is 0, then a machine check handler is not
- // provided.
- //
- UINT32 ApMachineCheckHandlerSize;
-} ACPI_CPU_DATA;
-
-#endif
diff --git a/UefiCpuPkg/Include/CpuHotPlugData.h b/UefiCpuPkg/Include/CpuHotPlugData.h deleted file mode 100644 index 2a0d9fabd5..0000000000 --- a/UefiCpuPkg/Include/CpuHotPlugData.h +++ /dev/null @@ -1,33 +0,0 @@ -/** @file
-Definition for a structure sharing information for CPU hot plug.
-
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _CPU_HOT_PLUG_DATA_H_
-#define _CPU_HOT_PLUG_DATA_H_
-
-#define CPU_HOT_PLUG_DATA_REVISION_1 0x00000001
-
-typedef struct {
- UINT32 Revision; // Used for version identification for this structure
- UINT32 ArrayLength; // The entries number of the following ApicId array and SmBase array
- //
- // Data required for SMBASE relocation
- //
- UINT64 *ApicId; // Pointer to ApicId array
- UINTN *SmBase; // Pointer to SmBase array
- UINT32 Reserved;
- UINT32 SmrrBase;
- UINT32 SmrrSize;
-} CPU_HOT_PLUG_DATA;
-
-#endif
diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h deleted file mode 100644 index cd4e613ef5..0000000000 --- a/UefiCpuPkg/Include/Library/LocalApicLib.h +++ /dev/null @@ -1,415 +0,0 @@ -/** @file
- Public include file for Local APIC library.
-
- Local APIC library assumes local APIC is enabled. It does not
- handles cases where local APIC is disabled.
-
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __LOCAL_APIC_LIB_H__
-#define __LOCAL_APIC_LIB_H__
-
-#define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.
-#define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.
-
-/**
- Retrieve the base address of local APIC.
-
- @return The base address of local APIC.
-
-**/
-UINTN
-EFIAPI
-GetLocalApicBaseAddress (
- VOID
- );
-
-/**
- Set the base address of local APIC.
-
- If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
-
- @param[in] BaseAddress Local APIC base address to be set.
-
-**/
-VOID
-EFIAPI
-SetLocalApicBaseAddress (
- IN UINTN BaseAddress
- );
-
-/**
- Get the current local APIC mode.
-
- If local APIC is disabled, then ASSERT.
-
- @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
- @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
-**/
-UINTN
-EFIAPI
-GetApicMode (
- VOID
- );
-
-/**
- Set the current local APIC mode.
-
- If the specified local APIC mode is not valid, then ASSERT.
- If the specified local APIC mode can't be set as current, then ASSERT.
-
- @param ApicMode APIC mode to be set.
-
- @note This API must not be called from an interrupt handler or SMI handler.
- It may result in unpredictable behavior.
-**/
-VOID
-EFIAPI
-SetApicMode (
- IN UINTN ApicMode
- );
-
-/**
- Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
-
- In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
- In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
- the 32-bit local APIC ID is returned as initial APIC ID.
-
- @return 32-bit initial local APIC ID of the executing processor.
-**/
-UINT32
-EFIAPI
-GetInitialApicId (
- VOID
- );
-
-/**
- Get the local APIC ID of the executing processor.
-
- @return 32-bit local APIC ID of the executing processor.
-**/
-UINT32
-EFIAPI
-GetApicId (
- VOID
- );
-
-/**
- Get the value of the local APIC version register.
-
- @return the value of the local APIC version register.
-**/
-UINT32
-EFIAPI
-GetApicVersion (
- VOID
- );
-
-/**
- Send a Fixed IPI to a specified target processor.
-
- This function returns after the IPI has been accepted by the target processor.
-
- @param ApicId The local APIC ID of the target processor.
- @param Vector The vector number of the interrupt being sent.
-**/
-VOID
-EFIAPI
-SendFixedIpi (
- IN UINT32 ApicId,
- IN UINT8 Vector
- );
-
-/**
- Send a Fixed IPI to all processors excluding self.
-
- This function returns after the IPI has been accepted by the target processors.
-
- @param Vector The vector number of the interrupt being sent.
-**/
-VOID
-EFIAPI
-SendFixedIpiAllExcludingSelf (
- IN UINT8 Vector
- );
-
-/**
- Send a SMI IPI to a specified target processor.
-
- This function returns after the IPI has been accepted by the target processor.
-
- @param ApicId Specify the local APIC ID of the target processor.
-**/
-VOID
-EFIAPI
-SendSmiIpi (
- IN UINT32 ApicId
- );
-
-/**
- Send a SMI IPI to all processors excluding self.
-
- This function returns after the IPI has been accepted by the target processors.
-**/
-VOID
-EFIAPI
-SendSmiIpiAllExcludingSelf (
- VOID
- );
-
-/**
- Send an INIT IPI to a specified target processor.
-
- This function returns after the IPI has been accepted by the target processor.
-
- @param ApicId Specify the local APIC ID of the target processor.
-**/
-VOID
-EFIAPI
-SendInitIpi (
- IN UINT32 ApicId
- );
-
-/**
- Send an INIT IPI to all processors excluding self.
-
- This function returns after the IPI has been accepted by the target processors.
-**/
-VOID
-EFIAPI
-SendInitIpiAllExcludingSelf (
- VOID
- );
-
-/**
- Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
-
- This function returns after the IPI has been accepted by the target processor.
-
- if StartupRoutine >= 1M, then ASSERT.
- if StartupRoutine is not multiple of 4K, then ASSERT.
-
- @param ApicId Specify the local APIC ID of the target processor.
- @param StartupRoutine Points to a start-up routine which is below 1M physical
- address and 4K aligned.
-**/
-VOID
-EFIAPI
-SendInitSipiSipi (
- IN UINT32 ApicId,
- IN UINT32 StartupRoutine
- );
-
-/**
- Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
-
- This function returns after the IPI has been accepted by the target processors.
-
- if StartupRoutine >= 1M, then ASSERT.
- if StartupRoutine is not multiple of 4K, then ASSERT.
-
- @param StartupRoutine Points to a start-up routine which is below 1M physical
- address and 4K aligned.
-**/
-VOID
-EFIAPI
-SendInitSipiSipiAllExcludingSelf (
- IN UINT32 StartupRoutine
- );
-
-/**
- Initialize the state of the SoftwareEnable bit in the Local APIC
- Spurious Interrupt Vector register.
-
- @param Enable If TRUE, then set SoftwareEnable to 1
- If FALSE, then set SoftwareEnable to 0.
-
-**/
-VOID
-EFIAPI
-InitializeLocalApicSoftwareEnable (
- IN BOOLEAN Enable
- );
-
-/**
- Programming Virtual Wire Mode.
-
- This function programs the local APIC for virtual wire mode following
- the example described in chapter A.3 of the MP 1.4 spec.
-
- IOxAPIC is not involved in this type of virtual wire mode.
-**/
-VOID
-EFIAPI
-ProgramVirtualWireMode (
- VOID
- );
-
-/**
- Disable LINT0 & LINT1 interrupts.
-
- This function sets the mask flag in the LVT LINT0 & LINT1 registers.
-**/
-VOID
-EFIAPI
-DisableLvtInterrupts (
- VOID
- );
-
-/**
- Read the initial count value from the init-count register.
-
- @return The initial count value read from the init-count register.
-**/
-UINT32
-EFIAPI
-GetApicTimerInitCount (
- VOID
- );
-
-/**
- Read the current count value from the current-count register.
-
- @return The current count value read from the current-count register.
-**/
-UINT32
-EFIAPI
-GetApicTimerCurrentCount (
- VOID
- );
-
-/**
- Initialize the local APIC timer.
-
- The local APIC timer is initialized and enabled.
-
- @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
- If it is 0, then use the current divide value in the DCR.
- @param InitCount The initial count value.
- @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
- @param Vector The timer interrupt vector number.
-**/
-VOID
-EFIAPI
-InitializeApicTimer (
- IN UINTN DivideValue,
- IN UINT32 InitCount,
- IN BOOLEAN PeriodicMode,
- IN UINT8 Vector
- );
-
-/**
- Get the state of the local APIC timer.
-
- @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
- @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
- @param Vector Return the timer interrupt vector number.
-**/
-VOID
-EFIAPI
-GetApicTimerState (
- OUT UINTN *DivideValue OPTIONAL,
- OUT BOOLEAN *PeriodicMode OPTIONAL,
- OUT UINT8 *Vector OPTIONAL
- );
-
-/**
- Enable the local APIC timer interrupt.
-**/
-VOID
-EFIAPI
-EnableApicTimerInterrupt (
- VOID
- );
-
-/**
- Disable the local APIC timer interrupt.
-**/
-VOID
-EFIAPI
-DisableApicTimerInterrupt (
- VOID
- );
-
-/**
- Get the local APIC timer interrupt state.
-
- @retval TRUE The local APIC timer interrupt is enabled.
- @retval FALSE The local APIC timer interrupt is disabled.
-**/
-BOOLEAN
-EFIAPI
-GetApicTimerInterruptState (
- VOID
- );
-
-/**
- Send EOI to the local APIC.
-**/
-VOID
-EFIAPI
-SendApicEoi (
- VOID
- );
-
-/**
- Get the 32-bit address that a device should use to send a Message Signaled
- Interrupt (MSI) to the Local APIC of the currently executing processor.
-
- @return 32-bit address used to send an MSI to the Local APIC.
-**/
-UINT32
-EFIAPI
-GetApicMsiAddress (
- VOID
- );
-
-/**
- Get the 64-bit data value that a device should use to send a Message Signaled
- Interrupt (MSI) to the Local APIC of the currently executing processor.
-
- If Vector is not in range 0x10..0xFE, then ASSERT().
- If DeliveryMode is not supported, then ASSERT().
-
- @param Vector The 8-bit interrupt vector associated with the MSI.
- Must be in the range 0x10..0xFE
- @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
- is handled. The only supported values are:
- 0: LOCAL_APIC_DELIVERY_MODE_FIXED
- 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
- 2: LOCAL_APIC_DELIVERY_MODE_SMI
- 4: LOCAL_APIC_DELIVERY_MODE_NMI
- 5: LOCAL_APIC_DELIVERY_MODE_INIT
- 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
-
- @param LevelTriggered TRUE specifies a level triggered interrupt.
- FALSE specifies an edge triggered interrupt.
- @param AssertionLevel Ignored if LevelTriggered is FALSE.
- TRUE specifies a level triggered interrupt that active
- when the interrupt line is asserted.
- FALSE specifies a level triggered interrupt that active
- when the interrupt line is deasserted.
-
- @return 64-bit data value used to send an MSI to the Local APIC.
-**/
-UINT64
-EFIAPI
-GetApicMsiValue (
- IN UINT8 Vector,
- IN UINTN DeliveryMode,
- IN BOOLEAN LevelTriggered,
- IN BOOLEAN AssertionLevel
- );
-
-#endif
-
diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Library/MtrrLib.h deleted file mode 100644 index 36cd2cd6d5..0000000000 --- a/UefiCpuPkg/Include/Library/MtrrLib.h +++ /dev/null @@ -1,386 +0,0 @@ -/** @file
- MTRR setting library
-
- Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _MTRR_LIB_H_
-#define _MTRR_LIB_H_
-
-//
-// According to IA32 SDM, MTRRs number and msr offset are always consistent
-// for IA32 processor family
-//
-
-//
-// The semantics of below macro is MAX_MTRR_NUMBER_OF_VARIABLE_MTRR, the real number can be read out from MTRR_CAP register.
-//
-#define MTRR_NUMBER_OF_VARIABLE_MTRR 32
-//
-// Firmware need reserve 2 MTRR for OS
-// Note: It is replaced by PCD PcdCpuNumberOfReservedVariableMtrrs
-//
-#define RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER 2
-
-#define MTRR_NUMBER_OF_FIXED_MTRR 11
-//
-// Below macro is deprecated, and should not be used.
-//
-#define FIRMWARE_VARIABLE_MTRR_NUMBER 6
-#define MTRR_LIB_IA32_MTRR_CAP 0x0FE
-#define MTRR_LIB_IA32_MTRR_CAP_VCNT_MASK 0x0FF
-#define MTRR_LIB_IA32_MTRR_FIX64K_00000 0x250
-#define MTRR_LIB_IA32_MTRR_FIX16K_80000 0x258
-#define MTRR_LIB_IA32_MTRR_FIX16K_A0000 0x259
-#define MTRR_LIB_IA32_MTRR_FIX4K_C0000 0x268
-#define MTRR_LIB_IA32_MTRR_FIX4K_C8000 0x269
-#define MTRR_LIB_IA32_MTRR_FIX4K_D0000 0x26A
-#define MTRR_LIB_IA32_MTRR_FIX4K_D8000 0x26B
-#define MTRR_LIB_IA32_MTRR_FIX4K_E0000 0x26C
-#define MTRR_LIB_IA32_MTRR_FIX4K_E8000 0x26D
-#define MTRR_LIB_IA32_MTRR_FIX4K_F0000 0x26E
-#define MTRR_LIB_IA32_MTRR_FIX4K_F8000 0x26F
-#define MTRR_LIB_IA32_VARIABLE_MTRR_BASE 0x200
-//
-// Below macro is deprecated, and should not be used.
-//
-#define MTRR_LIB_IA32_VARIABLE_MTRR_END 0x20F
-#define MTRR_LIB_IA32_MTRR_DEF_TYPE 0x2FF
-#define MTRR_LIB_MSR_VALID_MASK 0xFFFFFFFFFULL
-#define MTRR_LIB_CACHE_VALID_ADDRESS 0xFFFFFF000ULL
-#define MTRR_LIB_CACHE_MTRR_ENABLED 0x800
-#define MTRR_LIB_CACHE_FIXED_MTRR_ENABLED 0x400
-
-//
-// Structure to describe a fixed MTRR
-//
-typedef struct {
- UINT32 Msr;
- UINT32 BaseAddress;
- UINT32 Length;
-} FIXED_MTRR;
-
-//
-// Structure to describe a variable MTRR
-//
-typedef struct {
- UINT64 BaseAddress;
- UINT64 Length;
- UINT64 Type;
- UINT32 Msr;
- BOOLEAN Valid;
- BOOLEAN Used;
-} VARIABLE_MTRR;
-
-//
-// Structure to hold base and mask pair for variable MTRR register
-//
-typedef struct _MTRR_VARIABLE_SETTING_ {
- UINT64 Base;
- UINT64 Mask;
-} MTRR_VARIABLE_SETTING;
-
-//
-// Array for variable MTRRs
-//
-typedef struct _MTRR_VARIABLE_SETTINGS_ {
- MTRR_VARIABLE_SETTING Mtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
-} MTRR_VARIABLE_SETTINGS;
-
-//
-// Array for fixed mtrrs
-//
-typedef struct _MTRR_FIXED_SETTINGS_ {
- UINT64 Mtrr[MTRR_NUMBER_OF_FIXED_MTRR];
-} MTRR_FIXED_SETTINGS;
-
-//
-// Structure to hold all MTRRs
-//
-typedef struct _MTRR_SETTINGS_ {
- MTRR_FIXED_SETTINGS Fixed;
- MTRR_VARIABLE_SETTINGS Variables;
- UINT64 MtrrDefType;
-} MTRR_SETTINGS;
-
-//
-// Memory cache types
-//
-typedef enum {
- CacheUncacheable = 0,
- CacheWriteCombining = 1,
- CacheWriteThrough = 4,
- CacheWriteProtected = 5,
- CacheWriteBack = 6
-} MTRR_MEMORY_CACHE_TYPE;
-
-#define MTRR_CACHE_UNCACHEABLE 0
-#define MTRR_CACHE_WRITE_COMBINING 1
-#define MTRR_CACHE_WRITE_THROUGH 4
-#define MTRR_CACHE_WRITE_PROTECTED 5
-#define MTRR_CACHE_WRITE_BACK 6
-#define MTRR_CACHE_INVALID_TYPE 7
-
-/**
- Returns the variable MTRR count for the CPU.
-
- @return Variable MTRR count
-
-**/
-UINT32
-EFIAPI
-GetVariableMtrrCount (
- VOID
- );
-
-/**
- Returns the firmware usable variable MTRR count for the CPU.
-
- @return Firmware usable variable MTRR count
-
-**/
-UINT32
-EFIAPI
-GetFirmwareVariableMtrrCount (
- VOID
- );
-
-/**
- This function attempts to set the attributes for a memory range.
-
- @param[in] BaseAddress The physical address that is the start
- address of a memory region.
- @param[in] Length The size in bytes of the memory region.
- @param[in] Attribute The bit mask of attributes to set for the
- memory region.
-
- @retval RETURN_SUCCESS The attributes were set for the memory
- region.
- @retval RETURN_INVALID_PARAMETER Length is zero.
- @retval RETURN_UNSUPPORTED The processor does not support one or
- more bytes of the memory resource range
- specified by BaseAddress and Length.
- @retval RETURN_UNSUPPORTED The bit mask of attributes is not support
- for the memory resource range specified
- by BaseAddress and Length.
- @retval RETURN_ACCESS_DENIED The attributes for the memory resource
- range specified by BaseAddress and Length
- cannot be modified.
- @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to
- modify the attributes of the memory
- resource range.
-
-**/
-RETURN_STATUS
-EFIAPI
-MtrrSetMemoryAttribute (
- IN PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN MTRR_MEMORY_CACHE_TYPE Attribute
- );
-
-
-/**
- This function will get the memory cache type of the specific address.
- This function is mainly for debugging purposes.
-
- @param[in] Address The specific address
-
- @return The memory cache type of the specific address
-
-**/
-MTRR_MEMORY_CACHE_TYPE
-EFIAPI
-MtrrGetMemoryAttribute (
- IN PHYSICAL_ADDRESS Address
- );
-
-
-/**
- This function will get the raw value in variable MTRRs
-
- @param[out] VariableSettings A buffer to hold variable MTRRs content.
-
- @return The buffer point to MTRR_VARIABLE_SETTINGS in which holds the content of the variable mtrr
-
-**/
-MTRR_VARIABLE_SETTINGS*
-EFIAPI
-MtrrGetVariableMtrr (
- OUT MTRR_VARIABLE_SETTINGS *VariableSettings
- );
-
-
-/**
- This function sets fixed MTRRs
-
- @param[in] VariableSettings A buffer to hold variable MTRRs content.
-
- @return The pointer of VariableSettings
-
-**/
-MTRR_VARIABLE_SETTINGS*
-EFIAPI
-MtrrSetVariableMtrr (
- IN MTRR_VARIABLE_SETTINGS *VariableSettings
- );
-
-
-/**
- This function gets the content in fixed MTRRs
-
- @param[out] FixedSettings A buffer to hold fixed MTRRs content.
-
- @return The pointer of FixedSettings
-
-**/
-MTRR_FIXED_SETTINGS*
-EFIAPI
-MtrrGetFixedMtrr (
- OUT MTRR_FIXED_SETTINGS *FixedSettings
- );
-
-
-/**
- This function sets fixed MTRRs
-
- @param[in] FixedSettings A buffer holding fixed MTRRs content.
-
- @return The pointer of FixedSettings
-
-**/
-MTRR_FIXED_SETTINGS*
-EFIAPI
-MtrrSetFixedMtrr (
- IN MTRR_FIXED_SETTINGS *FixedSettings
- );
-
-
-/**
- This function gets the content in all MTRRs (variable and fixed)
-
- @param[out] MtrrSetting A buffer to hold all MTRRs content.
-
- @return The pointer of MtrrSetting
-
-**/
-MTRR_SETTINGS *
-EFIAPI
-MtrrGetAllMtrrs (
- OUT MTRR_SETTINGS *MtrrSetting
- );
-
-
-/**
- This function sets all MTRRs (variable and fixed)
-
- @param[in] MtrrSetting A buffer to hold all MTRRs content.
-
- @return The pointer of MtrrSetting
-
-**/
-MTRR_SETTINGS *
-EFIAPI
-MtrrSetAllMtrrs (
- IN MTRR_SETTINGS *MtrrSetting
- );
-
-
-/**
- Get the attribute of variable MTRRs.
-
- This function shadows the content of variable MTRRs into
- an internal array: VariableMtrr
-
- @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR
- @param[in] MtrrValidAddressMask The valid address mask for MTRR since the base address in
- MTRR must align to 4K, so valid address mask equal to
- MtrrValidBitsMask & 0xfffffffffffff000ULL
- @param[out] VariableMtrr The array to shadow variable MTRRs content
-
- @return The ruturn value of this paramter indicates the number of
- MTRRs which has been used.
-**/
-UINT32
-EFIAPI
-MtrrGetMemoryAttributeInVariableMtrr (
- IN UINT64 MtrrValidBitsMask,
- IN UINT64 MtrrValidAddressMask,
- OUT VARIABLE_MTRR *VariableMtrr
- );
-
-
-/**
- This function prints all MTRRs for debugging.
-**/
-VOID
-EFIAPI
-MtrrDebugPrintAllMtrrs (
- VOID
- );
-
-/**
- Checks if MTRR is supported.
-
- @retval TRUE MTRR is supported.
- @retval FALSE MTRR is not supported.
-
-**/
-BOOLEAN
-EFIAPI
-IsMtrrSupported (
- VOID
- );
-
-/**
- Returns the default MTRR cache type for the system.
-
- @return The default MTRR cache type.
-
-**/
-MTRR_MEMORY_CACHE_TYPE
-EFIAPI
-MtrrGetDefaultMemoryType (
- VOID
- );
-
-/**
- This function attempts to set the attributes into MTRR setting buffer for a memory range.
-
- @param[in, out] MtrrSetting MTRR setting buffer to be set.
- @param[in] BaseAddress The physical address that is the start address
- of a memory region.
- @param[in] Length The size in bytes of the memory region.
- @param[in] Attribute The bit mask of attributes to set for the
- memory region.
-
- @retval RETURN_SUCCESS The attributes were set for the memory region.
- @retval RETURN_INVALID_PARAMETER Length is zero.
- @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the
- memory resource range specified by BaseAddress and Length.
- @retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource
- range specified by BaseAddress and Length.
- @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by
- BaseAddress and Length cannot be modified.
- @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
- the memory resource range.
-
-**/
-RETURN_STATUS
-EFIAPI
-MtrrSetMemoryAttributeInMtrrSettings (
- IN OUT MTRR_SETTINGS *MtrrSetting,
- IN PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN MTRR_MEMORY_CACHE_TYPE Attribute
- );
-
-#endif // _MTRR_LIB_H_
diff --git a/UefiCpuPkg/Include/Library/PlatformSecLib.h b/UefiCpuPkg/Include/Library/PlatformSecLib.h deleted file mode 100644 index 0af7781771..0000000000 --- a/UefiCpuPkg/Include/Library/PlatformSecLib.h +++ /dev/null @@ -1,70 +0,0 @@ -/** @file
-This library class defines interface for platform to perform platform
-specific initialization in SEC phase.
-
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __PLATFORM_SEC_LIB_H__
-#define __PLATFORM_SEC_LIB_H__
-
-/**
- A developer supplied function to perform platform specific operations.
-
- It's a developer supplied function to perform any operations appropriate to a
- given platform. It's invoked just before passing control to PEI core by SEC
- core. Platform developer may modify the SecCoreData passed to PEI Core.
- It returns a platform specific PPI list that platform wishes to pass to PEI core.
- The Generic SEC core module will merge this list to join the final list passed to
- PEI core.
-
- @param SecCoreData The same parameter as passing to PEI core. It
- could be overridden by this function.
-
- @return The platform specific PPI list to be passed to PEI core or
- NULL if there is no need of such platform specific PPI list.
-
-**/
-EFI_PEI_PPI_DESCRIPTOR *
-EFIAPI
-SecPlatformMain (
- IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
- );
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param PeiServices Pointer to the PEI Services Table.
- @param StructureSize Pointer to the variable describing size of the input buffer.
- @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- );
-
-/**
- This interface disables temporary memory in SEC Phase.
-**/
-VOID
-EFIAPI
-SecPlatformDisableTemporaryMemory (
- VOID
- );
-
-#endif
diff --git a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h deleted file mode 100644 index 4478003467..0000000000 --- a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h +++ /dev/null @@ -1,401 +0,0 @@ -/** @file
-Library that provides CPU specific functions to support the PiSmmCpuDxeSmm module.
-
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __SMM_FEATURES_LIB_H__
-#define __SMM_FEATURES_LIB_H__
-
-#include <Protocol/MpService.h>
-#include <Protocol/SmmCpu.h>
-#include <Register/SmramSaveStateMap.h>
-#include <CpuHotPlugData.h>
-
-///
-/// Enumeration of SMM registers that are accessed using the library functions
-/// SmmCpuFeaturesIsSmmRegisterSupported (), SmmCpuFeaturesGetSmmRegister (),
-/// and SmmCpuFeaturesSetSmmRegister ().
-///
-typedef enum {
- ///
- /// Read-write register to provides access to MSR_SMM_FEATURE_CONTROL if the
- /// CPU supports this MSR.
- ///
- SmmRegFeatureControl,
- ///
- /// Read-only register that returns a non-zero value if the CPU is able to
- /// respond to SMIs.
- ///
- SmmRegSmmEnable,
- ///
- /// Read-only register that returns a non-zero value if the CPU is able to
- /// respond to SMIs, but is busy with other actions that are causing a delay
- /// in responding to an SMI. This register abstracts access to MSR_SMM_DELAYED
- /// if the CPU supports this MSR.
- ///
- SmmRegSmmDelayed,
- ///
- /// Read-only register that returns a non-zero value if the CPU is able to
- /// respond to SMIs, but is busy with other actions that are blocking its
- /// ability to respond to an SMI. This register abstracts access to
- /// MSR_SMM_BLOCKED if the CPU supports this MSR.
- ///
- SmmRegSmmBlocked
-} SMM_REG_NAME;
-
-/**
- Called during the very first SMI into System Management Mode to initialize
- CPU features, including SMBASE, for the currently executing CPU. Since this
- is the first SMI, the SMRAM Save State Map is at the default address of
- SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
- CPU is specified by CpuIndex and CpuIndex can be used to access information
- about the currently executing CPU in the ProcessorInfo array and the
- HotPlugCpuData data structure.
-
- @param[in] CpuIndex The index of the CPU to initialize. The value
- must be between 0 and the NumberOfCpus field in
- the System Management System Table (SMST).
- @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
- was elected as monarch during System Management
- Mode initialization.
- FALSE if the CpuIndex is not the index of the CPU
- that was elected as monarch during System
- Management Mode initialization.
- @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
- structures. ProcessorInfo[CpuIndex] contains the
- information for the currently executing CPU.
- @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
- contains the ApidId and SmBase arrays.
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesInitializeProcessor (
- IN UINTN CpuIndex,
- IN BOOLEAN IsMonarch,
- IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
- IN CPU_HOT_PLUG_DATA *CpuHotPlugData
- );
-
-/**
- This function updates the SMRAM save state on the currently executing CPU
- to resume execution at a specific address after an RSM instruction. This
- function must evaluate the SMRAM save state to determine the execution mode
- the RSM instruction resumes and update the resume execution address with
- either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
- flag in the SMRAM save state must always be cleared. This function returns
- the value of the instruction pointer from the SMRAM save state that was
- replaced. If this function returns 0, then the SMRAM save state was not
- modified.
-
- This function is called during the very first SMI on each CPU after
- SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
- to signal that the SMBASE of each CPU has been updated before the default
- SMBASE address is used for the first SMI to the next CPU.
-
- @param[in] CpuIndex The index of the CPU to hook. The value
- must be between 0 and the NumberOfCpus
- field in the System Management System Table
- (SMST).
- @param[in] CpuState Pointer to SMRAM Save State Map for the
- currently executing CPU.
- @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
- 32-bit execution mode from 64-bit SMM.
- @param[in] NewInstructionPointer Instruction pointer to use if resuming to
- same execution mode as SMM.
-
- @retval 0 This function did modify the SMRAM save state.
- @retval > 0 The original instruction pointer value from the SMRAM save state
- before it was replaced.
-**/
-UINT64
-EFIAPI
-SmmCpuFeaturesHookReturnFromSmm (
- IN UINTN CpuIndex,
- IN SMRAM_SAVE_STATE_MAP *CpuState,
- IN UINT64 NewInstructionPointer32,
- IN UINT64 NewInstructionPointer
- );
-
-/**
- Hook point in normal execution mode that allows the one CPU that was elected
- as monarch during System Management Mode initialization to perform additional
- initialization actions immediately after all of the CPUs have processed their
- first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
- into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesSmmRelocationComplete (
- VOID
- );
-
-/**
- Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
- returned, then a custom SMI handler is not provided by this library,
- and the default SMI handler must be used.
-
- @retval 0 Use the default SMI handler.
- @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
- The caller is required to allocate enough SMRAM for each CPU to
- support the size of the custom SMI handler.
-**/
-UINTN
-EFIAPI
-SmmCpuFeaturesGetSmiHandlerSize (
- VOID
- );
-
-/**
- Install a custom SMI handler for the CPU specified by CpuIndex. This function
- is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
- than zero and is called by the CPU that was elected as monarch during System
- Management Mode initialization.
-
- @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
- The value must be between 0 and the NumberOfCpus field
- in the System Management System Table (SMST).
- @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
- @param[in] SmiStack The stack to use when an SMI is processed by the
- the CPU specified by CpuIndex.
- @param[in] StackSize The size, in bytes, if the stack used when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] GdtBase The base address of the GDT to use when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] IdtBase The base address of the IDT to use when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] Cr3 The base address of the page tables to use when an SMI
- is processed by the CPU specified by CpuIndex.
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesInstallSmiHandler (
- IN UINTN CpuIndex,
- IN UINT32 SmBase,
- IN VOID *SmiStack,
- IN UINTN StackSize,
- IN UINTN GdtBase,
- IN UINTN GdtSize,
- IN UINTN IdtBase,
- IN UINTN IdtSize,
- IN UINT32 Cr3
- );
-
-/**
- Determines if MTRR registers must be configured to set SMRAM cache-ability
- when executing in System Management Mode.
-
- @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
- @retval FALSE MTRR registers do not need to be configured to set SMRAM
- cache-ability.
-**/
-BOOLEAN
-EFIAPI
-SmmCpuFeaturesNeedConfigureMtrrs (
- VOID
- );
-
-/**
- Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
- returns TRUE.
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesDisableSmrr (
- VOID
- );
-
-/**
- Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
- returns TRUE.
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesReenableSmrr (
- VOID
- );
-
-/**
- Processor specific hook point each time a CPU enters System Management Mode.
-
- @param[in] CpuIndex The index of the CPU that has entered SMM. The value
- must be between 0 and the NumberOfCpus field in the
- System Management System Table (SMST).
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesRendezvousEntry (
- IN UINTN CpuIndex
- );
-
-/**
- Processor specific hook point each time a CPU exits System Management Mode.
-
- @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must
- be between 0 and the NumberOfCpus field in the System
- Management System Table (SMST).
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesRendezvousExit (
- IN UINTN CpuIndex
- );
-
-/**
- Check to see if an SMM register is supported by a specified CPU.
-
- @param[in] CpuIndex The index of the CPU to check for SMM register support.
- The value must be between 0 and the NumberOfCpus field
- in the System Management System Table (SMST).
- @param[in] RegName Identifies the SMM register to check for support.
-
- @retval TRUE The SMM register specified by RegName is supported by the CPU
- specified by CpuIndex.
- @retval FALSE The SMM register specified by RegName is not supported by the
- CPU specified by CpuIndex.
-**/
-BOOLEAN
-EFIAPI
-SmmCpuFeaturesIsSmmRegisterSupported (
- IN UINTN CpuIndex,
- IN SMM_REG_NAME RegName
- );
-
-/**
- Returns the current value of the SMM register for the specified CPU.
- If the SMM register is not supported, then 0 is returned.
-
- @param[in] CpuIndex The index of the CPU to read the SMM register. The
- value must be between 0 and the NumberOfCpus field in
- the System Management System Table (SMST).
- @param[in] RegName Identifies the SMM register to read.
-
- @return The value of the SMM register specified by RegName from the CPU
- specified by CpuIndex.
-**/
-UINT64
-EFIAPI
-SmmCpuFeaturesGetSmmRegister (
- IN UINTN CpuIndex,
- IN SMM_REG_NAME RegName
- );
-
-/**
- Sets the value of an SMM register on a specified CPU.
- If the SMM register is not supported, then no action is performed.
-
- @param[in] CpuIndex The index of the CPU to write the SMM register. The
- value must be between 0 and the NumberOfCpus field in
- the System Management System Table (SMST).
- @param[in] RegName Identifies the SMM register to write.
- registers are read-only.
- @param[in] Value The value to write to the SMM register.
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesSetSmmRegister (
- IN UINTN CpuIndex,
- IN SMM_REG_NAME RegName,
- IN UINT64 Value
- );
-
-/**
- Read an SMM Save State register on the target processor. If this function
- returns EFI_UNSUPPORTED, then the caller is responsible for reading the
- SMM Save Sate register.
-
- @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
- value must be between 0 and the NumberOfCpus field in
- the System Management System Table (SMST).
- @param[in] Register The SMM Save State register to read.
- @param[in] Width The number of bytes to read from the CPU save state.
- @param[out] Buffer Upon return, this holds the CPU register value read
- from the save state.
-
- @retval EFI_SUCCESS The register was read from Save State.
- @retval EFI_INVALID_PARAMTER Buffer is NULL.
- @retval EFI_UNSUPPORTED This function does not support reading Register.
-
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesReadSaveStateRegister (
- IN UINTN CpuIndex,
- IN EFI_SMM_SAVE_STATE_REGISTER Register,
- IN UINTN Width,
- OUT VOID *Buffer
- );
-
-/**
- Writes an SMM Save State register on the target processor. If this function
- returns EFI_UNSUPPORTED, then the caller is responsible for writing the
- SMM Save Sate register.
-
- @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
- value must be between 0 and the NumberOfCpus field in
- the System Management System Table (SMST).
- @param[in] Register The SMM Save State register to write.
- @param[in] Width The number of bytes to write to the CPU save state.
- @param[in] Buffer Upon entry, this holds the new CPU register value.
-
- @retval EFI_SUCCESS The register was written to Save State.
- @retval EFI_INVALID_PARAMTER Buffer is NULL.
- @retval EFI_UNSUPPORTED This function does not support writing Register.
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesWriteSaveStateRegister (
- IN UINTN CpuIndex,
- IN EFI_SMM_SAVE_STATE_REGISTER Register,
- IN UINTN Width,
- IN CONST VOID *Buffer
- );
-
-/**
- This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
- notification is completely processed.
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesCompleteSmmReadyToLock (
- VOID
- );
-
-/**
- This API provides a method for a CPU to allocate a specific region for storing page tables.
-
- This API can be called more once to allocate memory for page tables.
-
- Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
- allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
- is returned. If there is not enough memory remaining to satisfy the request, then NULL is
- returned.
-
- This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
-
- @param Pages The number of 4 KB pages to allocate.
-
- @return A pointer to the allocated buffer for page tables.
- @retval NULL Fail to allocate a specific region for storing page tables,
- Or there is no preference on where the page tables are allocated in SMRAM.
-
-**/
-VOID *
-EFIAPI
-SmmCpuFeaturesAllocatePageTableMemory (
- IN UINTN Pages
- );
-
-#endif
diff --git a/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h b/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h deleted file mode 100644 index e40084edf9..0000000000 --- a/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h +++ /dev/null @@ -1,109 +0,0 @@ -/** @file
- Public include file for the SMM CPU Platform Hook Library.
-
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __SMM_CPU_PLATFORM_HOOK_LIB_H__
-#define __SMM_CPU_PLATFORM_HOOK_LIB_H__
-
-///
-/// SMM Page Size Type
-///
-typedef enum {
- SmmPageSize4K,
- SmmPageSize2M,
- SmmPageSize1G,
- MaxSmmPageSizeType
-} SMM_PAGE_SIZE_TYPE;
-
-/**
- Checks if platform produces a valid SMI.
-
- This function checks if platform produces a valid SMI. This function is
- called at SMM entry to detect if this is a spurious SMI. This function
- must be implemented in an MP safe way because it is called by multiple CPU
- threads.
-
- @retval TRUE There is a valid SMI
- @retval FALSE There is no valid SMI
-
-**/
-BOOLEAN
-EFIAPI
-PlatformValidSmi (
- VOID
- );
-
-/**
- Clears platform top level SMI status bit.
-
- This function clears platform top level SMI status bit.
-
- @retval TRUE The platform top level SMI status is cleared.
- @retval FALSE The platform top level SMI status cannot be cleared.
-
-**/
-BOOLEAN
-EFIAPI
-ClearTopLevelSmiStatus (
- VOID
- );
-
-/**
- Performs platform specific way of SMM BSP election.
-
- This function performs platform specific way of SMM BSP election.
-
- @param IsBsp Output parameter. TRUE: the CPU this function executes
- on is elected to be the SMM BSP. FALSE: the CPU this
- function executes on is to be SMM AP.
-
- @retval EFI_SUCCESS The function executes successfully.
- @retval EFI_NOT_READY The function does not determine whether this CPU should be
- BSP or AP. This may occur if hardware init sequence to
- enable the determination is yet to be done, or the function
- chooses not to do BSP election and will let SMM CPU driver to
- use its default BSP election process.
- @retval EFI_DEVICE_ERROR The function cannot determine whether this CPU should be
- BSP or AP due to hardware error.
-
-**/
-EFI_STATUS
-EFIAPI
-PlatformSmmBspElection (
- OUT BOOLEAN *IsBsp
- );
-
-/**
- Get platform page table attribute .
-
- This function gets page table attribute of platform.
-
- @param Address Input parameter. Obtain the page table entries attribute on this address.
- @param PageSize Output parameter. The size of the page.
- @param NumOfPages Output parameter. Number of page.
- @param PageAttribute Output parameter. Paging Attributes (WB, UC, etc).
-
- @retval EFI_SUCCESS The platform page table attribute from the address is determined.
- @retval EFI_UNSUPPORTED The platform does not support getting page table attribute for the address.
-
-**/
-EFI_STATUS
-EFIAPI
-GetPlatformPageTableAttribute (
- IN UINT64 Address,
- OUT SMM_PAGE_SIZE_TYPE *PageSize,
- OUT UINTN *NumOfPages,
- OUT UINTN *PageAttribute
- );
-
-#endif
diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/Library/UefiCpuLib.h deleted file mode 100644 index 561d579968..0000000000 --- a/UefiCpuPkg/Include/Library/UefiCpuLib.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @file
- Public header file for UEFI CPU library class.
-
- This library class defines some routines that are generic for IA32 family CPU
- to be UEFI specification compliant.
-
- Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __UEFI_CPU_LIB_H__
-#define __UEFI_CPU_LIB_H__
-
-
-
-/**
- Initializes floating point units for requirement of UEFI specification.
-
- This function initializes floating-point control word to 0x027F (all exceptions
- masked,double-precision, round-to-nearest) and multimedia-extensions control word
- (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
- for masked underflow).
-
-**/
-VOID
-EFIAPI
-InitializeFloatingPointUnits (
- VOID
- );
-
-#endif
diff --git a/UefiCpuPkg/Include/Protocol/SmmCpuService.h b/UefiCpuPkg/Include/Protocol/SmmCpuService.h deleted file mode 100644 index 9aced54f4d..0000000000 --- a/UefiCpuPkg/Include/Protocol/SmmCpuService.h +++ /dev/null @@ -1,209 +0,0 @@ -/** @file
-SMM CPU Service protocol definition.
-
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _SMM_CPU_SERVICE_PROTOCOL_H_
-#define _SMM_CPU_SERVICE_PROTOCOL_H_
-
-//
-// Share some definitions with MP Services and CPU Arch Protocol
-//
-#include <Protocol/MpService.h>
-#include <Protocol/Cpu.h>
-
-#define EFI_SMM_CPU_SERVICE_PROTOCOL_GUID \
- { \
- 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 } \
- }
-
-typedef struct _EFI_SMM_CPU_SERVICE_PROTOCOL EFI_SMM_CPU_SERVICE_PROTOCOL;
-
-//
-// Protocol functions
-//
-
-/**
- Gets processor information on the requested processor at the
- instant this call is made. This service may only be called from the BSP.
-
- @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL
- instance.
- @param[in] ProcessorNumber The handle number of processor.
- @param[out] ProcessorInfoBuffer A pointer to the buffer where information for
- the requested processor is deposited.
-
- @retval EFI_SUCCESS Processor information was returned.
- @retval EFI_DEVICE_ERROR The calling processor is an AP.
- @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
- @retval EFI_NOT_FOUND The processor with the handle specified by
- ProcessorNumber does not exist in the platform.
-**/
-typedef
-EFI_STATUS
-(EFIAPI * EFI_SMM_GET_PROCESSOR_INFO) (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN UINTN ProcessorNumber,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
- );
-
-/**
- This service switches the requested AP to be the BSP from that point onward.
- This service changes the BSP for all purposes. This call can only be performed
- by the current BSP.
-
- This service switches the requested AP to be the BSP from that point onward.
- This service changes the BSP for all purposes. The new BSP can take over the
- execution of the old BSP and continue seamlessly from where the old one left
- off.
-
- If the BSP cannot be switched prior to the return from this service, then
- EFI_UNSUPPORTED must be returned.
-
- @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
- @param[in] ProcessorNumber The handle number of AP that is to become the new
- BSP. The range is from 0 to the total number of
- logical processors minus 1.
-
- @retval EFI_SUCCESS BSP successfully switched.
- @retval EFI_UNSUPPORTED Switching the BSP cannot be completed prior to
- this service returning.
- @retval EFI_UNSUPPORTED Switching the BSP is not supported.
- @retval EFI_SUCCESS The calling processor is an AP.
- @retval EFI_NOT_FOUND The processor with the handle specified by
- ProcessorNumber does not exist.
- @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or
- a disabled AP.
- @retval EFI_NOT_READY The specified AP is busy.
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI * EFI_SMM_SWITCH_BSP) (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN UINTN ProcessorNumber
- );
-
-/**
- Notify that a new processor has been added to the system.
-
- The SMM CPU driver should add the processor to the SMM CPU list.
-
- If the processor is disabled it won't participate any SMI handler during subsequent SMIs.
-
- @param This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
- @param ProcessorId The hardware ID of the processor.
- @param ProcessorNumber The handle number of processor.
- @param ProcessorResource A pointer to EFI_SMM_PROCESSOR_RESOURCE which holds the assigned resources.
-
- @retval EFI_SUCCESS The function completed successfully.
- @retval EFI_ALREADY_STARTED Processor already present.
- @retval EFI_NOT_READY Space for a new handle could not be allocated.
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_ADD_PROCESSOR) (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN UINT64 ProcessorId,
- OUT UINTN *ProcessorNumber
- );
-
-/**
- Notify that a processor is hot-removed.
-
- Remove a processor from the CPU list of the SMM CPU driver. After this API is called, the removed processor
- must not respond to SMIs in the coherence domain.
-
- @param This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
- @param ProcessorId The hardware ID of the processor.
-
- @retval EFI_SUCCESS The function completed successfully.
- @retval EFI_NOT_FOUND Processor with the hardware ID specified by ProcessorId does not exist.
- @retval EFI_NOT_READY Specified AP is busy.
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_REMOVE_PROCESSOR) (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN UINTN ProcessorNumber
- );
-
-/**
- This return the handle number for the calling processor. This service may be
- called from the BSP and APs.
-
- This service returns the processor handle number for the calling processor.
- The returned value is in the range from 0 to the total number of logical
- processors minus 1. This service may be called from the BSP and APs.
- If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER
- is returned. Otherwise, the current processors handle number is returned in
- ProcessorNumber, and EFI_SUCCESS is returned.
-
- @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
- @param[in] ProcessorNumber The handle number of AP that is to become the new
- BSP. The range is from 0 to the total number of
- logical processors minus 1.
-
- @retval EFI_SUCCESS The current processor handle number was returned
- in ProcessorNumber.
- @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI * EFI_SMM_WHOAMI) (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- OUT UINTN *ProcessorNumber
- );
-
-/**
- Register exception handler.
-
- @param This A pointer to the SMM_CPU_SERVICE_PROTOCOL instance.
- @param ExceptionType Defines which interrupt or exception to hook. Type EFI_EXCEPTION_TYPE and
- the valid values for this parameter are defined in EFI_DEBUG_SUPPORT_PROTOCOL
- of the UEFI 2.0 specification.
- @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER
- that is called when a processor interrupt occurs.
- If this parameter is NULL, then the handler will be uninstalled.
-
- @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
- @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
- @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
- @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER) (
- IN EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
- );
-
-//
-// This protocol provides CPU services from SMM.
-//
-struct _EFI_SMM_CPU_SERVICE_PROTOCOL {
- EFI_SMM_GET_PROCESSOR_INFO GetProcessorInfo;
- EFI_SMM_SWITCH_BSP SwitchBsp;
- EFI_SMM_ADD_PROCESSOR AddProcessor;
- EFI_SMM_REMOVE_PROCESSOR RemoveProcessor;
- EFI_SMM_WHOAMI WhoAmI;
- EFI_SMM_REGISTER_EXCEPTION_HANDLER RegisterExceptionHandler;
-};
-
-extern EFI_GUID gEfiSmmCpuServiceProtocolGuid;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h deleted file mode 100644 index a4702edc73..0000000000 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ /dev/null @@ -1,5801 +0,0 @@ -/** @file
- Architectural MSR Definitions.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.
-
-**/
-
-#ifndef __ARCHITECTURAL_MSR_H__
-#define __ARCHITECTURAL_MSR_H__
-
-/**
- See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
-
- @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
- AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
- @endcode
-**/
-#define MSR_IA32_P5_MC_ADDR 0x00000000
-
-
-/**
- See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.
-
- @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
- AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
- @endcode
-**/
-#define MSR_IA32_P5_MC_TYPE 0x00000001
-
-
-/**
- See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
- at Display Family / Display Model 0F_03H.
-
- @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
- AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
- @endcode
-**/
-#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
-
-
-/**
- See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /
- Display Model 05_01H.
-
- @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
- AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
- @endcode
-**/
-#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
-
-
-/**
- Platform ID (RO) The operating system can use this MSR to determine "slot"
- information for the processor and the proper microcode update to load.
- Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PLATFORM_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
- @endcode
-**/
-#define MSR_IA32_PLATFORM_ID 0x00000017
-
-/**
- MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:18;
- ///
- /// [Bits 52:50] Platform Id (RO) Contains information concerning the
- /// intended platform for the processor.
- /// 52 51 50
- /// -- -- --
- /// 0 0 0 Processor Flag 0.
- /// 0 0 1 Processor Flag 1
- /// 0 1 0 Processor Flag 2
- /// 0 1 1 Processor Flag 3
- /// 1 0 0 Processor Flag 4
- /// 1 0 1 Processor Flag 5
- /// 1 1 0 Processor Flag 6
- /// 1 1 1 Processor Flag 7
- ///
- UINT32 PlatformId:3;
- UINT32 Reserved3:11;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PLATFORM_ID_REGISTER;
-
-
-/**
- 06_01H.
-
- @param ECX MSR_IA32_APIC_BASE (0x0000001B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_APIC_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_APIC_BASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_APIC_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
- AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_APIC_BASE 0x0000001B
-
-/**
- MSR information returned for MSR index #MSR_IA32_APIC_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bit 8] BSP flag (R/W).
- ///
- UINT32 BSP:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
- /// Model 06_1AH.
- ///
- UINT32 EXTD:1;
- ///
- /// [Bit 11] APIC Global Enable (R/W).
- ///
- UINT32 EN:1;
- ///
- /// [Bits 31:12] APIC Base (R/W).
- ///
- UINT32 ApicBase:20;
- ///
- /// [Bits 63:32] APIC Base (R/W).
- ///
- UINT32 ApicBaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_APIC_BASE_REGISTER;
-
-
-/**
- Control Features in Intel 64 Processor (R/W). If any one enumeration
- condition for defined bit field holds.
-
- @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
- AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_FEATURE_CONTROL 0x0000003A
-
-/**
- MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
- /// being written, writes to this bit will result in GP(0). Note: Once the
- /// Lock bit is set, the contents of this register cannot be modified.
- /// Therefore the lock bit must be set after configuring support for Intel
- /// Virtualization Technology and prior to transferring control to an
- /// option ROM or the OS. Hence, once the Lock bit is set, the entire
- /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
- /// is not deasserted. If any one enumeration condition for defined bit
- /// field position greater than bit 0 holds.
- ///
- UINT32 Lock:1;
- ///
- /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
- /// system executive to use VMX in conjunction with SMX to support
- /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
- /// when the CPUID function 1 returns VMX feature flag and SMX feature
- /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
- /// CPUID.01H:ECX[6] = 1.
- ///
- UINT32 EnableVmxInsideSmx:1;
- ///
- /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
- /// for system executive that do not require SMX. BIOS must set this bit
- /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
- /// 5). If CPUID.01H:ECX[5] = 1.
- ///
- UINT32 EnableVmxOutsideSmx:1;
- UINT32 Reserved1:5;
- ///
- /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
- /// in the field represents an enable control for a corresponding SENTER
- /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
- /// CPUID.01H:ECX[6] = 1.
- ///
- UINT32 SenterLocalFunctionEnables:7;
- ///
- /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
- /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
- /// 6] is set. If CPUID.01H:ECX[6] = 1.
- ///
- UINT32 SenterGlobalEnable:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
- /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is
- /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
- ///
- UINT32 SgxEnable:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 20] LMCE On (R/WL): When set, system software can program the
- /// MSRs associated with LMCE to configure delivery of some machine check
- /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
- ///
- UINT32 LmceOn:1;
- UINT32 Reserved4:11;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_FEATURE_CONTROL_REGISTER;
-
-
-/**
- Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
- ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
- a logical processor. Reset value is Zero. A write to IA32_TSC will modify
- the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
- not affect the internal invariant TSC hardware.
-
- @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
- AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
- @endcode
-**/
-#define MSR_IA32_TSC_ADJUST 0x0000003B
-
-
-/**
- BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
- microcode update to be loaded into the processor. See Section 9.11.6,
- "Microcode Update Loader." A processor may prevent writing to this MSR when
- loading guest states on VM entries or saving guest states on VM exits.
- Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = 0;
- AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
- @endcode
-**/
-#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
-
-
-/**
- BIOS Update Signature (RO) Returns the microcode update signature following
- the execution of CPUID.01H. A processor may prevent writing to this MSR when
- loading guest states on VM entries or saving guest states on VM exits.
- Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
- @endcode
-**/
-#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
-
-/**
- MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:32;
- ///
- /// [Bits 63:32] Microcode update signature. This field contains the
- /// signature of the currently loaded microcode update when read following
- /// the execution of the CPUID instruction, function 1. It is required
- /// that this register field be pre-loaded with zero prior to executing
- /// the CPUID, function 1. If the field remains equal to zero, then there
- /// is no microcode update loaded. Another nonzero value will be the
- /// signature.
- ///
- UINT32 MicrocodeUpdateSignature:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_BIOS_SIGN_ID_REGISTER;
-
-
-/**
- SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =
- 1.
-
- @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
- AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
-
-/**
- MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
- /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
- /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
- /// if the bit is 0. This bit is cleared when the logical processor is
- /// reset.
- ///
- UINT32 Valid:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
- /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
- /// unless bit 2 is 1 (the value of bit 0 is irrelevant).
- ///
- UINT32 BlockSmi:1;
- UINT32 Reserved2:9;
- ///
- /// [Bits 31:12] MSEG Base (R/W).
- ///
- UINT32 MsegBase:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SMM_MONITOR_CTL_REGISTER;
-
-
-/**
- Base address of the logical processor's SMRAM image (RO, SMM only). If
- IA32_VMX_MISC[15].
-
- @param ECX MSR_IA32_SMBASE (0x0000009E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
- @endcode
-**/
-#define MSR_IA32_SMBASE 0x0000009E
-
-
-/**
- General Performance Counters (R/W).
- MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
-
- @param ECX MSR_IA32_PMCn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_PMC0);
- AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
- @endcode
- @{
-**/
-#define MSR_IA32_PMC0 0x000000C1
-#define MSR_IA32_PMC1 0x000000C2
-#define MSR_IA32_PMC2 0x000000C3
-#define MSR_IA32_PMC3 0x000000C4
-#define MSR_IA32_PMC4 0x000000C5
-#define MSR_IA32_PMC5 0x000000C6
-#define MSR_IA32_PMC6 0x000000C7
-#define MSR_IA32_PMC7 0x000000C8
-/// @}
-
-
-/**
- TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
- C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
- to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
- wrap-around of IA32_APERF.
-
- @param ECX MSR_IA32_MPERF (0x000000E7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MPERF);
- AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
- @endcode
-**/
-#define MSR_IA32_MPERF 0x000000E7
-
-
-/**
- Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
- 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
- the coordinated clock frequency, when the logical processor is in C0.
- Cleared upon overflow / wrap-around of IA32_MPERF.
-
- @param ECX MSR_IA32_APERF (0x000000E8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_APERF);
- AsmWriteMsr64 (MSR_IA32_APERF, Msr);
- @endcode
-**/
-#define MSR_IA32_APERF 0x000000E8
-
-
-/**
- MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
- Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_MTRRCAP (0x000000FE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MTRRCAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MTRRCAP_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MTRRCAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
- @endcode
-**/
-#define MSR_IA32_MTRRCAP 0x000000FE
-
-/**
- MSR information returned for MSR index #MSR_IA32_MTRRCAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
- /// processor.
- ///
- UINT32 VCNT:8;
- ///
- /// [Bit 8] Fixed range MTRRs are supported when set.
- ///
- UINT32 FIX:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 10] WC Supported when set.
- ///
- UINT32 WC:1;
- ///
- /// [Bit 11] SMRR Supported when set.
- ///
- UINT32 SMRR:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MTRRCAP_REGISTER;
-
-
-/**
- SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_SYSENTER_CS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
- AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_SYSENTER_CS 0x00000174
-
-/**
- MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] CS Selector.
- ///
- UINT32 CS:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SYSENTER_CS_REGISTER;
-
-
-/**
- SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
- AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
- @endcode
-**/
-#define MSR_IA32_SYSENTER_ESP 0x00000175
-
-
-/**
- SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
- AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
- @endcode
-**/
-#define MSR_IA32_SYSENTER_EIP 0x00000176
-
-
-/**
- Global Machine Check Capability (RO). Introduced at Display Family / Display
- Model 06_01H.
-
- @param ECX MSR_IA32_MCG_CAP (0x00000179)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_CAP_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MCG_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
- @endcode
-**/
-#define MSR_IA32_MCG_CAP 0x00000179
-
-/**
- MSR information returned for MSR index #MSR_IA32_MCG_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Count: Number of reporting banks.
- ///
- UINT32 Count:8;
- ///
- /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
- ///
- UINT32 MCG_CTL_P:1;
- ///
- /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
- /// if this bit is set.
- ///
- UINT32 MCG_EXT_P:1;
- ///
- /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
- /// Introduced at Display Family / Display Model 06_01H.
- ///
- UINT32 MCP_CMCI_P:1;
- ///
- /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
- /// if this bit is set.
- ///
- UINT32 MCG_TES_P:1;
- UINT32 Reserved1:4;
- ///
- /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
- /// registers present.
- ///
- UINT32 MCG_EXT_CNT:8;
- ///
- /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
- /// this bit is set.
- ///
- UINT32 MCG_SER_P:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
- /// firmware to be invoked when an error is detected so that it may
- /// provide additional platform specific information in an ACPI format
- /// "Generic Error Data Entry" that augments the data included in machine
- /// check bank registers. Introduced at Display Family / Display Model
- /// 06_3EH.
- ///
- UINT32 MCG_ELOG_P:1;
- ///
- /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
- /// state in IA32_MCG_STATUS and associated MSR necessary to configure
- /// Local Machine Check Exception (LMCE). Introduced at Display Family /
- /// Display Model 06_3EH.
- ///
- UINT32 MCG_LMCE_P:1;
- UINT32 Reserved3:4;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MCG_CAP_REGISTER;
-
-
-/**
- Global Machine Check Status (R/W0). Introduced at Display Family / Display
- Model 06_01H.
-
- @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MCG_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
- AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_MCG_STATUS 0x0000017A
-
-/**
- MSR information returned for MSR index #MSR_IA32_MCG_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
- /// Model 06_01H.
- ///
- UINT32 RIPV:1;
- ///
- /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
- /// Model 06_01H.
- ///
- UINT32 EIPV:1;
- ///
- /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
- /// / Display Model 06_01H.
- ///
- UINT32 MCIP:1;
- ///
- /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
- ///
- UINT32 LMCE_S:1;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MCG_STATUS_REGISTER;
-
-
-/**
- Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
-
- @param ECX MSR_IA32_MCG_CTL (0x0000017B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
- AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
- @endcode
-**/
-#define MSR_IA32_MCG_CTL 0x0000017B
-
-
-/**
- Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
-
- @param ECX MSR_IA32_PERFEVTSELn
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERFEVTSEL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_IA32_PERFEVTSEL0 0x00000186
-#define MSR_IA32_PERFEVTSEL1 0x00000187
-#define MSR_IA32_PERFEVTSEL2 0x00000188
-#define MSR_IA32_PERFEVTSEL3 0x00000189
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
- #MSR_IA32_PERFEVTSEL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Event Select: Selects a performance event logic unit.
- ///
- UINT32 EventSelect:8;
- ///
- /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
- /// detect on the selected event logic.
- ///
- UINT32 UMASK:8;
- ///
- /// [Bit 16] USR: Counts while in privilege level is not ring 0.
- ///
- UINT32 USR:1;
- ///
- /// [Bit 17] OS: Counts while in privilege level is ring 0.
- ///
- UINT32 OS:1;
- ///
- /// [Bit 18] Edge: Enables edge detection if set.
- ///
- UINT32 E:1;
- ///
- /// [Bit 19] PC: enables pin control.
- ///
- UINT32 PC:1;
- ///
- /// [Bit 20] INT: enables interrupt on counter overflow.
- ///
- UINT32 INT:1;
- ///
- /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR.
- ///
- UINT32 ANY:1;
- ///
- /// [Bit 22] EN: enables the corresponding performance counter to commence
- /// counting when this bit is set.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 23] INV: invert the CMASK.
- ///
- UINT32 INV:1;
- ///
- /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
- /// performance counter increments each cycle if the event count is
- /// greater than or equal to the CMASK.
- ///
- UINT32 CMASK:8;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERFEVTSEL_REGISTER;
-
-
-/**
- Current performance state(P-State) operating point (RO). Introduced at
- Display Family / Display Model 0F_03H.
-
- @param ECX MSR_IA32_PERF_STATUS (0x00000198)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
- @endcode
-**/
-#define MSR_IA32_PERF_STATUS 0x00000198
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Current performance State Value.
- ///
- UINT32 State:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_STATUS_REGISTER;
-
-
-/**
- (R/W). Introduced at Display Family / Display Model 0F_03H.
-
- @param ECX MSR_IA32_PERF_CTL (0x00000199)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
- AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PERF_CTL 0x00000199
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Target performance State Value.
- ///
- UINT32 TargetState:16;
- UINT32 Reserved1:16;
- ///
- /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
- /// (Mobile only).
- ///
- UINT32 IDA:1;
- UINT32 Reserved2:31;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_CTL_REGISTER;
-
-
-/**
- Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
- Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.
-
- @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
- AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_CLOCK_MODULATION 0x0000019A
-
-/**
- MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
- /// CPUID.06H:EAX[5] = 1.
- ///
- UINT32 ExtendedOnDemandClockModulationDutyCycle:1;
- ///
- /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
- /// values for target duty cycle modulation.
- ///
- UINT32 OnDemandClockModulationDutyCycle:3;
- ///
- /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
- ///
- UINT32 OnDemandClockModulationEnable:1;
- UINT32 Reserved1:27;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_CLOCK_MODULATION_REGISTER;
-
-
-/**
- Thermal Interrupt Control (R/W) Enables and disables the generation of an
- interrupt on temperature transitions detected with the processor's thermal
- sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
- Introduced at Display Family / Display Model 0F_0H.
-
- @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
- AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_THERM_INTERRUPT 0x0000019B
-
-/**
- MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] High-Temperature Interrupt Enable.
- ///
- UINT32 HighTempEnable:1;
- ///
- /// [Bit 1] Low-Temperature Interrupt Enable.
- ///
- UINT32 LowTempEnable:1;
- ///
- /// [Bit 2] PROCHOT# Interrupt Enable.
- ///
- UINT32 PROCHOT_Enable:1;
- ///
- /// [Bit 3] FORCEPR# Interrupt Enable.
- ///
- UINT32 FORCEPR_Enable:1;
- ///
- /// [Bit 4] Critical Temperature Interrupt Enable.
- ///
- UINT32 CriticalTempEnable:1;
- UINT32 Reserved1:3;
- ///
- /// [Bits 14:8] Threshold #1 Value.
- ///
- UINT32 Threshold1:7;
- ///
- /// [Bit 15] Threshold #1 Interrupt Enable.
- ///
- UINT32 Threshold1Enable:1;
- ///
- /// [Bits 22:16] Threshold #2 Value.
- ///
- UINT32 Threshold2:7;
- ///
- /// [Bit 23] Threshold #2 Interrupt Enable.
- ///
- UINT32 Threshold2Enable:1;
- ///
- /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
- ///
- UINT32 PowerLimitNotificationEnable:1;
- UINT32 Reserved2:7;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_THERM_INTERRUPT_REGISTER;
-
-
-/**
- Thermal Status Information (RO) Contains status information about the
- processor's thermal sensor and automatic thermal monitoring facilities. See
- Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display
- Model 0F_0H.
-
- @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_THERM_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_THERM_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_THERM_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
- @endcode
-**/
-#define MSR_IA32_THERM_STATUS 0x0000019C
-
-/**
- MSR information returned for MSR index #MSR_IA32_THERM_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thermal Status (RO):.
- ///
- UINT32 ThermalStatus:1;
- ///
- /// [Bit 1] Thermal Status Log (R/W):.
- ///
- UINT32 ThermalStatusLog:1;
- ///
- /// [Bit 2] PROCHOT # or FORCEPR# event (RO).
- ///
- UINT32 PROCHOT_FORCEPR_Event:1;
- ///
- /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).
- ///
- UINT32 PROCHOT_FORCEPR_Log:1;
- ///
- /// [Bit 4] Critical Temperature Status (RO).
- ///
- UINT32 CriticalTempStatus:1;
- ///
- /// [Bit 5] Critical Temperature Status log (R/WC0).
- ///
- UINT32 CriticalTempStatusLog:1;
- ///
- /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
- ///
- UINT32 ThermalThreshold1Status:1;
- ///
- /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
- ///
- UINT32 ThermalThreshold1Log:1;
- ///
- /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
- ///
- UINT32 ThermalThreshold2Status:1;
- ///
- /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
- ///
- UINT32 ThermalThreshold2Log:1;
- ///
- /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
- ///
- UINT32 PowerLimitStatus:1;
- ///
- /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
- ///
- UINT32 PowerLimitLog:1;
- ///
- /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
- ///
- UINT32 CurrentLimitStatus:1;
- ///
- /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
- ///
- UINT32 CurrentLimitLog:1;
- ///
- /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
- ///
- UINT32 CrossDomainLimitStatus:1;
- ///
- /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
- ///
- UINT32 CrossDomainLimitLog:1;
- ///
- /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
- ///
- UINT32 DigitalReadout:7;
- UINT32 Reserved1:4;
- ///
- /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
- /// 1.
- ///
- UINT32 ResolutionInDegreesCelsius:4;
- ///
- /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
- ///
- UINT32 ReadingValid:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_THERM_STATUS_REGISTER;
-
-
-/**
- Enable Misc. Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
- /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
- /// are disabled. Introduced at Display Family / Display Model 0F_0H.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
- /// this bit enables the thermal control circuit (TCC) portion of the
- /// Intel Thermal Monitor feature. This allows the processor to
- /// automatically reduce power consumption in response to TCC activation.
- /// 0 = Disabled. Note: In some products clearing this bit might be
- /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
- /// thermal throttling will still be activated. Introduced at Display
- /// Family / Display Model 0F_0H.
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
- /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
- /// Display Family / Display Model 0F_0H.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
- ///
- /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
- /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
- /// Display Family / Display Model 0F_0H.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =
- /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
- /// Family / Display Model 06_0FH.
- ///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
- ///
- /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
- /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
- /// Technology enabled. If CPUID.01H: ECX[7] =1.
- ///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
- /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
- /// indicates that MONITOR/MWAIT are not supported. Software attempts to
- /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
- /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
- /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
- /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
- /// in the default state. Writing this bit when the SSE3 feature flag is
- /// set to 0 may generate a #GP exception. Introduced at Display Family /
- /// Display Model 0F_03H.
- ///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
- ///
- /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
- /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup
- /// question that allows users to specify when the installed OS does not
- /// support CPUID functions greater than 3. Before setting this bit, BIOS
- /// must execute the CPUID.0H and examine the maximum value returned in
- /// EAX[7:0]. If the maximum value is greater than 3, the bit is
- /// supported. Otherwise, the bit is not supported. Writing to this bit
- /// when the maximum value is greater than 3 may generate a #GP exception.
- /// Setting this bit may cause unexpected behavior in software that
- /// depends on the availability of CPUID leaves greater than 3. Introduced
- /// at Display Family / Display Model 0F_03H.
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
- /// disabled. xTPR messages are optional messages that allow the processor
- /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
- ///
- /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
- /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
- /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
- /// Execute Disable Bit feature (if available) allows the OS to enable PAE
- /// paging and take advantage of data only pages. BIOS must not alter the
- /// contents of this bit location, if XD bit is not supported. Writing
- /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
- /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
- ///
- UINT32 XD:1;
- UINT32 Reserved9:29;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
-
- @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
- AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
-
-/**
- MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
- /// performance. 15 indicates preference to maximize energy saving.
- ///
- UINT32 PowerPolicyPreference:4;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;
-
-
-/**
- Package Thermal Status Information (RO) Contains status information about
- the package's thermal sensor. See Section 14.8, "Package Level Thermal
- Management.". If CPUID.06H: EAX[6] = 1.
-
- @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
- @endcode
-**/
-#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
-
-/**
- MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Pkg Thermal Status (RO):.
- ///
- UINT32 ThermalStatus:1;
- ///
- /// [Bit 1] Pkg Thermal Status Log (R/W):.
- ///
- UINT32 ThermalStatusLog:1;
- ///
- /// [Bit 2] Pkg PROCHOT # event (RO).
- ///
- UINT32 PROCHOT_Event:1;
- ///
- /// [Bit 3] Pkg PROCHOT # log (R/WC0).
- ///
- UINT32 PROCHOT_Log:1;
- ///
- /// [Bit 4] Pkg Critical Temperature Status (RO).
- ///
- UINT32 CriticalTempStatus:1;
- ///
- /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
- ///
- UINT32 CriticalTempStatusLog:1;
- ///
- /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
- ///
- UINT32 ThermalThreshold1Status:1;
- ///
- /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
- ///
- UINT32 ThermalThreshold1Log:1;
- ///
- /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
- ///
- UINT32 ThermalThreshold2Status:1;
- ///
- /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
- ///
- UINT32 ThermalThreshold2Log:1;
- ///
- /// [Bit 10] Pkg Power Limitation Status (RO).
- ///
- UINT32 PowerLimitStatus:1;
- ///
- /// [Bit 11] Pkg Power Limitation log (R/WC0).
- ///
- UINT32 PowerLimitLog:1;
- UINT32 Reserved1:4;
- ///
- /// [Bits 22:16] Pkg Digital Readout (RO).
- ///
- UINT32 DigitalReadout:7;
- UINT32 Reserved2:9;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;
-
-
-/**
- Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
- an interrupt on temperature transitions detected with the package's thermal
- sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
- EAX[6] = 1.
-
- @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
- AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
-
-/**
- MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Pkg High-Temperature Interrupt Enable.
- ///
- UINT32 HighTempEnable:1;
- ///
- /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
- ///
- UINT32 LowTempEnable:1;
- ///
- /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
- ///
- UINT32 PROCHOT_Enable:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 4] Pkg Overheat Interrupt Enable.
- ///
- UINT32 OverheatEnable:1;
- UINT32 Reserved2:3;
- ///
- /// [Bits 14:8] Pkg Threshold #1 Value.
- ///
- UINT32 Threshold1:7;
- ///
- /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
- ///
- UINT32 Threshold1Enable:1;
- ///
- /// [Bits 22:16] Pkg Threshold #2 Value.
- ///
- UINT32 Threshold2:7;
- ///
- /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
- ///
- UINT32 Threshold2Enable:1;
- ///
- /// [Bit 24] Pkg Power Limit Notification Enable.
- ///
- UINT32 PowerLimitNotificationEnable:1;
- UINT32 Reserved3:7;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;
-
-
-/**
- Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
- Model 06_0EH.
-
- @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_DEBUGCTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_DEBUGCTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_DEBUGCTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
- AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_DEBUGCTL 0x000001D9
-
-/**
- MSR information returned for MSR index #MSR_IA32_DEBUGCTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
- /// running trace of the most recent branches taken by the processor in
- /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
- ///
- UINT32 LBR:1;
- ///
- /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
- /// EFLAGS.TF as single-step on branches instead of single-step on
- /// instructions. Introduced at Display Family / Display Model 06_01H.
- ///
- UINT32 BTF:1;
- UINT32 Reserved1:4;
- ///
- /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
- /// sent. Introduced at Display Family / Display Model 06_0EH.
- ///
- UINT32 TR:1;
- ///
- /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
- /// be logged in a BTS buffer. Introduced at Display Family / Display
- /// Model 06_0EH.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
- /// fashion. When this bit is set, an interrupt is generated by the BTS
- /// facility when the BTS buffer is full. Introduced at Display Family /
- /// Display Model 06_0EH.
- ///
- UINT32 BTINT:1;
- ///
- /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
- /// Introduced at Display Family / Display Model 06_0FH.
- ///
- UINT32 BTS_OFF_OS:1;
- ///
- /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
- /// Introduced at Display Family / Display Model 06_0FH.
- ///
- UINT32 BTS_OFF_USR:1;
- ///
- /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
- /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 FREEZE_LBRS_ON_PMI:1;
- ///
- /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
- /// global counter control MSR are frozen (address 38FH) on a PMI request.
- /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 FREEZE_PERFMON_ON_PMI:1;
- ///
- /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
- /// receive and generate PMI on behalf of the uncore. Introduced at
- /// Display Family / Display Model 06_1AH.
- ///
- UINT32 ENABLE_UNCORE_PMI:1;
- ///
- /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
- /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
- ///
- UINT32 FREEZE_WHILE_SMM:1;
- ///
- /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
- /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
- ///
- UINT32 RTM_DEBUG:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_DEBUGCTL_REGISTER;
-
-
-/**
- SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
- If IA32_MTRRCAP.SMRR[11] = 1.
-
- @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
- AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
-
-/**
- MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Type. Specifies memory type of the range.
- ///
- UINT32 Type:8;
- UINT32 Reserved1:4;
- ///
- /// [Bits 31:12] PhysBase. SMRR physical Base Address.
- ///
- UINT32 PhysBase:20;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SMRR_PHYSBASE_REGISTER;
-
-
-/**
- SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
- IA32_MTRRCAP[SMRR] = 1.
-
- @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
- AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
-
-/**
- MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:11;
- ///
- /// [Bit 11] Valid Enable range mask.
- ///
- UINT32 Valid:1;
- ///
- /// [Bits 31:12] PhysMask SMRR address range mask.
- ///
- UINT32 PhysMask:20;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SMRR_PHYSMASK_REGISTER;
-
-
-/**
- DCA Capability (R). If CPUID.01H: ECX[18] = 1.
-
- @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
- @endcode
-**/
-#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
-
-
-/**
- If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
-
- @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
- AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
- @endcode
-**/
-#define MSR_IA32_CPU_DCA_CAP 0x000001F9
-
-
-/**
- DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
-
- @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_DCA_0_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
- AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_DCA_0_CAP 0x000001FA
-
-/**
- MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
- /// defeatures are set.
- ///
- UINT32 DCA_ACTIVE:1;
- ///
- /// [Bits 2:1] TRANSACTION.
- ///
- UINT32 TRANSACTION:2;
- ///
- /// [Bits 6:3] DCA_TYPE.
- ///
- UINT32 DCA_TYPE:4;
- ///
- /// [Bits 10:7] DCA_QUEUE_SIZE.
- ///
- UINT32 DCA_QUEUE_SIZE:4;
- UINT32 Reserved1:2;
- ///
- /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
- /// side-effect.
- ///
- UINT32 DCA_DELAY:4;
- UINT32 Reserved2:7;
- ///
- /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
- ///
- UINT32 SW_BLOCK:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
- ///
- UINT32 HW_BLOCK:1;
- UINT32 Reserved4:5;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_DCA_0_CAP_REGISTER;
-
-
-/**
- MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
- If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
-
- @param ECX MSR_IA32_MTRR_PHYSBASEn
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
- AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
-#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
-#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
-#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
-#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
-#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
-#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
-#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
-#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
-#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
- #MSR_IA32_MTRR_PHYSBASE9
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Type. Specifies memory type of the range.
- ///
- UINT32 Type:8;
- UINT32 Reserved1:4;
- ///
- /// [Bits 31:12] PhysBase. MTRR physical Base Address.
- ///
- UINT32 PhysBase:20;
- ///
- /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
- /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
- /// maximum physical address range supported by the processor. It is
- /// reported by CPUID leaf function 80000008H. If CPUID does not support
- /// leaf 80000008H, the processor supports 36-bit physical address size,
- /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
- ///
- UINT32 PhysBaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MTRR_PHYSBASE_REGISTER;
-
-
-/**
- MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
- If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
-
- @param ECX MSR_IA32_MTRR_PHYSMASKn
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
- AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
-#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
-#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
-#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
-#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
-#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
-#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
-#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
-#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
-#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
- #MSR_IA32_MTRR_PHYSMASK9
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:11;
- ///
- /// [Bit 11] Valid Enable range mask.
- ///
- UINT32 V:8;
- ///
- /// [Bits 31:12] PhysMask. MTRR address range mask.
- ///
- UINT32 PhysMask:20;
- ///
- /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
- /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
- /// maximum physical address range supported by the processor. It is
- /// reported by CPUID leaf function 80000008H. If CPUID does not support
- /// leaf 80000008H, the processor supports 36-bit physical address size,
- /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
- ///
- UINT32 PhysMaskHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MTRR_PHYSMASK_REGISTER;
-
-
-/**
- MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
-
-
-/**
- MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
-
-
-/**
- MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
-
-
-/**
- See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
-
-
-/**
- MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
-
-
-/**
- MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
-
-
-/**
- MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
-
-
-/**
- MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
-
-
-/**
- MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
-
-
-/**
- MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
-
-
-/**
- MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
- @endcode
-**/
-#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
-
-
-/**
- IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
-
- @param ECX MSR_IA32_PAT (0x00000277)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PAT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PAT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PAT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
- AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PAT 0x00000277
-
-/**
- MSR information returned for MSR index #MSR_IA32_PAT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] PA0.
- ///
- UINT32 PA0:3;
- UINT32 Reserved1:5;
- ///
- /// [Bits 10:8] PA1.
- ///
- UINT32 PA1:3;
- UINT32 Reserved2:5;
- ///
- /// [Bits 18:16] PA2.
- ///
- UINT32 PA2:3;
- UINT32 Reserved3:5;
- ///
- /// [Bits 26:24] PA3.
- ///
- UINT32 PA3:3;
- UINT32 Reserved4:5;
- ///
- /// [Bits 34:32] PA4.
- ///
- UINT32 PA4:3;
- UINT32 Reserved5:5;
- ///
- /// [Bits 42:40] PA5.
- ///
- UINT32 PA5:3;
- UINT32 Reserved6:5;
- ///
- /// [Bits 50:48] PA6.
- ///
- UINT32 PA6:3;
- UINT32 Reserved7:5;
- ///
- /// [Bits 58:56] PA7.
- ///
- UINT32 PA7:3;
- UINT32 Reserved8:5;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PAT_REGISTER;
-
-
-/**
- Provides the programming interface to use corrected MC error signaling
- capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
-
- @param ECX MSR_IA32_MCn_CTL2
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MC_CTL2_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MC_CTL2_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MC_CTL2_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
- AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_IA32_MC0_CTL2 0x00000280
-#define MSR_IA32_MC1_CTL2 0x00000281
-#define MSR_IA32_MC2_CTL2 0x00000282
-#define MSR_IA32_MC3_CTL2 0x00000283
-#define MSR_IA32_MC4_CTL2 0x00000284
-#define MSR_IA32_MC5_CTL2 0x00000285
-#define MSR_IA32_MC6_CTL2 0x00000286
-#define MSR_IA32_MC7_CTL2 0x00000287
-#define MSR_IA32_MC8_CTL2 0x00000288
-#define MSR_IA32_MC9_CTL2 0x00000289
-#define MSR_IA32_MC10_CTL2 0x0000028A
-#define MSR_IA32_MC11_CTL2 0x0000028B
-#define MSR_IA32_MC12_CTL2 0x0000028C
-#define MSR_IA32_MC13_CTL2 0x0000028D
-#define MSR_IA32_MC14_CTL2 0x0000028E
-#define MSR_IA32_MC15_CTL2 0x0000028F
-#define MSR_IA32_MC16_CTL2 0x00000290
-#define MSR_IA32_MC17_CTL2 0x00000291
-#define MSR_IA32_MC18_CTL2 0x00000292
-#define MSR_IA32_MC19_CTL2 0x00000293
-#define MSR_IA32_MC20_CTL2 0x00000294
-#define MSR_IA32_MC21_CTL2 0x00000295
-#define MSR_IA32_MC22_CTL2 0x00000296
-#define MSR_IA32_MC23_CTL2 0x00000297
-#define MSR_IA32_MC24_CTL2 0x00000298
-#define MSR_IA32_MC25_CTL2 0x00000299
-#define MSR_IA32_MC26_CTL2 0x0000029A
-#define MSR_IA32_MC27_CTL2 0x0000029B
-#define MSR_IA32_MC28_CTL2 0x0000029C
-#define MSR_IA32_MC29_CTL2 0x0000029D
-#define MSR_IA32_MC30_CTL2 0x0000029E
-#define MSR_IA32_MC31_CTL2 0x0000029F
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
- to #MSR_IA32_MC31_CTL2
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] Corrected error count threshold.
- ///
- UINT32 CorrectedErrorCountThreshold:15;
- UINT32 Reserved1:15;
- ///
- /// [Bit 30] CMCI_EN.
- ///
- UINT32 CMCI_EN:1;
- UINT32 Reserved2:1;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MC_CTL2_REGISTER;
-
-
-/**
- MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
- AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
-
-/**
- MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Default Memory Type.
- ///
- UINT32 Type:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] Fixed Range MTRR Enable.
- ///
- UINT32 FE:1;
- ///
- /// [Bit 11] MTRR Enable.
- ///
- UINT32 E:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MTRR_DEF_TYPE_REGISTER;
-
-
-/**
- Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
- CPUID.0AH: EDX[4:0] > 0.
-
- @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
- @endcode
-**/
-#define MSR_IA32_FIXED_CTR0 0x00000309
-
-
-/**
- Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.
- If CPUID.0AH: EDX[4:0] > 1.
-
- @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
- @endcode
-**/
-#define MSR_IA32_FIXED_CTR1 0x0000030A
-
-
-/**
- Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.
- If CPUID.0AH: EDX[4:0] > 2.
-
- @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
- @endcode
-**/
-#define MSR_IA32_FIXED_CTR2 0x0000030B
-
-
-/**
- RO. If CPUID.01H: ECX[15] = 1.
-
- @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
- AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PERF_CAPABILITIES 0x00000345
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 5:0] LBR format.
- ///
- UINT32 LBR_FMT:6;
- ///
- /// [Bit 6] PEBS Trap.
- ///
- UINT32 PEBS_TRAP:1;
- ///
- /// [Bit 7] PEBSSaveArchRegs.
- ///
- UINT32 PEBS_ARCH_REG:1;
- ///
- /// [Bits 11:8] PEBS Record Format.
- ///
- UINT32 PEBS_REC_FMT:4;
- ///
- /// [Bit 12] 1: Freeze while SMM is supported.
- ///
- UINT32 SMM_FREEZE:1;
- ///
- /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
- ///
- UINT32 FW_WRITE:1;
- UINT32 Reserved1:18;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_CAPABILITIES_REGISTER;
-
-
-/**
- Fixed-Function Performance Counter Control (R/W) Counter increments while
- the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
- the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
- > 1.
-
- @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
-
-/**
- MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
- ///
- UINT32 EN0_OS:1;
- ///
- /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
- ///
- UINT32 EN0_Usr:1;
- ///
- /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
- ///
- UINT32 AnyThread0:1;
- ///
- /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
- ///
- UINT32 EN0_PMI:1;
- ///
- /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
- ///
- UINT32 EN1_OS:1;
- ///
- /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
- ///
- UINT32 EN1_Usr:1;
- ///
- /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
- ///
- UINT32 AnyThread1:1;
- ///
- /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
- ///
- UINT32 EN1_PMI:1;
- ///
- /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
- ///
- UINT32 EN2_OS:1;
- ///
- /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
- ///
- UINT32 EN2_Usr:1;
- ///
- /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
- ///
- UINT32 AnyThread2:1;
- ///
- /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
- ///
- UINT32 EN2_PMI:1;
- UINT32 Reserved1:20;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_FIXED_CTR_CTRL_REGISTER;
-
-
-/**
- Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
-
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
- @endcode
-**/
-#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
- /// EAX[15:8] > 0.
- ///
- UINT32 Ovf_PMC0:1;
- ///
- /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
- /// EAX[15:8] > 1.
- ///
- UINT32 Ovf_PMC1:1;
- ///
- /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
- /// EAX[15:8] > 2.
- ///
- UINT32 Ovf_PMC2:1;
- ///
- /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
- /// EAX[15:8] > 3.
- ///
- UINT32 Ovf_PMC3:1;
- UINT32 Reserved1:28;
- ///
- /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
- /// CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 Ovf_FixedCtr0:1;
- ///
- /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
- /// CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 Ovf_FixedCtr1:1;
- ///
- /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
- /// CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:20;
- ///
- /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
- /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
- /// && IA32_RTIT_CTL.ToPA = 1.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 58] LBR_Frz: LBRs are frozen due to -
- /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
- /// CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
- /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
- /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
- /// include contributions from the direct or indirect operation intel SGX
- /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
- /// EAX[7:0] > 2.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
- /// EAX[7:0] > 0.
- ///
- UINT32 OvfBuf:1;
- ///
- /// [Bit 63] CondChgd: status bits of this register has changed. If
- /// CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;
-
-
-/**
- Global Performance Counter Control (R/W) Counter increments while the result
- of ANDing respective enable bit in this MSR with the corresponding OS or USR
- bits in the general-purpose or fixed counter control MSR is true. If
- CPUID.0AH: EAX[7:0] > 0.
-
- @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
-///
- struct {
- ///
- /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
- /// Enable bitmask. Only the first n-1 bits are valid.
- /// Bits n..31 are reserved.
- ///
- UINT32 EN_PMCn:32;
- ///
- /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
- /// Enable bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 EN_FIXED_CTRn:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;
-
-
-/**
- Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
- 0 && CPUID.0AH: EAX[7:0] <= 3.
-
- @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
- /// Clear bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 Ovf_PMCn:32;
- ///
- /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
- /// If CPUID.0AH: EDX[4:0] > n.
- /// Clear bitmask. Only the first n-1 bits are valid.
- /// Bits 22:n are reserved.
- ///
- UINT32 Ovf_FIXED_CTRn:23;
- ///
- /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
- /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:5;
- ///
- /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
- /// Display Model 06_2EH.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 OvfBuf:1;
- ///
- /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;
-
-
-/**
- Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
- EAX[7:0] > 3.
-
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
- /// Clear bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 Ovf_PMCn:32;
- ///
- /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
- /// If CPUID.0AH: EDX[4:0] > n.
- /// Clear bitmask. Only the first n-1 bits are valid.
- /// Bits 22:n are reserved.
- ///
- UINT32 Ovf_FIXED_CTRn:23;
- ///
- /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
- /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
- /// Display Model 06_2EH.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 OvfBuf:1;
- ///
- /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
-
-
-/**
- Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
- EAX[7:0] > 3.
-
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
- /// Set bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 Ovf_PMCn:32;
- ///
- /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
- /// If CPUID.0AH: EAX[7:0] > n.
- /// Set bitmask. Only the first n-1 bits are valid.
- /// Bits 22:n are reserved.
- ///
- UINT32 Ovf_FIXED_CTRn:23;
- ///
- /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 OvfBuf:1;
- UINT32 Reserved3:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
-
-
-/**
- Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
- 3.
-
- @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
- @endcode
-**/
-#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
- /// Status bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 IA32_PERFEVTSELn:32;
- ///
- /// [Bits 62:32] IA32_FIXED_CTRn in use.
- /// If CPUID.0AH: EAX[7:0] > n.
- /// Status bitmask. Only the first n-1 bits are valid.
- /// Bits 30:n are reserved.
- ///
- UINT32 IA32_FIXED_CTRn:31;
- ///
- /// [Bit 63] PMI in use.
- ///
- UINT32 PMI:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;
-
-
-/**
- PEBS Control (R/W).
-
- @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
- /// Display Model 06_0FH.
- ///
- UINT32 Enable:1;
- ///
- /// [Bits 3:1] Reserved or Model specific.
- ///
- UINT32 Reserved1:3;
- UINT32 Reserved2:28;
- ///
- /// [Bits 35:32] Reserved or Model specific.
- ///
- UINT32 Reserved3:4;
- UINT32 Reserved4:28;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PEBS_ENABLE_REGISTER;
-
-
-/**
- MCn_CTL. If IA32_MCG_CAP.CNT > n.
-
- @param ECX MSR_IA32_MCn_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
- AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
- @endcode
- @{
-**/
-#define MSR_IA32_MC0_CTL 0x00000400
-#define MSR_IA32_MC1_CTL 0x00000404
-#define MSR_IA32_MC2_CTL 0x00000408
-#define MSR_IA32_MC3_CTL 0x0000040C
-#define MSR_IA32_MC4_CTL 0x00000410
-#define MSR_IA32_MC5_CTL 0x00000414
-#define MSR_IA32_MC6_CTL 0x00000418
-#define MSR_IA32_MC7_CTL 0x0000041C
-#define MSR_IA32_MC8_CTL 0x00000420
-#define MSR_IA32_MC9_CTL 0x00000424
-#define MSR_IA32_MC10_CTL 0x00000428
-#define MSR_IA32_MC11_CTL 0x0000042C
-#define MSR_IA32_MC12_CTL 0x00000430
-#define MSR_IA32_MC13_CTL 0x00000434
-#define MSR_IA32_MC14_CTL 0x00000438
-#define MSR_IA32_MC15_CTL 0x0000043C
-#define MSR_IA32_MC16_CTL 0x00000440
-#define MSR_IA32_MC17_CTL 0x00000444
-#define MSR_IA32_MC18_CTL 0x00000448
-#define MSR_IA32_MC19_CTL 0x0000044C
-#define MSR_IA32_MC20_CTL 0x00000450
-#define MSR_IA32_MC21_CTL 0x00000454
-#define MSR_IA32_MC22_CTL 0x00000458
-#define MSR_IA32_MC23_CTL 0x0000045C
-#define MSR_IA32_MC24_CTL 0x00000460
-#define MSR_IA32_MC25_CTL 0x00000464
-#define MSR_IA32_MC26_CTL 0x00000468
-#define MSR_IA32_MC27_CTL 0x0000046C
-#define MSR_IA32_MC28_CTL 0x00000470
-/// @}
-
-
-/**
- MCn_STATUS. If IA32_MCG_CAP.CNT > n.
-
- @param ECX MSR_IA32_MCn_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
- AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
- @endcode
- @{
-**/
-#define MSR_IA32_MC0_STATUS 0x00000401
-#define MSR_IA32_MC1_STATUS 0x00000405
-#define MSR_IA32_MC2_STATUS 0x00000409
-#define MSR_IA32_MC3_STATUS 0x0000040D
-#define MSR_IA32_MC4_STATUS 0x00000411
-#define MSR_IA32_MC5_STATUS 0x00000415
-#define MSR_IA32_MC6_STATUS 0x00000419
-#define MSR_IA32_MC7_STATUS 0x0000041D
-#define MSR_IA32_MC8_STATUS 0x00000421
-#define MSR_IA32_MC9_STATUS 0x00000425
-#define MSR_IA32_MC10_STATUS 0x00000429
-#define MSR_IA32_MC11_STATUS 0x0000042D
-#define MSR_IA32_MC12_STATUS 0x00000431
-#define MSR_IA32_MC13_STATUS 0x00000435
-#define MSR_IA32_MC14_STATUS 0x00000439
-#define MSR_IA32_MC15_STATUS 0x0000043D
-#define MSR_IA32_MC16_STATUS 0x00000441
-#define MSR_IA32_MC17_STATUS 0x00000445
-#define MSR_IA32_MC18_STATUS 0x00000449
-#define MSR_IA32_MC19_STATUS 0x0000044D
-#define MSR_IA32_MC20_STATUS 0x00000451
-#define MSR_IA32_MC21_STATUS 0x00000455
-#define MSR_IA32_MC22_STATUS 0x00000459
-#define MSR_IA32_MC23_STATUS 0x0000045D
-#define MSR_IA32_MC24_STATUS 0x00000461
-#define MSR_IA32_MC25_STATUS 0x00000465
-#define MSR_IA32_MC26_STATUS 0x00000469
-#define MSR_IA32_MC27_STATUS 0x0000046D
-#define MSR_IA32_MC28_STATUS 0x00000471
-/// @}
-
-
-/**
- MCn_ADDR. If IA32_MCG_CAP.CNT > n.
-
- @param ECX MSR_IA32_MCn_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
- AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
- @endcode
- @{
-**/
-#define MSR_IA32_MC0_ADDR 0x00000402
-#define MSR_IA32_MC1_ADDR 0x00000406
-#define MSR_IA32_MC2_ADDR 0x0000040A
-#define MSR_IA32_MC3_ADDR 0x0000040E
-#define MSR_IA32_MC4_ADDR 0x00000412
-#define MSR_IA32_MC5_ADDR 0x00000416
-#define MSR_IA32_MC6_ADDR 0x0000041A
-#define MSR_IA32_MC7_ADDR 0x0000041E
-#define MSR_IA32_MC8_ADDR 0x00000422
-#define MSR_IA32_MC9_ADDR 0x00000426
-#define MSR_IA32_MC10_ADDR 0x0000042A
-#define MSR_IA32_MC11_ADDR 0x0000042E
-#define MSR_IA32_MC12_ADDR 0x00000432
-#define MSR_IA32_MC13_ADDR 0x00000436
-#define MSR_IA32_MC14_ADDR 0x0000043A
-#define MSR_IA32_MC15_ADDR 0x0000043E
-#define MSR_IA32_MC16_ADDR 0x00000442
-#define MSR_IA32_MC17_ADDR 0x00000446
-#define MSR_IA32_MC18_ADDR 0x0000044A
-#define MSR_IA32_MC19_ADDR 0x0000044E
-#define MSR_IA32_MC20_ADDR 0x00000452
-#define MSR_IA32_MC21_ADDR 0x00000456
-#define MSR_IA32_MC22_ADDR 0x0000045A
-#define MSR_IA32_MC23_ADDR 0x0000045E
-#define MSR_IA32_MC24_ADDR 0x00000462
-#define MSR_IA32_MC25_ADDR 0x00000466
-#define MSR_IA32_MC26_ADDR 0x0000046A
-#define MSR_IA32_MC27_ADDR 0x0000046E
-#define MSR_IA32_MC28_ADDR 0x00000472
-/// @}
-
-
-/**
- MCn_MISC. If IA32_MCG_CAP.CNT > n.
-
- @param ECX MSR_IA32_MCn_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
- AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
- @endcode
- @{
-**/
-#define MSR_IA32_MC0_MISC 0x00000403
-#define MSR_IA32_MC1_MISC 0x00000407
-#define MSR_IA32_MC2_MISC 0x0000040B
-#define MSR_IA32_MC3_MISC 0x0000040F
-#define MSR_IA32_MC4_MISC 0x00000413
-#define MSR_IA32_MC5_MISC 0x00000417
-#define MSR_IA32_MC6_MISC 0x0000041B
-#define MSR_IA32_MC7_MISC 0x0000041F
-#define MSR_IA32_MC8_MISC 0x00000423
-#define MSR_IA32_MC9_MISC 0x00000427
-#define MSR_IA32_MC10_MISC 0x0000042B
-#define MSR_IA32_MC11_MISC 0x0000042F
-#define MSR_IA32_MC12_MISC 0x00000433
-#define MSR_IA32_MC13_MISC 0x00000437
-#define MSR_IA32_MC14_MISC 0x0000043B
-#define MSR_IA32_MC15_MISC 0x0000043F
-#define MSR_IA32_MC16_MISC 0x00000443
-#define MSR_IA32_MC17_MISC 0x00000447
-#define MSR_IA32_MC18_MISC 0x0000044B
-#define MSR_IA32_MC19_MISC 0x0000044F
-#define MSR_IA32_MC20_MISC 0x00000453
-#define MSR_IA32_MC21_MISC 0x00000457
-#define MSR_IA32_MC22_MISC 0x0000045B
-#define MSR_IA32_MC23_MISC 0x0000045F
-#define MSR_IA32_MC24_MISC 0x00000463
-#define MSR_IA32_MC25_MISC 0x00000467
-#define MSR_IA32_MC26_MISC 0x0000046B
-#define MSR_IA32_MC27_MISC 0x0000046F
-#define MSR_IA32_MC28_MISC 0x00000473
-/// @}
-
-
-/**
- Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
- VMX Information.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_BASIC (0x00000480)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
- @endcode
-**/
-#define MSR_IA32_VMX_BASIC 0x00000480
-
-
-/**
- Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
- Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
- @endcode
-**/
-#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
-
-
-/**
- Capability Reporting Register of Primary Processor-based VM-execution
- Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
- Controls.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
- @endcode
-**/
-#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
-
-
-/**
- Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
- "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
- @endcode
-**/
-#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
-
-
-/**
- Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
- "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
- @endcode
-**/
-#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
-
-
-/**
- Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
- "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_MISC (0x00000485)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);
- @endcode
-**/
-#define MSR_IA32_VMX_MISC 0x00000485
-
-
-/**
- Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
- "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
- @endcode
-**/
-#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
-
-
-/**
- Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
- "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
- @endcode
-**/
-#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
-
-
-/**
- Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
- "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
- @endcode
-**/
-#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
-
-
-/**
- Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
- "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
- @endcode
-**/
-#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
-
-
-/**
- Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
- A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
- @endcode
-**/
-#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
-
-
-/**
- Capability Reporting Register of Secondary Processor-based VM-execution
- Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
- Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
-
- @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
- @endcode
-**/
-#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
-
-
-/**
- Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
- "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
- TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
-
- @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
- @endcode
-**/
-#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
-
-
-/**
- Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
- See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
- CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
- @endcode
-**/
-#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
-
-
-/**
- Capability Reporting Register of Primary Processor-based VM-execution Flex
- Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
- Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
- @endcode
-**/
-#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
-
-
-/**
- Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
- A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
- @endcode
-**/
-#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
-
-
-/**
- Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
- A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
- @endcode
-**/
-#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
-
-
-/**
- Capability Reporting Register of VMfunction Controls (R/O). If(
- CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
- @endcode
-**/
-#define MSR_IA32_VMX_VMFUNC 0x00000491
-
-
-/**
- Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
- IA32_PERF_CAPABILITIES[ 13] = 1.
-
- @param ECX MSR_IA32_A_PMCn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
- AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
- @endcode
- @{
-**/
-#define MSR_IA32_A_PMC0 0x000004C1
-#define MSR_IA32_A_PMC1 0x000004C2
-#define MSR_IA32_A_PMC2 0x000004C3
-#define MSR_IA32_A_PMC3 0x000004C4
-#define MSR_IA32_A_PMC4 0x000004C5
-#define MSR_IA32_A_PMC5 0x000004C6
-#define MSR_IA32_A_PMC6 0x000004C7
-#define MSR_IA32_A_PMC7 0x000004C8
-/// @}
-
-
-/**
- (R/W). If IA32_MCG_CAP.LMCE_P =1.
-
- @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
- AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_MCG_EXT_CTL 0x000004D0
-
-/**
- MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] LMCE_EN.
- ///
- UINT32 LMCE_EN:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MCG_EXT_CTL_REGISTER;
-
-
-/**
- Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
- ECX=0H): EBX[2] = 1.
-
- @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
- @endcode
-**/
-#define MSR_IA32_SGX_SVN_STATUS 0x00000500
-
-/**
- MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated
- /// Code Modules (ACMs)".
- ///
- UINT32 Lock:1;
- UINT32 Reserved1:15;
- ///
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with
- /// Authenticated Code Modules (ACMs)".
- ///
- UINT32 SGX_SVN_SINIT:8;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SGX_SVN_STATUS_REGISTER;
-
-
-/**
- Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
- && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
- ) ).
-
- @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
- AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:7;
- ///
- /// [Bits 31:7] Base physical address.
- ///
- UINT32 Base:25;
- ///
- /// [Bits 63:32] Base physical address.
- ///
- UINT32 BaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;
-
-
-/**
- Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
- ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
- (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
-
- @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
- AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:7;
- ///
- /// [Bits 31:7] MaskOrTableOffset.
- ///
- UINT32 MaskOrTableOffset:25;
- ///
- /// [Bits 63:32] Output Offset.
- ///
- UINT32 OutputOffset:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;
-
-
-/**
- Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
-
- @param ECX MSR_IA32_RTIT_CTL (0x00000570)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_RTIT_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
- AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_RTIT_CTL 0x00000570
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] TraceEn.
- ///
- UINT32 TraceEn:1;
- ///
- /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
- ///
- UINT32 CYCEn:1;
- ///
- /// [Bit 2] OS.
- ///
- UINT32 OS:1;
- ///
- /// [Bit 3] User.
- ///
- UINT32 User:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
- ///
- UINT32 FabricEn:1;
- ///
- /// [Bit 7] CR3 filter.
- ///
- UINT32 CR3:1;
- ///
- /// [Bit 8] ToPA.
- ///
- UINT32 ToPA:1;
- ///
- /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
- ///
- UINT32 MTCEn:1;
- ///
- /// [Bit 10] TSCEn.
- ///
- UINT32 TSCEn:1;
- ///
- /// [Bit 11] DisRETC.
- ///
- UINT32 DisRETC:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 13] BranchEn.
- ///
- UINT32 BranchEn:1;
- ///
- /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
- ///
- UINT32 MTCFreq:4;
- UINT32 Reserved3:1;
- ///
- /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
- ///
- UINT32 CYCThresh:4;
- UINT32 Reserved4:1;
- ///
- /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
- ///
- UINT32 PSBFreq:4;
- UINT32 Reserved5:4;
- ///
- /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
- ///
- UINT32 ADDR0_CFG:4;
- ///
- /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
- ///
- UINT32 ADDR1_CFG:4;
- ///
- /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
- ///
- UINT32 ADDR2_CFG:4;
- ///
- /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
- ///
- UINT32 ADDR3_CFG:4;
- UINT32 Reserved6:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_CTL_REGISTER;
-
-
-/**
- Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
-
- @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_RTIT_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
- AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_RTIT_STATUS 0x00000571
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] FilterEn, (writes ignored).
- /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
- ///
- UINT32 FilterEn:1;
- ///
- /// [Bit 1] ContexEn, (writes ignored).
- ///
- UINT32 ContexEn:1;
- ///
- /// [Bit 2] TriggerEn, (writes ignored).
- ///
- UINT32 TriggerEn:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 4] Error.
- ///
- UINT32 Error:1;
- ///
- /// [Bit 5] Stopped.
- ///
- UINT32 Stopped:1;
- UINT32 Reserved2:26;
- ///
- /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
- ///
- UINT32 PacketByteCnt:17;
- UINT32 Reserved3:15;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_STATUS_REGISTER;
-
-
-/**
- Trace Filter CR3 Match Register (R/W).
- If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
-
- @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
- AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:5;
- ///
- /// [Bits 31:5] CR3[63:5] value to match.
- ///
- UINT32 Cr3:27;
- ///
- /// [Bits 63:32] CR3[63:5] value to match.
- ///
- UINT32 Cr3Hi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_CR3_MATCH_REGISTER;
-
-
-/**
- Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
-
- @param ECX MSR_IA32_RTIT_ADDRn_A
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_RTIT_ADDR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
- AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_IA32_RTIT_ADDR0_A 0x00000580
-#define MSR_IA32_RTIT_ADDR1_A 0x00000582
-#define MSR_IA32_RTIT_ADDR2_A 0x00000584
-#define MSR_IA32_RTIT_ADDR3_A 0x00000586
-/// @}
-
-
-/**
- Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
-
- @param ECX MSR_IA32_RTIT_ADDRn_B
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_RTIT_ADDR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
- AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_IA32_RTIT_ADDR0_B 0x00000581
-#define MSR_IA32_RTIT_ADDR1_B 0x00000583
-#define MSR_IA32_RTIT_ADDR2_B 0x00000585
-#define MSR_IA32_RTIT_ADDR3_B 0x00000587
-/// @}
-
-
-/**
- MSR information returned for MSR indexes
- #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
- #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Virtual Address.
- ///
- UINT32 VirtualAddress:32;
- ///
- /// [Bits 47:32] Virtual Address.
- ///
- UINT32 VirtualAddressHi:16;
- ///
- /// [Bits 63:48] SignExt_VA.
- ///
- UINT32 SignExt_VA:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_ADDR_REGISTER;
-
-
-/**
- DS Save Area (R/W) Points to the linear address of the first byte of the DS
- buffer management area, which is used to manage the BTS and PEBS buffers.
- See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
- = 1.
-
- [Bits 31..0] The linear address of the first byte of the DS buffer
- management area, if not in IA-32e mode.
-
- [Bits 63..0] The linear address of the first byte of the DS buffer
- management area, if IA-32e mode is active.
-
- @param ECX MSR_IA32_DS_AREA (0x00000600)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_DS_AREA_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_DS_AREA_REGISTER.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
- AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
- @endcode
-**/
-#define MSR_IA32_DS_AREA 0x00000600
-
-
-/**
- TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
- 1.
-
- @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
- AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
- @endcode
-**/
-#define MSR_IA32_TSC_DEADLINE 0x000006E0
-
-
-/**
- Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
-
- @param ECX MSR_IA32_PM_ENABLE (0x00000770)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PM_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PM_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PM_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
- AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PM_ENABLE 0x00000770
-
-/**
- MSR information returned for MSR index #MSR_IA32_PM_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
- /// CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 HWP_ENABLE:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PM_ENABLE_REGISTER;
-
-
-/**
- HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
-
- @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
- @endcode
-**/
-#define MSR_IA32_HWP_CAPABILITIES 0x00000771
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
- /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Highest_Performance:8;
- ///
- /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
- /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Guaranteed_Performance:8;
- ///
- /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
- /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Most_Efficient_Performance:8;
- ///
- /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
- /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Lowest_Performance:8;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_CAPABILITIES_REGISTER;
-
-
-/**
- Power Management Control Hints for All Logical Processors in a Package
- (R/W). If CPUID.06H:EAX.[11] = 1.
-
- @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
- AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[11] = 1.
- ///
- UINT32 Minimum_Performance:8;
- ///
- /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[11] = 1.
- ///
- UINT32 Maximum_Performance:8;
- ///
- /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
- /// If CPUID.06H:EAX.[11] = 1.
- ///
- UINT32 Desired_Performance:8;
- ///
- /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
- /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
- ///
- UINT32 Energy_Performance_Preference:8;
- ///
- /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
- ///
- UINT32 Activity_Window:10;
- UINT32 Reserved:22;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_REQUEST_PKG_REGISTER;
-
-
-/**
- Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
-
- @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
- AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_HWP_INTERRUPT 0x00000773
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
- /// Notifications". If CPUID.06H:EAX.[8] = 1.
- ///
- UINT32 EN_Guaranteed_Performance_Change:1;
- ///
- /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
- /// If CPUID.06H:EAX.[8] = 1.
- ///
- UINT32 EN_Excursion_Minimum:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_INTERRUPT_REGISTER;
-
-
-/**
- Power Management Control Hints to a Logical Processor (R/W). If
- CPUID.06H:EAX.[7] = 1.
-
- @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_HWP_REQUEST_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
- AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_HWP_REQUEST 0x00000774
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Minimum_Performance:8;
- ///
- /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Maximum_Performance:8;
- ///
- /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
- /// If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Desired_Performance:8;
- ///
- /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
- /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
- ///
- UINT32 Energy_Performance_Preference:8;
- ///
- /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
- ///
- UINT32 Activity_Window:10;
- ///
- /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
- ///
- UINT32 Package_Control:1;
- UINT32 Reserved:21;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_REQUEST_REGISTER;
-
-
-/**
- Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
- CPUID.06H:EAX.[7] = 1.
-
- @param ECX MSR_IA32_HWP_STATUS (0x00000777)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_HWP_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
- AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_HWP_STATUS 0x00000777
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
- /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Guaranteed_Performance_Change:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
- /// Feedback". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Excursion_To_Minimum:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_STATUS_REGISTER;
-
-
-/**
- x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
- && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
- @endcode
-**/
-#define MSR_IA32_X2APIC_APICID 0x00000802
-
-
-/**
- x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
- @endcode
-**/
-#define MSR_IA32_X2APIC_VERSION 0x00000803
-
-
-/**
- x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_TPR 0x00000808
-
-
-/**
- x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
- @endcode
-**/
-#define MSR_IA32_X2APIC_PPR 0x0000080A
-
-
-/**
- x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
- = 1.
-
- @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = 0;
- AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_EOI 0x0000080B
-
-
-/**
- x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
- @endcode
-**/
-#define MSR_IA32_X2APIC_LDR 0x0000080D
-
-
-/**
- x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
- && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_SIVR 0x0000080F
-
-
-/**
- x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_ISRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
- @endcode
- @{
-**/
-#define MSR_IA32_X2APIC_ISR0 0x00000810
-#define MSR_IA32_X2APIC_ISR1 0x00000811
-#define MSR_IA32_X2APIC_ISR2 0x00000812
-#define MSR_IA32_X2APIC_ISR3 0x00000813
-#define MSR_IA32_X2APIC_ISR4 0x00000814
-#define MSR_IA32_X2APIC_ISR5 0x00000815
-#define MSR_IA32_X2APIC_ISR6 0x00000816
-#define MSR_IA32_X2APIC_ISR7 0x00000817
-/// @}
-
-
-/**
- x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_TMRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
- @endcode
- @{
-**/
-#define MSR_IA32_X2APIC_TMR0 0x00000818
-#define MSR_IA32_X2APIC_TMR1 0x00000819
-#define MSR_IA32_X2APIC_TMR2 0x0000081A
-#define MSR_IA32_X2APIC_TMR3 0x0000081B
-#define MSR_IA32_X2APIC_TMR4 0x0000081C
-#define MSR_IA32_X2APIC_TMR5 0x0000081D
-#define MSR_IA32_X2APIC_TMR6 0x0000081E
-#define MSR_IA32_X2APIC_TMR7 0x0000081F
-/// @}
-
-
-/**
- x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_IRRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
- @endcode
- @{
-**/
-#define MSR_IA32_X2APIC_IRR0 0x00000820
-#define MSR_IA32_X2APIC_IRR1 0x00000821
-#define MSR_IA32_X2APIC_IRR2 0x00000822
-#define MSR_IA32_X2APIC_IRR3 0x00000823
-#define MSR_IA32_X2APIC_IRR4 0x00000824
-#define MSR_IA32_X2APIC_IRR5 0x00000825
-#define MSR_IA32_X2APIC_IRR6 0x00000826
-#define MSR_IA32_X2APIC_IRR7 0x00000827
-/// @}
-
-
-/**
- x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_ESR 0x00000828
-
-
-/**
- x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
- CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
-
-
-/**
- x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_ICR 0x00000830
-
-
-/**
- x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
-
-
-/**
- x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
- 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
-
-
-/**
- x2APIC LVT Performance Monitor Interrupt Register (R/W). If
- CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
-
-
-/**
- x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
-
-
-/**
- x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
-
-
-/**
- x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
-
-
-/**
- x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
- AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
-
-
-/**
- x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
- @endcode
-**/
-#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
-
-
-/**
- x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
- AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
-
-
-/**
- x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = 0;
- AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
- @endcode
-**/
-#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
-
-
-/**
- Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
-
- @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
- AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
-
-/**
- MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
- /// Default is 0. If CPUID.01H:ECX.[11] = 1.
- ///
- UINT32 Enable:1;
- UINT32 Reserved1:29;
- ///
- /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
- /// lock bit is set automatically on the first SMI assertion even if not
- /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
- ///
- UINT32 Lock:1;
- ///
- /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
- /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
- ///
- UINT32 DebugOccurred:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_DEBUG_INTERFACE_REGISTER;
-
-
-/**
- L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
-
- @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_L3_QOS_CFG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
- AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_L3_QOS_CFG 0x00000C81
-
-/**
- MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
- /// in Code and Data Prioritization (CDP) mode.
- ///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_L3_QOS_CFG_REGISTER;
-
-
-/**
- Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
- = 1 ).
-
- @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_QM_EVTSEL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
- AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_QM_EVTSEL 0x00000C8D
-
-/**
- MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
- /// IA32_QM_CTR.
- ///
- UINT32 EventID:8;
- UINT32 Reserved:24;
- ///
- /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
- /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
- /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
- ///
- UINT32 ResourceMonitoringID:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_QM_EVTSEL_REGISTER;
-
-
-/**
- Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
- ).
-
- @param ECX MSR_IA32_QM_CTR (0x00000C8E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_QM_CTR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_QM_CTR_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_QM_CTR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
- @endcode
-**/
-#define MSR_IA32_QM_CTR 0x00000C8E
-
-/**
- MSR information returned for MSR index #MSR_IA32_QM_CTR
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Resource Monitored Data.
- ///
- UINT32 ResourceMonitoredData:32;
- ///
- /// [Bits 61:32] Resource Monitored Data.
- ///
- UINT32 ResourceMonitoredDataHi:30;
- ///
- /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
- /// available or not monitored for this resource or RMID.
- ///
- UINT32 Unavailable:1;
- ///
- /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
- /// written to IA32_PQR_QM_EVTSEL.
- ///
- UINT32 Error:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_QM_CTR_REGISTER;
-
-
-/**
- Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =
- 1 ).
-
- @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PQR_ASSOC_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
- AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PQR_ASSOC 0x00000C8F
-
-/**
- MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
- /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
- /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
- ///
- UINT32 ResourceMonitoringID:32;
- ///
- /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
- /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
- /// ECX=0):EBX.[15] = 1 ).
- ///
- UINT32 COS:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PQR_ASSOC_REGISTER;
-
-
-/**
- Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
- ECX=0H):EBX[14] = 1).
-
- @param ECX MSR_IA32_BNDCFGS (0x00000D90)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_BNDCFGS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_BNDCFGS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_BNDCFGS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
- AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_BNDCFGS 0x00000D90
-
-/**
- MSR information returned for MSR index #MSR_IA32_BNDCFGS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
- /// instructions in the absence of the BND prefix.
- ///
- UINT32 BNDPRESERVE:1;
- UINT32 Reserved:10;
- ///
- /// [Bits 31:12] Base Address of Bound Directory.
- ///
- UINT32 Base:20;
- ///
- /// [Bits 63:32] Base Address of Bound Directory.
- ///
- UINT32 BaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_BNDCFGS_REGISTER;
-
-
-/**
- Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
-
- @param ECX MSR_IA32_XSS (0x00000DA0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_XSS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_XSS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_XSS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
- AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_XSS 0x00000DA0
-
-/**
- MSR information returned for MSR index #MSR_IA32_XSS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bit 8] Trace Packet Configuration State (R/W).
- ///
- UINT32 TracePacketConfigurationState:1;
- UINT32 Reserved2:23;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_XSS_REGISTER;
-
-
-/**
- Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
-
- @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
- AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
-
-/**
- MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
- /// logical processors in the package. See Section 14.5.2, "Package level
- /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
- ///
- UINT32 HDC_Pkg_Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PKG_HDC_CTL_REGISTER;
-
-
-/**
- Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
-
- @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PM_CTL1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PM_CTL1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_PM_CTL1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
- AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_PM_CTL1 0x00000DB1
-
-/**
- MSR information returned for MSR index #MSR_IA32_PM_CTL1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
- /// package level HDC control. See Section 14.5.3.
- /// If CPUID.06H:EAX.[13] = 1.
- ///
- UINT32 HDC_Allow_Block:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PM_CTL1_REGISTER;
-
-
-/**
- Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
- Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
- processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
-
- @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
- @endcode
-**/
-#define MSR_IA32_THREAD_STALL 0x00000DB2
-
-
-/**
- Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
- CPUID.80000001H:EDX.[2 9]).
-
- @param ECX MSR_IA32_EFER (0xC0000080)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_EFER_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_EFER_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_EFER_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
- AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_EFER 0xC0000080
-
-/**
- MSR information returned for MSR index #MSR_IA32_EFER
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
- /// instructions in 64-bit mode.
- ///
- UINT32 SCE:1;
- UINT32 Reserved1:7;
- ///
- /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
- /// operation.
- ///
- UINT32 LME:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
- /// is active when set.
- ///
- UINT32 LMA:1;
- ///
- /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
- ///
- UINT32 NXE:1;
- UINT32 Reserved3:20;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_EFER_REGISTER;
-
-
-/**
- System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_STAR (0xC0000081)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_STAR);
- AsmWriteMsr64 (MSR_IA32_STAR, Msr);
- @endcode
-**/
-#define MSR_IA32_STAR 0xC0000081
-
-
-/**
- IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_LSTAR (0xC0000082)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
- AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
- @endcode
-**/
-#define MSR_IA32_LSTAR 0xC0000082
-
-
-/**
- System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_FMASK (0xC0000084)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FMASK);
- AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
- @endcode
-**/
-#define MSR_IA32_FMASK 0xC0000084
-
-
-/**
- Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_FS_BASE (0xC0000100)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
- AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
- @endcode
-**/
-#define MSR_IA32_FS_BASE 0xC0000100
-
-
-/**
- Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_GS_BASE (0xC0000101)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
- AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
- @endcode
-**/
-#define MSR_IA32_GS_BASE 0xC0000101
-
-
-/**
- Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
- AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
- @endcode
-**/
-#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
-
-
-/**
- Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
-
- @param ECX MSR_IA32_TSC_AUX (0xC0000103)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_TSC_AUX_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_TSC_AUX_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IA32_TSC_AUX_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
- AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
- @endcode
-**/
-#define MSR_IA32_TSC_AUX 0xC0000103
-
-/**
- MSR information returned for MSR index #MSR_IA32_TSC_AUX
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] AUX: Auxiliary signature of TSC.
- ///
- UINT32 AUX:32;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_TSC_AUX_REGISTER;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h deleted file mode 100644 index eb24840746..0000000000 --- a/UefiCpuPkg/Include/Register/Cpuid.h +++ /dev/null @@ -1,3406 +0,0 @@ -/** @file
- CPUID leaf definitions.
-
- Provides defines for CPUID leaf indexes. Data structures are provided for
- registers returned by a CPUID leaf that contain one or more bit fields.
- If a register returned is a single 32-bit value, then a data structure is
- not provided for that register.
-
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials are licensed and made available under
- the terms and conditions of the BSD License which accompanies this distribution.
- The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
- December 2015, CPUID instruction.
-
-**/
-
-#ifndef __CPUID_H__
-#define __CPUID_H__
-
-/**
- CPUID Signature Information
-
- @param EAX CPUID_SIGNATURE (0x00)
-
- @retval EAX Returns the highest value the CPUID instruction recognizes for
- returning basic processor information. The value is returned is
- processor specific.
- @retval EBX First 4 characters of a vendor identification string.
- @retval ECX Last 4 characters of a vendor identification string.
- @retval EDX Middle 4 characters of a vendor identification string.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
- UINT32 Ebx;
- UINT32 Ecx;
- UINT32 Edx;
-
- AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
- @endcode
-**/
-#define CPUID_SIGNATURE 0x00
-
-///
-/// @{ CPUID signature values returned by Intel processors
-///
-#define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
-#define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
-#define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
-///
-/// @}
-///
-
-
-/**
- CPUID Version Information
-
- @param EAX CPUID_VERSION_INFO (0x01)
-
- @retval EAX Returns Model, Family, Stepping Information described by the
- type CPUID_VERSION_INFO_EAX.
- @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
- the type CPUID_VERSION_INFO_EBX.
- @retval ECX CPU Feature Information described by the type
- CPUID_VERSION_INFO_ECX.
- @retval EDX CPU Feature Information described by the type
- CPUID_VERSION_INFO_EDX.
-
- <b>Example usage</b>
- @code
- CPUID_VERSION_INFO_EAX Eax;
- CPUID_VERSION_INFO_EBX Ebx;
- CPUID_VERSION_INFO_ECX Ecx;
- CPUID_VERSION_INFO_EDX Edx;
-
- AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
- @endcode
-**/
-#define CPUID_VERSION_INFO 0x01
-
-/**
- CPUID Version Information returned in EAX for CPUID leaf
- #CPUID_VERSION_INFO.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID
- UINT32 Model:4; ///< [Bits 7:4] Model
- UINT32 FamilyId:4; ///< [Bits 11:8] Family
- UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type
- UINT32 Reserved1:2; ///< [Bits 15:14] Reserved
- UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID
- UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID
- UINT32 Reserved2:4; ///< Reserved
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_VERSION_INFO_EAX;
-
-///
-/// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
-///
-#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
-#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
-#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
-///
-/// @}
-///
-
-/**
- CPUID Version Information returned in EBX for CPUID leaf
- #CPUID_VERSION_INFO.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Provides an entry into a brand string table that contains
- /// brand strings for IA-32 processors.
- ///
- UINT32 BrandIndex:8;
- ///
- /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
- /// and CLFLUSHOPT instructions in 8-byte increments. This field was
- /// introduced in the Pentium 4 processor.
- ///
- UINT32 CacheLineSize:8;
- ///
- /// [Bits 23:16] Maximum number of addressable IDs for logical processors
- /// in this physical package.
- ///
- /// @note
- /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
- /// the number of unique initial APICIDs reserved for addressing different
- /// logical processors in a physical package. This field is only valid if
- /// CPUID.1.EDX.HTT[bit 28]= 1.
- ///
- UINT32 MaximumAddressableIdsForLogicalProcessors:8;
- ///
- /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
- /// processor during power up. This field was introduced in the Pentium 4
- /// processor.
- ///
- UINT32 InitialLocalApicId:8;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_VERSION_INFO_EBX;
-
-/**
- CPUID Version Information returned in ECX for CPUID leaf
- #CPUID_VERSION_INFO.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
- /// processor supports this technology
- ///
- UINT32 SSE3:1;
- ///
- /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
- /// instruction. Carryless Multiplication
- ///
- UINT32 PCLMULQDQ:1;
- ///
- /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
- /// DS area using 64-bit layout.
- ///
- UINT32 DTES64:1;
- ///
- /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
- /// this feature.
- ///
- UINT32 MONITOR:1;
- ///
- /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
- /// supports the extensions to the Debug Store feature to allow for branch
- /// message storage qualified by CPL
- ///
- UINT32 DS_CPL:1;
- ///
- /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
- /// processor supports this technology.
- ///
- UINT32 VMX:1;
- ///
- /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
- /// supports this technology
- ///
- UINT32 SMX:1;
- ///
- /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
- /// that the processor supports this technology
- ///
- UINT32 EIST:1;
- ///
- /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
- /// supports this technology
- ///
- UINT32 TM2:1;
- ///
- /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
- /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
- /// extensions are not present in the processor.
- ///
- UINT32 SSSE3:1;
- ///
- /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
- /// can be set to either adaptive mode or shared mode. A value of 0 indicates
- /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
- /// Bit 24 (L1 Data Cache Context Mode) for details
- ///
- UINT32 CNXT_ID:1;
- ///
- /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
- /// MSR for silicon debug
- ///
- UINT32 SDBG:1;
- ///
- /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
- /// Add) extensions using YMM state.
- ///
- UINT32 FMA:1;
- ///
- /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
- /// is available.
- ///
- UINT32 CMPXCHG16B:1;
- ///
- /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
- /// supports changing IA32_MISC_ENABLE[Bit 23].
- ///
- UINT32 xTPR_Update_Control:1;
- ///
- /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
- /// processor supports the performance and debug feature indication MSR
- /// IA32_PERF_CAPABILITIES.
- ///
- UINT32 PDCM:1;
- UINT32 Reserved:1;
- ///
- /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
- /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
- ///
- UINT32 PCID:1;
- ///
- /// [Bit 18] A value of 1 indicates the processor supports the ability to
- /// prefetch data from a memory mapped device. Direct Cache Access.
- ///
- UINT32 DCA:1;
- ///
- /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
- ///
- UINT32 SSE4_1:1;
- ///
- /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
- ///
- UINT32 SSE4_2:1;
- ///
- /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
- /// feature.
- ///
- UINT32 x2APIC:1;
- ///
- /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
- /// instruction.
- ///
- UINT32 MOVBE:1;
- ///
- /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
- /// instruction.
- ///
- UINT32 POPCNT:1;
- ///
- /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
- /// supports one-shot operation using a TSC deadline value.
- ///
- UINT32 TSC_Deadline:1;
- ///
- /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
- /// instruction extensions.
- ///
- UINT32 AESNI:1;
- ///
- /// [Bit 26] A value of 1 indicates that the processor supports the
- /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
- /// instructions, and XCR0.
- ///
- UINT32 XSAVE:1;
- ///
- /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
- /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
- /// processor extended state management using XSAVE/XRSTOR.
- ///
- UINT32 OSXSAVE:1;
- ///
- /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
- /// extensions.
- ///
- UINT32 AVX:1;
- ///
- /// [Bit 29] A value of 1 indicates that processor supports 16-bit
- /// floating-point conversion instructions.
- ///
- UINT32 F16C:1;
- ///
- /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
- ///
- UINT32 RDRAND:1;
- ///
- /// [Bit 31] Always returns 0.
- ///
- UINT32 NotUsed:1;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_VERSION_INFO_ECX;
-
-/**
- CPUID Version Information returned in EDX for CPUID leaf
- #CPUID_VERSION_INFO.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
- ///
- UINT32 FPU:1;
- ///
- /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
- /// including CR4.VME for controlling the feature, CR4.PVI for protected
- /// mode virtual interrupts, software interrupt indirection, expansion of
- /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
- /// EFLAGS.VIP flags.
- ///
- UINT32 VME:1;
- ///
- /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
- /// CR4.DE for controlling the feature, and optional trapping of accesses to
- /// DR4 and DR5.
- ///
- UINT32 DE:1;
- ///
- /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
- /// including CR4.PSE for controlling the feature, the defined dirty bit in
- /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
- /// PDEs, and PTEs.
- ///
- UINT32 PSE:1;
- ///
- /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
- /// including CR4.TSD for controlling privilege.
- ///
- UINT32 TSC:1;
- ///
- /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
- /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
- /// implementation dependent.
- ///
- UINT32 MSR:1;
- ///
- /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
- /// bits are supported: extended page table entry formats, an extra level in
- /// the page translation tables is defined, 2-MByte pages are supported
- /// instead of 4 Mbyte pages if PAE bit is 1.
- ///
- UINT32 PAE:1;
- ///
- /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
- /// Checks, including CR4.MCE for controlling the feature. This feature does
- /// not define the model-specific implementations of machine-check error
- /// logging, reporting, and processor shutdowns. Machine Check exception
- /// handlers may have to depend on processor version to do model specific
- /// processing of the exception, or test for the presence of the Machine
- /// Check feature.
- ///
- UINT32 MCE:1;
- ///
- /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
- /// instruction is supported (implicitly locked and atomic).
- ///
- UINT32 CX8:1;
- ///
- /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
- /// Interrupt Controller (APIC), responding to memory mapped commands in the
- /// physical address range FFFE0000H to FFFE0FFFH (by default - some
- /// processors permit the APIC to be relocated).
- ///
- UINT32 APIC:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
- /// and associated MSRs are supported.
- ///
- UINT32 SEP:1;
- ///
- /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
- /// MSR contains feature bits that describe what memory types are supported,
- /// how many variable MTRRs are supported, and whether fixed MTRRs are
- /// supported.
- ///
- UINT32 MTRR:1;
- ///
- /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
- /// entries that map a page, indicating TLB entries that are common to
- /// different processes and need not be flushed. The CR4.PGE bit controls
- /// this feature.
- ///
- UINT32 PGE:1;
- ///
- /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,
- /// which provides a compatible mechanism for error reporting in P6 family,
- /// Pentium 4, Intel Xeon processors, and future processors, is supported.
- /// The MCG_CAP MSR contains feature bits describing how many banks of error
- /// reporting MSRs are supported.
- ///
- UINT32 MCA:1;
- ///
- /// [Bit 15] Conditional Move Instructions. The conditional move instruction
- /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
- /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
- ///
- UINT32 CMOV:1;
- ///
- /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
- /// feature augments the Memory Type Range Registers (MTRRs), allowing an
- /// operating system to specify attributes of memory accessed through a
- /// linear address on a 4KB granularity.
- ///
- UINT32 PAT:1;
- ///
- /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
- /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
- /// indicates that upper bits of the physical address of a 4-MByte page are
- /// encoded in bits 20:13 of the page-directory entry. Such physical
- /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
- ///
- UINT32 PSE_36:1;
- ///
- /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
- /// processor identification number feature and the feature is enabled.
- ///
- UINT32 PSN:1;
- ///
- /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
- ///
- UINT32 CLFSH:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 21] Debug Store. The processor supports the ability to write debug
- /// information into a memory resident buffer. This feature is used by the
- /// branch trace store (BTS) and precise event-based sampling (PEBS)
- /// facilities.
- ///
- UINT32 DS:1;
- ///
- /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
- /// processor implements internal MSRs that allow processor temperature to
- /// be monitored and processor performance to be modulated in predefined
- /// duty cycles under software control.
- ///
- UINT32 ACPI:1;
- ///
- /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
- /// technology.
- ///
- UINT32 MMX:1;
- ///
- /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
- /// instructions are supported for fast save and restore of the floating
- /// point context. Presence of this bit also indicates that CR4.OSFXSR is
- /// available for an operating system to indicate that it supports the
- /// FXSAVE and FXRSTOR instructions.
- ///
- UINT32 FXSR:1;
- ///
- /// [Bit 25] SSE. The processor supports the SSE extensions.
- ///
- UINT32 SSE:1;
- ///
- /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
- ///
- UINT32 SSE2:1;
- ///
- /// [Bit 27] Self Snoop. The processor supports the management of
- /// conflicting memory types by performing a snoop of its own cache
- /// structure for transactions issued to the bus.
- ///
- UINT32 SS:1;
- ///
- /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
- /// indicates there is only a single logical processor in the package and
- /// software should assume only a single APIC ID is reserved. A value of 1
- /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
- /// addressable IDs for logical processors in this package) is valid for the
- /// package.
- ///
- UINT32 HTT:1;
- ///
- /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
- /// automatic thermal control circuitry (TCC).
- ///
- UINT32 TM:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 31] Pending Break Enable. The processor supports the use of the
- /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
- /// asserted) to signal the processor that an interrupt is pending and that
- /// the processor should return to normal operation to handle the interrupt.
- /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
- ///
- UINT32 PBE:1;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_VERSION_INFO_EDX;
-
-
-/**
- CPUID Cache and TLB Information
-
- @param EAX CPUID_CACHE_INFO (0x02)
-
- @retval EAX Cache and TLB Information described by the type
- CPUID_CACHE_INFO_CACHE_TLB.
- CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
- 0x01 and must be ignored. Only valid if
- CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
- @retval EBX Cache and TLB Information described by the type
- CPUID_CACHE_INFO_CACHE_TLB. Only valid if
- CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
- @retval ECX Cache and TLB Information described by the type
- CPUID_CACHE_INFO_CACHE_TLB. Only valid if
- CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
- @retval EDX Cache and TLB Information described by the type
- CPUID_CACHE_INFO_CACHE_TLB. Only valid if
- CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
-
- <b>Example usage</b>
- @code
- CPUID_CACHE_INFO_CACHE_TLB Eax;
- CPUID_CACHE_INFO_CACHE_TLB Ebx;
- CPUID_CACHE_INFO_CACHE_TLB Ecx;
- CPUID_CACHE_INFO_CACHE_TLB Edx;
-
- AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
- @endcode
-
- <b>Cache Descriptor values</b>
- <table>
- <tr><th>Value </th><th> Type </th><th> Description </th></tr>
- <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
- <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
- <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
- <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
- <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
- <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
- <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
- 32 byte line size</td></tr>
- <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
- 32 byte line size</td></tr>
- <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
- 64 byte line size</td></tr>
- <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
- <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
- 2 lines per sector</td></tr>
- <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
- 2 lines per sector</td></tr>
- <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
- 2 lines per sector</td></tr>
- <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
- 2 lines per sector</td></tr>
- <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
- 64 byte line size</td></tr>
- <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
- 64 byte line size</td></tr>
- <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
- no 3rd-level cache</td></tr>
- <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
- (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
- 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
- <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
- <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
- <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
- <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
- <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
- <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
- <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
- <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
- <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
- <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
- <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
- <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
- <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>
- <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
- <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
- <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
- <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
- <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
- <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
- <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
- <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
- <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
- <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
- 2 lines per sector</td></tr>
- <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
- 2 lines per sector</td></tr>
- <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
- 2 lines per sector</td></tr>
- <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
- 2 lines per sector</td></tr>
- <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
- <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
- <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
- <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
- <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
- <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
- <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
- <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
- <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
- <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
- <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
- <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
- 128 entries</td></tr>
- <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
- <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
- <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
- 1024 entries</td></tr>
- <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
- <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
- 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
- <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
- <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
- <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
- <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
- <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
- use CPUID leaf 4 to query cache parameters</td></tr>
- </table>
-**/
-#define CPUID_CACHE_INFO 0x02
-
-/**
- CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
- leaf #CPUID_CACHE_INFO.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:31;
- ///
- /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
- /// if 1, then none of the cache descriptor bytes in the register are valid.
- ///
- UINT32 NotValid:1;
- } Bits;
- ///
- /// Array of Cache and TLB descriptor bytes
- ///
- UINT8 CacheDescriptor[4];
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_CACHE_INFO_CACHE_TLB;
-
-
-/**
- CPUID Processor Serial Number
-
- Processor serial number (PSN) is not supported in the Pentium 4 processor
- or later. On all models, use the PSN flag (returned using CPUID) to check
- for PSN support before accessing the feature.
-
- @param EAX CPUID_SERIAL_NUMBER (0x03)
-
- @retval EAX Reserved.
- @retval EBX Reserved.
- @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
- Pentium III processor only; otherwise, the value in this
- register is reserved.)
- @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
- Pentium III processor only; otherwise, the value in this
- register is reserved.)
-
- <b>Example usage</b>
- @code
- UINT32 Ecx;
- UINT32 Edx;
-
- AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
- @endcode
-**/
-#define CPUID_SERIAL_NUMBER 0x03
-
-
-/**
- CPUID Cache Parameters
-
- @param EAX CPUID_CACHE_PARAMS (0x04)
- @param ECX Cache Level. Valid values start at 0. Software can enumerate
- the deterministic cache parameters for each level of the cache
- hierarchy starting with an index value of 0, until the
- parameters report the value associated with the CacheType
- field in CPUID_CACHE_PARAMS_EAX is 0.
-
- @retval EAX Returns cache type information described by the type
- CPUID_CACHE_PARAMS_EAX.
- @retval EBX Returns cache line and associativity information described by
- the type CPUID_CACHE_PARAMS_EBX.
- @retval ECX Returns the number of sets in the cache.
- @retval EDX Returns cache WINVD/INVD behavior described by the type
- CPUID_CACHE_PARAMS_EDX.
-
- <b>Example usage</b>
- @code
- UINT32 CacheLevel;
- CPUID_CACHE_PARAMS_EAX Eax;
- CPUID_CACHE_PARAMS_EBX Ebx;
- UINT32 Ecx;
- CPUID_CACHE_PARAMS_EDX Edx;
-
- CacheLevel = 0;
- do {
- AsmCpuidEx (
- CPUID_CACHE_PARAMS, CacheLevel,
- &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
- );
- CacheLevel++;
- } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
- @endcode
-**/
-#define CPUID_CACHE_PARAMS 0x04
-
-/**
- CPUID Cache Parameters Information returned in EAX for CPUID leaf
- #CPUID_CACHE_PARAMS.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
- /// then there is no information for the requested cache level.
- ///
- UINT32 CacheType:5;
- ///
- /// [Bits 7:5] Cache level (Starts at 1).
- ///
- UINT32 CacheLevel:3;
- ///
- /// [Bit 8] Self Initializing cache level (does not need SW initialization).
- ///
- UINT32 SelfInitializingCache:1;
- ///
- /// [Bit 9] Fully Associative cache.
- ///
- UINT32 FullyAssociativeCache:1;
- ///
- /// [Bits 13:10] Reserved.
- ///
- UINT32 Reserved:4;
- ///
- /// [Bits 25:14] Maximum number of addressable IDs for logical processors
- /// sharing this cache.
- ///
- /// Add one to the return value to get the result.
- /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
- /// is the number of unique initial APIC IDs reserved for addressing
- /// different logical processors sharing this cache.
- ///
- UINT32 MaximumAddressableIdsForLogicalProcessors:12;
- ///
- /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
- /// the physical package.
- ///
- /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
- /// is the number of unique Core_IDs reserved for addressing different
- /// processor cores in a physical package. Core ID is a subset of bits of
- /// the initial APIC ID.
- /// The returned value is constant for valid initial values in ECX. Valid
- /// ECX values start from 0.
- ///
- UINT32 MaximumAddressableIdsForProcessorCores:6;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_CACHE_PARAMS_EAX;
-
-///
-/// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
-///
-#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
-#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
-#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
-#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
-///
-/// @}
-///
-
-/**
- CPUID Cache Parameters Information returned in EBX for CPUID leaf
- #CPUID_CACHE_PARAMS.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
- /// get the result.
- ///
- UINT32 LineSize:12;
- ///
- /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
- /// get the result.
- ///
- UINT32 LinePartitions:10;
- ///
- /// [Bits 31:22] Ways of associativity. Add one to the return value to get
- /// the result.
- ///
- UINT32 Ways:10;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_CACHE_PARAMS_EBX;
-
-/**
- CPUID Cache Parameters Information returned in EDX for CPUID leaf
- #CPUID_CACHE_PARAMS.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Write-Back Invalidate/Invalidate.
- /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
- /// caches for threads sharing this cache.
- /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
- /// non-originating threads sharing this cache.
- ///
- UINT32 Invalidate:1;
- ///
- /// [Bit 1] Cache Inclusiveness.
- /// 0 = Cache is not inclusive of lower cache levels.
- /// 1 = Cache is inclusive of lower cache levels.
- ///
- UINT32 CacheInclusiveness:1;
- ///
- /// [Bit 2] Complex Cache Indexing.
- /// 0 = Direct mapped cache.
- /// 1 = A complex function is used to index the cache, potentially using all
- /// address bits.
- ///
- UINT32 ComplexCacheIndexing:1;
- UINT32 Reserved:29;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_CACHE_PARAMS_EDX;
-
-
-/**
- CPUID MONITOR/MWAIT Information
-
- @param EAX CPUID_MONITOR_MWAIT (0x05)
-
- @retval EAX Smallest monitor-line size in bytes described by the type
- CPUID_MONITOR_MWAIT_EAX.
- @retval EBX Largest monitor-line size in bytes described by the type
- CPUID_MONITOR_MWAIT_EBX.
- @retval ECX Enumeration of Monitor-Mwait extensions support described by
- the type CPUID_MONITOR_MWAIT_ECX.
- @retval EDX Sub C-states supported described by the type
- CPUID_MONITOR_MWAIT_EDX.
-
- <b>Example usage</b>
- @code
- CPUID_MONITOR_MWAIT_EAX Eax;
- CPUID_MONITOR_MWAIT_EBX Ebx;
- CPUID_MONITOR_MWAIT_ECX Ecx;
- CPUID_MONITOR_MWAIT_EDX Edx;
-
- AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
- @endcode
-**/
-#define CPUID_MONITOR_MWAIT 0x05
-
-/**
- CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
- #CPUID_MONITOR_MWAIT.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
- /// monitor granularity).
- ///
- UINT32 SmallestMonitorLineSize:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_MONITOR_MWAIT_EAX;
-
-/**
- CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
- #CPUID_MONITOR_MWAIT.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
- /// monitor granularity).
- ///
- UINT32 LargestMonitorLineSize:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_MONITOR_MWAIT_EBX;
-
-/**
- CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
- #CPUID_MONITOR_MWAIT.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
- /// and EDX are valid.
- ///
- UINT32 ExtensionsSupported:1;
- ///
- /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
- /// interrupts disabled.
- ///
- UINT32 InterruptAsBreak:1;
- UINT32 Reserved:30;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_MONITOR_MWAIT_ECX;
-
-/**
- CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
- #CPUID_MONITOR_MWAIT.
-
- @note
- The definition of C0 through C7 states for MWAIT extension are
- processor-specific C-states, not ACPI C-states.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
- ///
- UINT32 C0States:4;
- ///
- /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
- ///
- UINT32 C1States:4;
- ///
- /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
- ///
- UINT32 C2States:4;
- ///
- /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
- ///
- UINT32 C3States:4;
- ///
- /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
- ///
- UINT32 C4States:4;
- ///
- /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
- ///
- UINT32 C5States:4;
- ///
- /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
- ///
- UINT32 C6States:4;
- ///
- /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
- ///
- UINT32 C7States:4;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_MONITOR_MWAIT_EDX;
-
-
-/**
- CPUID Thermal and Power Management
-
- @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
-
- @retval EAX Thermal and power management features described by the type
- CPUID_THERMAL_POWER_MANAGEMENT_EAX.
- @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
- described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
- @retval ECX Performance features described by the type
- CPUID_THERMAL_POWER_MANAGEMENT_ECX.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
- CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
- CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
-
- AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
- @endcode
-**/
-#define CPUID_THERMAL_POWER_MANAGEMENT 0x06
-
-/**
- CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
- #CPUID_THERMAL_POWER_MANAGEMENT.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Digital temperature sensor is supported if set.
- ///
- UINT32 DigitalTemperatureSensor:1;
- ///
- /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
- ///
- UINT32 TurboBoostTechnology:1;
- ///
- /// [Bit 2] APIC-Timer-always-running feature is supported if set.
- ///
- UINT32 ARAT:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 4] Power limit notification controls are supported if set.
- ///
- UINT32 PLN:1;
- ///
- /// [Bit 5] Clock modulation duty cycle extension is supported if set.
- ///
- UINT32 ECMD:1;
- ///
- /// [Bit 6] Package thermal management is supported if set.
- ///
- UINT32 PTM:1;
- ///
- /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
- /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
- ///
- UINT32 HWP:1;
- ///
- /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
- ///
- UINT32 HWP_Notification:1;
- ///
- /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
- ///
- UINT32 HWP_Activity_Window:1;
- ///
- /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
- ///
- UINT32 HWP_Energy_Performance_Preference:1;
- ///
- /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
- ///
- UINT32 HWP_Package_Level_Request:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
- /// IA32_THREAD_STALL MSRs are supported if set.
- ///
- UINT32 HDC:1;
- UINT32 Reserved3:18;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_THERMAL_POWER_MANAGEMENT_EAX;
-
-/**
- CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
- #CPUID_THERMAL_POWER_MANAGEMENT.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
- ///
- UINT32 InterruptThresholds:4;
- UINT32 Reserved:28;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_THERMAL_POWER_MANAGEMENT_EBX;
-
-/**
- CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
- #CPUID_THERMAL_POWER_MANAGEMENT.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
- /// and IA32_APERF). The capability to provide a measure of delivered
- /// processor performance (since last reset of the counters), as a percentage
- /// of the expected processor performance when running at the TSC frequency.
- ///
- UINT32 HardwareCoordinationFeedback:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] If this bit is set, then the processor supports performance-energy
- /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
- /// (1B0H).
- ///
- UINT32 PerformanceEnergyBias:1;
- UINT32 Reserved2:28;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_THERMAL_POWER_MANAGEMENT_ECX;
-
-
-/**
- CPUID Structured Extended Feature Flags Enumeration
-
- @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
- @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
-
- @note
- If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
- index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
-
- @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
- @retval EBX Structured Extended Feature Flags described by the type
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
- @retval EBX Structured Extended Feature Flags described by the type
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
- UINT32 SubLeaf;
-
- AsmCpuidEx (
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
- &Eax, NULL, NULL, NULL
- );
- for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
- AsmCpuidEx (
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
- SubLeaf,
- NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
- );
- SubLeaf++;
- } while (SubLeaf <= Eax);
- @endcode
-**/
-#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
-
-///
-/// CPUID Structured Extended Feature Flags Enumeration sub-leaf
-///
-#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
-
-/**
- CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
- #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
- #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
- ///
- UINT32 FSGSBASE:1;
- ///
- /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
- ///
- UINT32 IA32_TSC_ADJUST:1;
- ///
- /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
- /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
- ///
- UINT32 SGX:1;
- ///
- /// [Bit 3] If 1 indicates the processor supports the first group of advanced
- /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
- ///
- UINT32 BMI1:1;
- ///
- /// [Bit 4] Hardware Lock Elision
- ///
- UINT32 HLE:1;
- ///
- /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
- ///
- UINT32 AVX2:1;
- ///
- /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
- ///
- UINT32 FDP_EXCPTN_ONLY:1;
- ///
- /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
- ///
- UINT32 SMEP:1;
- ///
- /// [Bit 8] If 1 indicates the processor supports the second group of
- /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
- /// SARX, SHLX, SHRX)
- ///
- UINT32 BMI2:1;
- ///
- /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
- ///
- UINT32 EnhancedRepMovsbStosb:1;
- ///
- /// [Bit 10] If 1, supports INVPCID instruction for system software that
- /// manages process-context identifiers.
- ///
- UINT32 INVPCID:1;
- ///
- /// [Bit 11] Restricted Transactional Memory
- ///
- UINT32 RTM:1;
- ///
- /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)
- /// capability if 1.
- ///
- UINT32 PQM:1;
- ///
- /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
- ///
- UINT32 DeprecateFpuCsDs:1;
- ///
- /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
- ///
- UINT32 MPX:1;
- ///
- /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)
- /// capability if 1.
- ///
- UINT32 PQE:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
- ///
- UINT32 RDSEED:1;
- ///
- /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
- /// instructions.
- ///
- UINT32 ADX:1;
- ///
- /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
- /// instructions) if 1.
- ///
- UINT32 SMAP:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
- ///
- UINT32 CLFLUSHOPT:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
- /// extensions.
- ///
- UINT32 IntelProcessorTrace:1;
- UINT32 Reserved5:6;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;
-
-/**
- CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
- #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
- #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
- ///
- UINT32 PREFETCHWT1:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] Supports protection keys for user-mode pages if 1.
- ///
- UINT32 PKU:1;
- ///
- /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
- /// RDPKRU/WRPKRU instructions).
- ///
- UINT32 OSPKE:1;
- UINT32 Reserved2:27;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;
-
-
-/**
- CPUID Direct Cache Access Information
-
- @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
-
- @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
- @retval EBX Reserved.
- @retval ECX Reserved.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
-
- AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
- @endcode
-**/
-#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
-
-
-/**
- CPUID Architectural Performance Monitoring
-
- @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
-
- @retval EAX Architectural Performance Monitoring information described by
- the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
- @retval EBX Architectural Performance Monitoring information described by
- the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
- @retval ECX Reserved.
- @retval EDX Architectural Performance Monitoring information described by
- the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
-
- <b>Example usage</b>
- @code
- CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
- CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
- CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
-
- AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
- @endcode
-**/
-#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
-
-/**
- CPUID Architectural Performance Monitoring EAX for CPUID leaf
- #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 7:0] Version ID of architectural performance monitoring.
- ///
- UINT32 ArchPerfMonVerID:8;
- ///
- /// [Bits 15:8] Number of general-purpose performance monitoring counter
- /// per logical processor.
- ///
- /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
- /// block of MSR address space. Each performance event select register is
- /// paired with a corresponding performance counter in the 0C1H address
- /// block.
- ///
- UINT32 PerformanceMonitorCounters:8;
- ///
- /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
- ///
- /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
- /// read operation. On write operations, the lower-order 32 bits of the MSR
- /// may be written with any value, and the high-order bits are sign-extended
- /// from the value of bit 31.
- ///
- UINT32 PerformanceMonitorCounterWidth:8;
- ///
- /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
- /// performance monitoring events.
- ///
- UINT32 EbxBitVectorLength:8;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;
-
-/**
- CPUID Architectural Performance Monitoring EBX for CPUID leaf
- #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Core cycle event not available if 1.
- ///
- UINT32 UnhaltedCoreCycles:1;
- ///
- /// [Bit 1] Instruction retired event not available if 1.
- ///
- UINT32 InstructionsRetired:1;
- ///
- /// [Bit 2] Reference cycles event not available if 1.
- ///
- UINT32 UnhaltedReferenceCycles:1;
- ///
- /// [Bit 3] Last-level cache reference event not available if 1.
- ///
- UINT32 LastLevelCacheReferences:1;
- ///
- /// [Bit 4] Last-level cache misses event not available if 1.
- ///
- UINT32 LastLevelCacheMisses:1;
- ///
- /// [Bit 5] Branch instruction retired event not available if 1.
- ///
- UINT32 BranchInstructionsRetired:1;
- ///
- /// [Bit 6] Branch mispredict retired event not available if 1.
- ///
- UINT32 AllBranchMispredictRetired:1;
- UINT32 Reserved:25;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;
-
-/**
- CPUID Architectural Performance Monitoring EDX for CPUID leaf
- #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 4:0] Number of fixed-function performance counters
- /// (if Version ID > 1).
- ///
- UINT32 FixedFunctionPerformanceCounters:5;
- ///
- /// [Bits 12:5] Bit width of fixed-function performance counters
- /// (if Version ID > 1).
- ///
- UINT32 FixedFunctionPerformanceCounterWidth:8;
- UINT32 Reserved:19;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;
-
-
-/**
- CPUID Extended Topology Information
-
- @note
- Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
- of leaf 0BH is always valid and does not vary with input value in ECX. Output
- value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that
- return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If
- an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
- other input values with ECX > n also return 0 in ECX[15:8].
-
- @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
- @param ECX Level number
-
- @retval EAX Extended topology information described by the type
- CPUID_EXTENDED_TOPOLOGY_EAX.
- @retval EBX Extended topology information described by the type
- CPUID_EXTENDED_TOPOLOGY_EBX.
- @retval ECX Extended topology information described by the type
- CPUID_EXTENDED_TOPOLOGY_ECX.
- @retval EDX x2APIC ID the current logical processor.
-
- <b>Example usage</b>
- @code
- CPUID_EXTENDED_TOPOLOGY_EAX Eax;
- CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
- CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
- UINT32 Edx;
- UINT32 LevelNumber;
-
- LevelNumber = 0;
- do {
- AsmCpuidEx (
- CPUID_EXTENDED_TOPOLOGY, LevelNumber,
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
- );
- LevelNumber++;
- } while (Eax.Bits.ApicIdShift != 0);
- @endcode
-**/
-#define CPUID_EXTENDED_TOPOLOGY 0x0B
-
-/**
- CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
- /// topology ID of the next level type. All logical processors with the
- /// same next level ID share current level.
- ///
- /// @note
- /// Software should use this field (EAX[4:0]) to enumerate processor
- /// topology of the system.
- ///
- UINT32 ApicIdShift:5;
- UINT32 Reserved:27;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_TOPOLOGY_EAX;
-
-/**
- CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Number of logical processors at this level type. The number
- /// reflects configuration as shipped by Intel.
- ///
- /// @note
- /// Software must not use EBX[15:0] to enumerate processor topology of the
- /// system. This value in this field (EBX[15:0]) is only intended for
- /// display/diagnostic purposes. The actual number of logical processors
- /// available to BIOS/OS/Applications may be different from the value of
- /// EBX[15:0], depending on software and platform hardware configurations.
- ///
- UINT32 LogicalProcessors:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_TOPOLOGY_EBX;
-
-/**
- CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Level number. Same value in ECX input.
- ///
- UINT32 LevelNumber:8;
- ///
- /// [Bits 15:8] Level type.
- ///
- /// @note
- /// The value of the "level type" field is not related to level numbers in
- /// any way, higher "level type" values do not mean higher levels.
- ///
- UINT32 LevelType:8;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_TOPOLOGY_ECX;
-
-///
-/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
-///
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
-///
-/// @}
-///
-
-
-/**
- CPUID Extended State Information
-
- @param EAX CPUID_EXTENDED_STATE (0x0D)
- @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
- CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
- CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
- Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
-**/
-#define CPUID_EXTENDED_STATE 0x0D
-
-/**
- CPUID Extended State Information Main Leaf
-
- @param EAX CPUID_EXTENDED_STATE (0x0D)
- @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
-
- @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
- can be set to 1 only if EAX[n] is 1. The format of the extended
- state main leaf is described by the type
- CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
- @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
- area) required by enabled features in XCR0. May be different than
- ECX if some features at the end of the XSAVE save area are not
- enabled.
- @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
- area) of the XSAVE/XRSTOR save area required by all supported
- features in the processor, i.e all the valid bit fields in XCR0.
- @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
- XCR0[n+32] can be set to 1 only if EDX[n] is 1.
-
- <b>Example usage</b>
- @code
- CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
- UINT32 Ebx;
- UINT32 Ecx;
- UINT32 Edx;
-
- AsmCpuidEx (
- CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
- &Eax.Uint32, &Ebx, &Ecx, &Edx
- );
- @endcode
-**/
-#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
-
-/**
- CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
- sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] x87 state.
- ///
- UINT32 x87:1;
- ///
- /// [Bit 1] SSE state.
- ///
- UINT32 SSE:1;
- ///
- /// [Bit 2] AVX state.
- ///
- UINT32 AVX:1;
- ///
- /// [Bits 4:3] MPX state.
- ///
- UINT32 MPX:2;
- ///
- /// [Bits 7:5] AVX-512 state.
- ///
- UINT32 AVX_512:3;
- ///
- /// [Bit 8] Used for IA32_XSS.
- ///
- UINT32 IA32_XSS:1;
- ///
- /// [Bit 9] PKRU state.
- ///
- UINT32 PKRU:1;
- UINT32 Reserved:22;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;
-
-/**
- CPUID Extended State Information Sub Leaf
-
- @param EAX CPUID_EXTENDED_STATE (0x0D)
- @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
-
- @retval EAX The format of the extended state sub-leaf is described by the
- type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
- @retval EBX The size in bytes of the XSAVE area containing all states
- enabled by XCRO | IA32_XSS.
- @retval ECX The format of the extended state sub-leaf is described by the
- type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
- @retval EDX Reports the supported bits of the upper 32 bits of the
- IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
-
- <b>Example usage</b>
- @code
- CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
- UINT32 Ebx;
- CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
- UINT32 Edx;
-
- AsmCpuidEx (
- CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
- &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
- );
- @endcode
-**/
-#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
-
-/**
- CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
- sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] XSAVEOPT is available.
- ///
- UINT32 XSAVEOPT:1;
- ///
- /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
- ///
- UINT32 XSAVEC:1;
- ///
- /// [Bit 2] Supports XGETBV with ECX = 1 if set.
- ///
- UINT32 XGETBV:1;
- ///
- /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
- ///
- UINT32 XSAVES:1;
- UINT32 Reserved:28;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;
-
-/**
- CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
- sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Used for XCR0.
- ///
- UINT32 XCR0:1;
- ///
- /// [Bit 8] PT STate.
- ///
- UINT32 PT:1;
- ///
- /// [Bit 9] Used for XCR0.
- ///
- UINT32 XCR0_1:1;
- UINT32 Reserved:22;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;
-
-/**
- CPUID Extended State Information Size and Offset Sub Leaf
-
- @note
- Leaf 0DH output depends on the initial value in ECX.
- Each sub-leaf index (starting at position 2) is supported if it corresponds to
- a supported bit in either the XCR0 register or the IA32_XSS MSR.
- If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
- n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
- returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
- returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
-
- @param EAX CPUID_EXTENDED_STATE (0x0D)
- @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
- on supported bits in XCR0 or IA32_XSS_MSR.
-
- @retval EAX The size in bytes (from the offset specified in EBX) of the save
- area for an extended state feature associated with a valid
- sub-leaf index, n.
- @retval EBX The offset in bytes of this extended state component's save area
- from the beginning of the XSAVE/XRSTOR area. This field reports
- 0 if the sub-leaf index, n, does not map to a valid bit in the
- XCR0 register.
- @retval ECX The format of the extended state components's save area as
- described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
- This field reports 0 if the sub-leaf index, n, is invalid.
- @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
- otherwise it is reserved.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
- UINT32 Ebx;
- CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
- UINT32 Edx;
- UINTN SubLeaf;
-
- for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
- AsmCpuidEx (
- CPUID_EXTENDED_STATE, SubLeaf,
- &Eax, &Ebx, &Ecx.Uint32, &Edx
- );
- }
- @endcode
-**/
-#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
-
-/**
- CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
- sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
- /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
- /// in XCR0.
- ///
- UINT32 XSS:1;
- ///
- /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
- /// this extended state component located on the next 64-byte boundary
- /// following the preceding state component (otherwise, it is located
- /// immediately following the preceding state component).
- ///
- UINT32 Compacted:1;
- UINT32 Reserved:30;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;
-
-
-/**
- CPUID Platform QoS Monitoring Information
-
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
- @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).
-
-**/
-#define CPUID_PLATFORM_QOS_MONITORING 0x0F
-
-/**
- CPUID Platform QoS Monitoring Information Enumeration Sub-leaf
-
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
- @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)
-
- @retval EAX Reserved.
- @retval EBX Maximum range (zero-based) of RMID within this physical
- processor of all types.
- @retval ECX Reserved.
- @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the
- type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.
-
- <b>Example usage</b>
- @code
- UINT32 Ebx;
- CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
-
- AsmCpuidEx (
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,
- NULL, &Ebx, NULL, &Edx.Uint32
- );
- @endcode
-**/
-#define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00
-
-/**
- CPUID Platform QoS Monitoring Information EDX for CPUID leaf
- #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
- #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.
- ///
- UINT32 L3CacheQosEnforcement:1;
- UINT32 Reserved2:30;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;
-
-/**
- CPUID Platform QoS Monitoring Information Capability Sub-leaf
-
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
- @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)
-
- @retval EAX Reserved.
- @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
- @retval ECX Maximum range (zero-based) of RMID of this resource type.
- @retval EDX L3 Cache QoS Monitoring Capability information described by the
- type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.
-
- <b>Example usage</b>
- @code
- UINT32 Ebx;
- UINT32 Ecx;
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;
-
- AsmCpuidEx (
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,
- NULL, &Ebx, &Ecx, &Edx.Uint32
- );
- @endcode
-**/
-#define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01
-
-/**
- CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf
- #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
- #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Supports L3 occupancy monitoring if 1.
- ///
- UINT32 L3CacheOccupancyMonitoring:1;
- UINT32 Reserved:31;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;
-
-
-/**
- CPUID Platform QoS Enforcement Information
-
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).
- Additional sub leafs 1..n based in RESID from sub leaf 0x00.
-**/
-#define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10
-
-/**
- CPUID Platform QoS Enforcement Information
-
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
-
- @retval EAX Reserved.
- @retval EBX L3 Cache QoS Enforcement information described by the
- type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.
- @retval ECX Reserved.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;
-
- AsmCpuidEx (
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,
- NULL, &Ebx.Uint32, NULL, NULL
- );
- @endcode
-**/
-#define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00
-
-/**
- CPUID Platform QoS Enforcement Information EBX for CPUID leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.
- ///
- UINT32 L3CacheQosEnforcement:1;
- UINT32 Reserved2:30;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;
-
-
-/**
- CPUID Platform QoS Enforcement Information
-
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)
- Additional sub leafs 1..n based in RESID from sub leaf 0x00.
-
- @retval EAX RESID L3 Cache3 QoS Enforcement information described by the
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.
- @retval EBX Bit-granular map of isolation/contention of allocation units.
- @retval ECX RESID L3 Cache3 QoS Enforcement information described by the
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.
- @retval EDX RESID L3 Cache3 QoS Enforcement information described by the
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.
-
- <b>Example usage</b>
- @code
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;
- UINT32 Ebx;
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;
-
- AsmCpuidEx (
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,
- &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
- );
- @endcode
-**/
-#define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01
-
-/**
- CPUID Platform QoS Enforcement Information EAX for CPUID leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.
- ///
- UINT32 CapacityLength:4;
- UINT32 Reserved:28;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;
-
-/**
- CPUID Platform QoS Enforcement Information ECX for CPUID leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Updates of COS should be infrequent if 1.
- ///
- UINT32 CosUpdatesInfrequent:1;
- ///
- /// [Bit 2] Code and Data Prioritization Technology supported if 1.
- ///
- UINT32 CodeDataPrioritization:1;
- UINT32 Reserved2:29;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;
-
-/**
- CPUID Platform QoS Enforcement Information EDX for CPUID leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Highest COS number supported for this ResID.
- ///
- UINT32 HighestCosNumber:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;
-
-
-/**
- Intel SGX resource capability and configuration.
- See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
-
- If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
- CPUID with EAX=12H on Intel SGX resource capability and configuration.
-
- @param EAX CPUID_INTEL_SGX (0x12)
- @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
- CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
- Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
- until the sub-leaf type is invalid.
-
-**/
-#define CPUID_INTEL_SGX 0x12
-
-/**
- Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
- Enumerates Intel SGX capability, including enclave instruction opcode support.
-
- @param EAX CPUID_INTEL_SGX (0x12)
- @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
-
- @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
- described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
- @retval EBX MISCSELECT: Reports the bit vector of supported extended features
- that can be written to the MISC region of the SSA.
- @retval ECX Reserved.
- @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
- described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
-
- <b>Example usage</b>
- @code
- CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
- UINT32 Ebx;
- CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
-
- AsmCpuidEx (
- CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
- &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
- );
- @endcode
-**/
-#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
-
-/**
- Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
- sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
- ///
- UINT32 SGX1:1;
- ///
- /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
- ///
- UINT32 SGX2:1;
- UINT32 Reserved:30;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;
-
-/**
- Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
- sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
- /// when not in 64-bit mode.
- ///
- UINT32 MaxEnclaveSize_Not64:8;
- ///
- /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
- /// when operating in 64-bit mode.
- ///
- UINT32 MaxEnclaveSize_64:8;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;
-
-
-/**
- Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
- Enumerates Intel SGX capability of processor state configuration and enclave
- configuration in the SECS structure.
-
- @param EAX CPUID_INTEL_SGX (0x12)
- @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
-
- @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
- set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
- only if EAX[n] is 1, where n < 32.
- @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
- set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
- only if EBX[n] is 1, where n < 32.
- @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
- set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
- only if ECX[n] is 1, where n < 32.
- @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
- set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
- only if EDX[n] is 1, where n < 32.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
- UINT32 Ebx;
- UINT32 Ecx;
- UINT32 Edx;
-
- AsmCpuidEx (
- CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
- &Eax, &Ebx, &Ecx, &Edx
- );
- @endcode
-**/
-#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
-
-
-/**
- Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
- Enumerates available EPC resources.
-
- @param EAX CPUID_INTEL_SGX (0x12)
- @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
-
- @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
- Resources is described by the type
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
- @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
- Resources is described by the type
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
- @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
- Resources is described by the type
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
- @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
- Resources is described by the type
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
-
- <b>Example usage</b>
- @code
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
- CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
-
- AsmCpuidEx (
- CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
- );
- @endcode
-**/
-#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
-
-/**
- Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
- leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 3:0] Sub-leaf-type encoding.
- /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
- /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
- /// in EBX:EAX and EDX:ECX.
- /// All other encoding are reserved.
- ///
- UINT32 SubLeafType:4;
- UINT32 Reserved:8;
- ///
- /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
- /// the base of the EPC section.
- ///
- UINT32 LowAddressOfEpcSection:20;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;
-
-/**
- Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
- leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
- /// the base of the EPC section.
- ///
- UINT32 HighAddressOfEpcSection:20;
- UINT32 Reserved:12;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;
-
-/**
- Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
- leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 3:0] The EPC section encoding.
- /// 0000b: Not valid.
- /// 0001b: The EPC section is confidentiality, integrity and replay protected.
- /// All other encoding are reserved.
- ///
- UINT32 EpcSection:4;
- UINT32 Reserved:8;
- ///
- /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
- /// corresponding EPC section within the Processor Reserved Memory.
- ///
- UINT32 LowSizeOfEpcSection:20;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;
-
-/**
- Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
- leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
- /// corresponding EPC section within the Processor Reserved Memory.
- ///
- UINT32 HighSizeOfEpcSection:20;
- UINT32 Reserved:12;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;
-
-
-/**
- CPUID Intel Processor Trace Information
-
- @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
- @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
- CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
-
-**/
-#define CPUID_INTEL_PROCESSOR_TRACE 0x14
-
-/**
- CPUID Intel Processor Trace Information Main Leaf
-
- @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
- @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
-
- @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
- @retval EBX Returns Intel processor trace information described by the
- type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
- @retval ECX Returns Intel processor trace information described by the
- type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
- CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
- CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
-
- AsmCpuidEx (
- CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
- &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
- );
- @endcode
-**/
-#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
-
-/**
- CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
- sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
- /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
- ///
- UINT32 Cr3Filter:1;
- ///
- /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate
- /// Mode.
- ///
- UINT32 ConfigurablePsb:1;
- ///
- /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,
- /// and preservation of Intel PT MSRs across warm reset.
- ///
- UINT32 IpTraceStopFiltering:1;
- ///
- /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of
- /// COFI-based packets.
- ///
- UINT32 Mtc:1;
- UINT32 Reserved:28;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;
-
-/**
- CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
- sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
- /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
- /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
- ///
- UINT32 RTIT:1;
- ///
- /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
- /// the maximum allowed by the MaskOrTableOffset field of
- /// IA32_RTIT_OUTPUT_MASK_PTRS.
- ///
- UINT32 ToPA:1;
- ///
- /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.
- ///
- UINT32 SingleRangeOutput:1;
- ///
- /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.
- ///
- UINT32 TraceTransportSubsystem:1;
- UINT32 Reserved:27;
- ///
- /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP
- /// values, which include the CS base component.
- ///
- UINT32 LIP:1;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;
-
-
-/**
- CPUID Intel Processor Trace Information Sub-leaf
-
- @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
- @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
-
- @retval EAX Returns Intel processor trace information described by the
- type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
- @retval EBX Returns Intel processor trace information described by the
- type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
- @retval ECX Reserved.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- UINT32 MaximumSubLeaf;
- UINT32 SubLeaf;
- CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
- CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
-
- AsmCpuidEx (
- CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
- &MaximumSubLeaf, NULL, NULL, NULL
- );
-
- for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
- AsmCpuidEx (
- CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
- &Eax.Uint32, &Ebx.Uint32, NULL, NULL
- );
- }
- @endcode
-**/
-#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
-
-/**
- CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
- sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Number of configurable Address Ranges for filtering.
- ///
- UINT32 ConfigurableAddressRanges:3;
- UINT32 Reserved:13;
- ///
- /// [Bits 31:16] Bitmap of supported MTC period encodings
- ///
- UINT32 MtcPeriodEncodings:16;
-
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;
-
-/**
- CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
- sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
- ///
- UINT32 CycleThresholdEncodings:16;
- ///
- /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
- ///
- UINT32 PsbFrequencyEncodings:16;
-
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;
-
-
-/**
- CPUID Time Stamp Counter Information
-
- @note
- If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
- EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
- crystal clock frequency.
- "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
- The core crystal clock may differ from the reference clock, bus clock, or core
- clock frequencies.
-
- @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
-
- @retval EAX An unsigned integer which is the denominator of the
- TSC/"core crystal clock" ratio
- @retval EBX An unsigned integer which is the numerator of the
- TSC/"core crystal clock" ratio.
- @retval ECX Reserved.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
- UINT32 Ebx;
-
- AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);
- @endcode
-**/
-#define CPUID_TIME_STAMP_COUNTER 0x15
-
-
-/**
- CPUID Processor Frequency Information
-
- @note
- Data is returned from this interface in accordance with the processor's
- specification and does not reflect actual values. Suitable use of this data
- includes the display of processor information in like manner to the processor
- brand string and for determining the appropriate range to use when displaying
- processor information e.g. frequency history graphs. The returned information
- should not be used for any other purpose as the returned information does not
- accurately correlate to information / counters returned by other processor
- interfaces. While a processor may support the Processor Frequency Information
- leaf, fields that return a value of zero are not supported.
-
- @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
-
- @retval EAX Returns processor base frequency information described by the
- type CPUID_PROCESSOR_FREQUENCY_EAX.
- @retval EBX Returns maximum frequency information described by the type
- CPUID_PROCESSOR_FREQUENCY_EBX.
- @retval ECX Returns bus frequency information described by the type
- CPUID_PROCESSOR_FREQUENCY_ECX.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- CPUID_PROCESSOR_FREQUENCY_EAX Eax;
- CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
- CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
-
- AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
- @endcode
-**/
-#define CPUID_PROCESSOR_FREQUENCY 0x16
-
-/**
- CPUID Processor Frequency Information EAX for CPUID leaf
- #CPUID_PROCESSOR_FREQUENCY.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Processor Base Frequency (in MHz).
- ///
- UINT32 ProcessorBaseFrequency:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PROCESSOR_FREQUENCY_EAX;
-
-/**
- CPUID Processor Frequency Information EBX for CPUID leaf
- #CPUID_PROCESSOR_FREQUENCY.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Maximum Frequency (in MHz).
- ///
- UINT32 MaximumFrequency:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PROCESSOR_FREQUENCY_EBX;
-
-/**
- CPUID Processor Frequency Information ECX for CPUID leaf
- #CPUID_PROCESSOR_FREQUENCY.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
- ///
- UINT32 BusFrequency:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_PROCESSOR_FREQUENCY_ECX;
-
-
-/**
- CPUID SoC Vendor Information
-
- @param EAX CPUID_SOC_VENDOR (0x17)
- @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
- CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
- CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
- CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
-
- @note
- Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
- is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
- Vendor Brand String is constructed by concatenating in ascending order of
- EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
-
-**/
-#define CPUID_SOC_VENDOR 0x17
-
-/**
- CPUID SoC Vendor Information
-
- @param EAX CPUID_SOC_VENDOR (0x17)
- @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
-
- @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
- sub-leaf in leaf 17H.
- @retval EBX Returns SoC Vendor information described by the type
- CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
- @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
- projects.
- @retval EDX Stepping ID. A unique number within an SOC project that an SOC
- vendor assigns.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
- CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
- UINT32 Ecx;
- UINT32 Edx;
-
- AsmCpuidEx (
- CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
- &Eax, &Ebx.Uint32, &Ecx, &Edx
- );
- @endcode
-**/
-#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
-
-/**
- CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
- #CPUID_SOC_VENDOR_MAIN_LEAF.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] SOC Vendor ID.
- ///
- UINT32 SocVendorId:16;
- ///
- /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
- /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
- /// assigned by Intel.
- ///
- UINT32 IsVendorScheme:1;
- UINT32 Reserved:15;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;
-
-/**
- CPUID SoC Vendor Information
-
- @param EAX CPUID_SOC_VENDOR (0x17)
- @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
-
- @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
-
- <b>Example usage</b>
- @code
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
-
- AsmCpuidEx (
- CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
- );
- @endcode
-**/
-#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
-
-/**
- CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
- #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
-**/
-typedef union {
- ///
- /// 4 UTF-8 characters of Soc Vendor Brand String
- ///
- CHAR8 BrandString[4];
- ///
- /// All fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_SOC_VENDOR_BRAND_STRING_DATA;
-
-/**
- CPUID SoC Vendor Information
-
- @param EAX CPUID_SOC_VENDOR (0x17)
- @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
-
- @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
-
- <b>Example usage</b>
- @code
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
-
- AsmCpuidEx (
- CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
- );
- @endcode
-**/
-#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
-
-/**
- CPUID SoC Vendor Information
-
- @param EAX CPUID_SOC_VENDOR (0x17)
- @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
-
- @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
- @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
- CPUID_SOC_VENDOR_BRAND_STRING_DATA.
-
- <b>Example usage</b>
- @code
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
- CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
-
- AsmCpuidEx (
- CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
- &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
- );
- @endcode
-**/
-#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
-
-
-/**
- CPUID Extended Function
-
- @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
-
- @retval EAX Maximum Input Value for Extended Function CPUID Information.
- @retval EBX Reserved.
- @retval ECX Reserved.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
-
- AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
- @endcode
-**/
-#define CPUID_EXTENDED_FUNCTION 0x80000000
-
-
-/**
- CPUID Extended Processor Signature and Feature Bits
-
- @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
-
- @retval EAX CPUID_EXTENDED_CPU_SIG.
- @retval EBX Reserved.
- @retval ECX Extended Processor Signature and Feature Bits information
- described by the type CPUID_EXTENDED_CPU_SIG_ECX.
- @retval EDX Extended Processor Signature and Feature Bits information
- described by the type CPUID_EXTENDED_CPU_SIG_EDX.
-
- <b>Example usage</b>
- @code
- UINT32 Eax;
- CPUID_EXTENDED_CPU_SIG_ECX Ecx;
- CPUID_EXTENDED_CPU_SIG_EDX Edx;
-
- AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
- @endcode
-**/
-#define CPUID_EXTENDED_CPU_SIG 0x80000001
-
-/**
- CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
- #CPUID_EXTENDED_CPU_SIG.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] LAHF/SAHF available in 64-bit mode.
- ///
- UINT32 LAHF_SAHF:1;
- UINT32 Reserved1:4;
- ///
- /// [Bit 5] LZCNT.
- ///
- UINT32 LZCNT:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 8] PREFETCHW.
- ///
- UINT32 PREFETCHW:1;
- UINT32 Reserved3:23;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_CPU_SIG_ECX;
-
-/**
- CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
- #CPUID_EXTENDED_CPU_SIG.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:11;
- ///
- /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
- ///
- UINT32 SYSCALL_SYSRET:1;
- UINT32 Reserved2:8;
- ///
- /// [Bit 20] Execute Disable Bit available.
- ///
- UINT32 NX:1;
- UINT32 Reserved3:5;
- ///
- /// [Bit 26] 1-GByte pages are available if 1.
- ///
- UINT32 Page1GB:1;
- ///
- /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
- ///
- UINT32 RDTSCP:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 29] Intel(R) 64 Architecture available if 1.
- ///
- UINT32 LM:1;
- UINT32 Reserved5:2;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_CPU_SIG_EDX;
-
-
-/**
- CPUID Processor Brand String
-
- @param EAX CPUID_BRAND_STRING1 (0x80000002)
-
- @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
- @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
- @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
- @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
-
- <b>Example usage</b>
- @code
- CPUID_BRAND_STRING_DATA Eax;
- CPUID_BRAND_STRING_DATA Ebx;
- CPUID_BRAND_STRING_DATA Ecx;
- CPUID_BRAND_STRING_DATA Edx;
-
- AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
- @endcode
-**/
-#define CPUID_BRAND_STRING1 0x80000002
-
-/**
- CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
- #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
-**/
-typedef union {
- ///
- /// 4 ASCII characters of Processor Brand String
- ///
- CHAR8 BrandString[4];
- ///
- /// All fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_BRAND_STRING_DATA;
-
-/**
- CPUID Processor Brand String
-
- @param EAX CPUID_BRAND_STRING2 (0x80000003)
-
- @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
- @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
- @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
- @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
-
- <b>Example usage</b>
- @code
- CPUID_BRAND_STRING_DATA Eax;
- CPUID_BRAND_STRING_DATA Ebx;
- CPUID_BRAND_STRING_DATA Ecx;
- CPUID_BRAND_STRING_DATA Edx;
-
- AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
- @endcode
-**/
-#define CPUID_BRAND_STRING2 0x80000003
-
-/**
- CPUID Processor Brand String
-
- @param EAX CPUID_BRAND_STRING3 (0x80000004)
-
- @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
- @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
- @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
- @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
-
- <b>Example usage</b>
- @code
- CPUID_BRAND_STRING_DATA Eax;
- CPUID_BRAND_STRING_DATA Ebx;
- CPUID_BRAND_STRING_DATA Ecx;
- CPUID_BRAND_STRING_DATA Edx;
-
- AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
- @endcode
-**/
-#define CPUID_BRAND_STRING3 0x80000004
-
-
-/**
- CPUID Extended Cache information
-
- @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
-
- @retval EAX Reserved.
- @retval EBX Reserved.
- @retval ECX Extended cache information described by the type
- CPUID_EXTENDED_CACHE_INFO_ECX.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
-
- AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
- @endcode
-**/
-#define CPUID_EXTENDED_CACHE_INFO 0x80000006
-
-/**
- CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Cache line size in bytes.
- ///
- UINT32 CacheLineSize:8;
- UINT32 Reserved:4;
- ///
- /// [Bits 15:12] L2 Associativity field. Supported values are in the range
- /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
- /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
- ///
- UINT32 L2Associativity:4;
- ///
- /// [Bits 31:16] Cache size in 1K units.
- ///
- UINT32 CacheSize:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_CACHE_INFO_ECX;
-
-///
-/// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
-///
-#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
-#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
-#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
-#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
-#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
-#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
-#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
-///
-/// @}
-///
-
-/**
- CPUID Extended Time Stamp Counter information
-
- @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
-
- @retval EAX Reserved.
- @retval EBX Reserved.
- @retval ECX Reserved.
- @retval EDX Extended time stamp counter (TSC) information described by the
- type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
-
- <b>Example usage</b>
- @code
- CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
-
- AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
- @endcode
-**/
-#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
-
-/**
- CPUID Extended Time Stamp Counter information EDX for CPUID leaf
- #CPUID_EXTENDED_TIME_STAMP_COUNTER.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bit 8] Invariant TSC available if 1.
- ///
- UINT32 InvariantTsc:1;
- UINT32 Reserved2:23;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;
-
-
-/**
- CPUID Linear Physical Address Size
-
- @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
-
- @retval EAX Linear/Physical Address Size described by the type
- CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
- @retval EBX Reserved.
- @retval ECX Reserved.
- @retval EDX Reserved.
-
- <b>Example usage</b>
- @code
- CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
-
- AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
- @endcode
-**/
-#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
-
-/**
- CPUID Linear Physical Address Size EAX for CPUID leaf
- #CPUID_VIR_PHY_ADDRESS_SIZE.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Number of physical address bits.
- ///
- /// @note
- /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
- /// number supported should come from this field.
- ///
- UINT32 PhysicalAddressBits:8;
- ///
- /// [Bits 15:8] Number of linear address bits.
- ///
- UINT32 LinearAddressBits:8;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
-} CPUID_VIR_PHY_ADDRESS_SIZE_EAX;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h deleted file mode 100644 index 346cce6756..0000000000 --- a/UefiCpuPkg/Include/Register/LocalApic.h +++ /dev/null @@ -1,207 +0,0 @@ -/** @file
- IA32 Local APIC Definitions.
-
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __LOCAL_APIC_H__
-#define __LOCAL_APIC_H__
-
-//
-// Definitions for IA32 architectural MSRs
-//
-#define MSR_IA32_APIC_BASE_ADDRESS 0x1B
-
-//
-// Definition for Local APIC registers and related values
-//
-#define XAPIC_ID_OFFSET 0x20
-#define XAPIC_VERSION_OFFSET 0x30
-#define XAPIC_EOI_OFFSET 0x0b0
-#define XAPIC_ICR_DFR_OFFSET 0x0e0
-#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
-#define XAPIC_ICR_LOW_OFFSET 0x300
-#define XAPIC_ICR_HIGH_OFFSET 0x310
-#define XAPIC_LVT_TIMER_OFFSET 0x320
-#define XAPIC_LVT_LINT0_OFFSET 0x350
-#define XAPIC_LVT_LINT1_OFFSET 0x360
-#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
-#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
-#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
-
-#define X2APIC_MSR_BASE_ADDRESS 0x800
-#define X2APIC_MSR_ICR_ADDRESS 0x830
-
-#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
-#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
-#define LOCAL_APIC_DELIVERY_MODE_SMI 2
-#define LOCAL_APIC_DELIVERY_MODE_NMI 4
-#define LOCAL_APIC_DELIVERY_MODE_INIT 5
-#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
-#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
-
-#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
-#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
-#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
-#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
-
-typedef union {
- struct {
- UINT32 Reserved0:8; ///< Reserved.
- UINT32 Bsp:1; ///< Processor is BSP.
- UINT32 Reserved1:1; ///< Reserved.
- UINT32 Extd:1; ///< Enable x2APIC mode.
- UINT32 En:1; ///< xAPIC global enable/disable.
- UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.
- UINT32 ApicBaseHigh:32;
- } Bits;
- UINT64 Uint64;
-} MSR_IA32_APIC_BASE;
-
-//
-// Local APIC Version Register.
-//
-typedef union {
- struct {
- UINT32 Version:8; ///< The version numbers of the local APIC.
- UINT32 Reserved0:8; ///< Reserved.
- UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.
- UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.
- UINT32 Reserved1:7; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_VERSION;
-
-//
-// Low half of Interrupt Command Register (ICR).
-//
-typedef union {
- struct {
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.
- UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.
- UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.
- UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
- UINT32 Reserved0:1; ///< Reserved.
- UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
- UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
- UINT32 Reserved1:2; ///< Reserved.
- UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.
- UINT32 Reserved2:12; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_ICR_LOW;
-
-//
-// High half of Interrupt Command Register (ICR)
-//
-typedef union {
- struct {
- UINT32 Reserved0:24; ///< Reserved.
- UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.
- } Bits;
- UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
-} LOCAL_APIC_ICR_HIGH;
-
-//
-// Spurious-Interrupt Vector Register (SVR)
-//
-typedef union {
- struct {
- UINT32 SpuriousVector:8; ///< Spurious Vector.
- UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.
- UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.
- UINT32 Reserved0:2; ///< Reserved.
- UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.
- UINT32 Reserved1:19; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_SVR;
-
-//
-// Divide Configuration Register (DCR)
-//
-typedef union {
- struct {
- UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.
- UINT32 Reserved0:1; ///< Always 0.
- UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.
- UINT32 Reserved1:28; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_DCR;
-
-//
-// LVT Timer Register
-//
-typedef union {
- struct {
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.
- UINT32 Reserved0:4; ///< Reserved.
- UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
- UINT32 Reserved1:3; ///< Reserved.
- UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
- UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.
- UINT32 Reserved2:14; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_LVT_TIMER;
-
-//
-// LVT LINT0/LINT1 Register
-//
-typedef union {
- struct {
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.
- UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
- UINT32 Reserved0:1; ///< Reserved.
- UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
- UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.
- UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
- UINT32 TriggerMode:1; ///< 0:edge, 1:level.
- UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
- UINT32 Reserved1:15; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_LVT_LINT;
-
-//
-// MSI Address Register
-//
-typedef union {
- struct {
- UINT32 Reserved0:2; ///< Reserved
- UINT32 DestinationMode:1; ///< Specifies the Destination Mode.
- UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.
- UINT32 Reserved1:8; ///< Reserved.
- UINT32 DestinationId:8; ///< Specifies the Destination ID.
- UINT32 BaseAddress:12; ///< Must be 0FEEH
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_MSI_ADDRESS;
-
-//
-// MSI Address Register
-//
-typedef union {
- struct {
- UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH
- UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
- UINT32 Reserved0:3; ///< Reserved.
- UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
- UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.
- UINT32 Reserved1:16; ///< Reserved.
- UINT32 Reserved2:32; ///< Reserved.
- } Bits;
- UINT64 Uint64;
-} LOCAL_APIC_MSI_DATA;
-
-#endif
-
diff --git a/UefiCpuPkg/Include/Register/Msr.h b/UefiCpuPkg/Include/Register/Msr.h deleted file mode 100644 index ffa6d4416a..0000000000 --- a/UefiCpuPkg/Include/Register/Msr.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file
- MSR Definitions.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
-
-**/
-
-#ifndef __MSR_H__
-#define __MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-#include <Register/Msr/Core2Msr.h>
-#include <Register/Msr/AtomMsr.h>
-#include <Register/Msr/SilvermontMsr.h>
-#include <Register/Msr/NehalemMsr.h>
-#include <Register/Msr/Xeon5600Msr.h>
-#include <Register/Msr/XeonE7Msr.h>
-#include <Register/Msr/SandyBridgeMsr.h>
-#include <Register/Msr/IvyBridgeMsr.h>
-#include <Register/Msr/HaswellMsr.h>
-#include <Register/Msr/HaswellEMsr.h>
-#include <Register/Msr/BroadwellMsr.h>
-#include <Register/Msr/XeonDMsr.h>
-#include <Register/Msr/SkylakeMsr.h>
-#include <Register/Msr/XeonPhiMsr.h>
-#include <Register/Msr/Pentium4Msr.h>
-#include <Register/Msr/CoreMsr.h>
-#include <Register/Msr/PentiumMMsr.h>
-#include <Register/Msr/P6Msr.h>
-#include <Register/Msr/PentiumMsr.h>
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h deleted file mode 100644 index 01e0d9a7a6..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h +++ /dev/null @@ -1,878 +0,0 @@ -/** @file
- MSR Definitions for the Intel(R) Atom(TM) Processor Family.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3.
-
-**/
-
-#ifndef __ATOM_MSR_H__
-#define __ATOM_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Shared. Model Specific Platform ID (R).
-
- @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_ATOM_PLATFORM_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
- @endcode
-**/
-#define MSR_ATOM_PLATFORM_ID 0x00000017
-
-/**
- MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
- ///
- UINT32 MaximumQualifiedRatio:5;
- UINT32 Reserved2:19;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_ATOM_PLATFORM_ID_REGISTER;
-
-
-/**
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
- processor features; (R) indicates current processor configuration.
-
- @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
- AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
- @endcode
-**/
-#define MSR_ATOM_EBL_CR_POWERON 0x0000002A
-
-/**
- MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 DataErrorCheckingEnable:1;
- ///
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 ResponseErrorCheckingEnable:1;
- ///
- /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
- ///
- UINT32 AERR_DriveEnable:1;
- ///
- /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
- /// Disabled Always 0.
- ///
- UINT32 BERR_Enable:1;
- UINT32 Reserved2:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
- ///
- UINT32 BINIT_DriverEnable:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 ExecuteBIST:1;
- ///
- /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 AERR_ObservationEnabled:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 BINIT_ObservationEnabled:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
- ///
- UINT32 ResetVector:1;
- UINT32 Reserved7:1;
- ///
- /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
- ///
- UINT32 APICClusterID:2;
- UINT32 Reserved8:2;
- ///
- /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
- ///
- UINT32 SymmetricArbitrationID:2;
- ///
- /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
- ///
- UINT32 IntegerBusFrequencyRatio:5;
- UINT32 Reserved9:5;
- UINT32 Reserved10:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_ATOM_EBL_CR_POWERON_REGISTER;
-
-
-/**
- Unique. Last Branch Record 0 From IP (R/W) One of eight pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the source instruction for one of the last eight
- branches, exceptions, or interrupts taken by the processor. See also: -
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
- Interrupt, and Exception Recording (Pentium M Processors).".
-
- @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
- AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
-#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
-#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
-#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
-#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
-#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
-#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
-#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
-/// @}
-
-
-/**
- Unique. Last Branch Record 0 To IP (R/W) One of eight pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction for one of the last eight
- branches, exceptions, or interrupts taken by the processor.
-
- @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
- AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
-#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
-#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
-#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
-#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
-#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
-#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
-#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
-/// @}
-
-
-/**
- Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
- bus clock speed for processors based on Intel Atom microarchitecture:.
-
- @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_ATOM_FSB_FREQ_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
- @endcode
-**/
-#define MSR_ATOM_FSB_FREQ 0x000000CD
-
-/**
- MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] - Scalable Bus Speed
- ///
- /// Atom Processor Family
- /// ---------------------
- /// 111B: 083 MHz (FSB 333)
- /// 101B: 100 MHz (FSB 400)
- /// 001B: 133 MHz (FSB 533)
- /// 011B: 167 MHz (FSB 667)
- ///
- /// 133.33 MHz should be utilized if performing calculation with
- /// System Bus Speed when encoding is 001B.
- /// 166.67 MHz should be utilized if performing calculation with
- /// System Bus Speed when
- /// encoding is 011B.
- ///
- UINT32 ScalableBusSpeed:3;
- UINT32 Reserved1:29;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_ATOM_FSB_FREQ_REGISTER;
-
-
-/**
- Shared.
-
- @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
- AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
- @endcode
-**/
-#define MSR_ATOM_BBL_CR_CTL3 0x0000011E
-
-/**
- MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
- /// Indicates if the L2 is hardware-disabled.
- ///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:7;
- ///
- /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
- /// Disabled (default) Until this bit is set the processor will not
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
- ///
- UINT32 L2Enabled:1;
- UINT32 Reserved2:14;
- ///
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
- ///
- UINT32 L2NotPresent:1;
- UINT32 Reserved3:8;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_ATOM_BBL_CR_CTL3_REGISTER;
-
-
-/**
- Shared.
-
- @param ECX MSR_ATOM_PERF_STATUS (0x00000198)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_ATOM_PERF_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
- AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_ATOM_PERF_STATUS 0x00000198
-
-/**
- MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Current Performance State Value.
- ///
- UINT32 CurrentPerformanceStateValue:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:8;
- ///
- /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
- /// configured for the processor.
- ///
- UINT32 MaximumBusRatio:5;
- UINT32 Reserved3:19;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_ATOM_PERF_STATUS_REGISTER;
-
-
-/**
- Shared.
-
- @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_ATOM_THERM2_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
- AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_ATOM_THERM2_CTL 0x0000019D
-
-/**
- MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
- ///
- UINT32 TM_SELECT:1;
- UINT32 Reserved2:15;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_ATOM_THERM2_CTL_REGISTER;
-
-
-/**
- Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Fast-Strings Enable See Table 35-2.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
- /// the processor to indicate a pending break event within the processor 0
- /// = Indicates compatible FERR# signaling behavior This bit must be set
- /// to 1 to support XAPIC interrupt model usage.
- ///
- UINT32 FERR:1;
- ///
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
- ///
- UINT32 PEBS:1;
- ///
- /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
- /// thermal sensor indicates that the die temperature is at the
- /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
- /// TM2 will reduce the bus to core ratio and voltage according to the
- /// value last written to MSR_THERM2_CTL bits 15:0.
- /// When this bit is clear (0, default), the processor does not change
- /// the VID signals or the bus to core ratio when the processor enters a
- /// thermally managed state. The BIOS must enable this feature if the
- /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
- /// not set, this feature is not supported and BIOS must not alter the
- /// contents of the TM2 bit location. The processor is operating out of
- /// specification if both this bit and the TM1 bit are set to 0.
- ///
- UINT32 TM2:1;
- UINT32 Reserved5:2;
- ///
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 EIST:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
- ///
- UINT32 MONITOR:1;
- UINT32 Reserved7:1;
- ///
- /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
- /// (R/WO) When set, this bit causes the following bits to become
- /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
- /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
- /// be set before an Enhanced Intel SpeedStep Technology transition is
- /// requested. This bit is cleared on reset.
- ///
- UINT32 EISTLock:1;
- UINT32 Reserved8:1;
- ///
- /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved9:8;
- UINT32 Reserved10:2;
- ///
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
- ///
- UINT32 XD:1;
- UINT32 Reserved11:29;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
- that points to the MSR containing the most recent branch record. See
- MSR_LASTBRANCH_0_FROM_IP (at 40H).
-
- @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
- last branch instruction that the processor executed prior to the last
- exception that was generated or the last interrupt that was handled.
-
- @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_ATOM_LER_FROM_LIP 0x000001DD
-
-
-/**
- Unique. Last Exception Record To Linear IP (R) This area contains a pointer
- to the target of the last branch instruction that the processor executed
- prior to the last exception that was generated or the last interrupt that
- was handled.
-
- @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
- @endcode
-**/
-#define MSR_ATOM_LER_TO_LIP 0x000001DE
-
-
-/**
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_ATOM_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
-**/
-#define MSR_ATOM_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
- (PEBS).".
-
- @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_ATOM_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
- ///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_ATOM_PEBS_ENABLE_REGISTER;
-
-
-/**
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_ATOM_MC3_CTL (0x0000040C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_CTL);
- AsmWriteMsr64 (MSR_ATOM_MC3_CTL, Msr);
- @endcode
-**/
-#define MSR_ATOM_MC3_CTL 0x0000040C
-
-
-/**
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_ATOM_MC3_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_STATUS);
- AsmWriteMsr64 (MSR_ATOM_MC3_STATUS, Msr);
- @endcode
-**/
-#define MSR_ATOM_MC3_STATUS 0x0000040D
-
-
-/**
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC3_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_ATOM_MC3_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_ADDR);
- AsmWriteMsr64 (MSR_ATOM_MC3_ADDR, Msr);
- @endcode
-**/
-#define MSR_ATOM_MC3_ADDR 0x0000040E
-
-
-/**
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_ATOM_MC4_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_CTL);
- AsmWriteMsr64 (MSR_ATOM_MC4_CTL, Msr);
- @endcode
-**/
-#define MSR_ATOM_MC4_CTL 0x00000410
-
-
-/**
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_ATOM_MC4_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_STATUS);
- AsmWriteMsr64 (MSR_ATOM_MC4_STATUS, Msr);
- @endcode
-**/
-#define MSR_ATOM_MC4_STATUS 0x00000411
-
-
-/**
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC4_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_ATOM_MC4_ADDR (0x00000412)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_ADDR);
- AsmWriteMsr64 (MSR_ATOM_MC4_ADDR, Msr);
- @endcode
-**/
-#define MSR_ATOM_MC4_ADDR 0x00000412
-
-
-/**
- Package. Package C2 Residency Note: C-state values are processor specific
- C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
- C-States. Package. Package C2 Residency Counter. (R/O) Time that this
- package is in processor-specific C2 states since last reset. Counts at 1 Mhz
- frequency.
-
- @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
- AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
-
-
-/**
- Package. Package C4 Residency Note: C-state values are processor specific
- C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
- C-States. Package. Package C4 Residency Counter. (R/O) Time that this
- package is in processor-specific C4 states since last reset. Counts at 1 Mhz
- frequency.
-
- @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
- AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
-
-
-/**
- Package. Package C6 Residency Note: C-state values are processor specific
- C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
- C-States. Package. Package C6 Residency Counter. (R/O) Time that this
- package is in processor-specific C6 states since last reset. Counts at 1 Mhz
- frequency.
-
- @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h deleted file mode 100644 index 69c404eccd..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h +++ /dev/null @@ -1,265 +0,0 @@ -/** @file
- MSR Definitions for Intel processors based on the Broadwell microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.
-
-**/
-
-#ifndef __BROADWELL_MSR_H__
-#define __BROADWELL_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-/**
- MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Ovf_PMC0.
- ///
- UINT32 Ovf_PMC0:1;
- ///
- /// [Bit 1] Ovf_PMC1.
- ///
- UINT32 Ovf_PMC1:1;
- ///
- /// [Bit 2] Ovf_PMC2.
- ///
- UINT32 Ovf_PMC2:1;
- ///
- /// [Bit 3] Ovf_PMC3.
- ///
- UINT32 Ovf_PMC3:1;
- UINT32 Reserved1:28;
- ///
- /// [Bit 32] Ovf_FixedCtr0.
- ///
- UINT32 Ovf_FixedCtr0:1;
- ///
- /// [Bit 33] Ovf_FixedCtr1.
- ///
- UINT32 Ovf_FixedCtr1:1;
- ///
- /// [Bit 34] Ovf_FixedCtr2.
- ///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:20;
- ///
- /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical
- /// Addresses (ToPA).".
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved3:5;
- ///
- /// [Bit 61] Ovf_Uncore.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Ovf_BufDSSAVE.
- ///
- UINT32 OvfBuf:1;
- ///
- /// [Bit 63] CondChgd.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;
-
-
-/**
- Core. C-State Configuration Control (R/W) Note: C-state values are processor
- specific C-state code names, unrelated to MWAIT extension C-state parameters
- or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
-
- @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
- /// processor-specific C-state code name (consuming the least power) for
- /// the package. The default is set as factory-configured package C-state
- /// limit. The following C-state code name encodings are supported: 0000b:
- /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
- /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
- ///
- UINT32 Limit:4;
- UINT32 Reserved1:6;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO).
- ///
- UINT32 CFGLock:1;
- UINT32 Reserved3:9;
- ///
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).
- ///
- UINT32 C3AutoDemotion:1;
- ///
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).
- ///
- UINT32 C1AutoDemotion:1;
- ///
- /// [Bit 27] Enable C3 Undemotion (R/W).
- ///
- UINT32 C3Undemotion:1;
- ///
- /// [Bit 28] Enable C1 Undemotion (R/W).
- ///
- UINT32 C1Undemotion:1;
- ///
- /// [Bit 29] Enable Package C-State Auto-demotion (R/W).
- ///
- UINT32 CStateAutoDemotion:1;
- ///
- /// [Bit 30] Enable Package C-State Undemotion (R/W).
- ///
- UINT32 CStateUndemotion:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
- @endcode
-**/
-#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
- /// limit of 1 core active.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
- /// limit of 2 core active.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
- /// limit of 3 core active.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
- /// limit of 4 core active.
- ///
- UINT32 Maximum4C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
- /// limit of 5core active.
- ///
- UINT32 Maximum5C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
- /// limit of 6core active.
- ///
- UINT32 Maximum6C:8;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h deleted file mode 100644 index 5fbde51bde..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h +++ /dev/null @@ -1,1325 +0,0 @@ -/** @file
- MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.
-
-**/
-
-#ifndef __CORE2_MSR_H__
-#define __CORE2_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Shared. Model Specific Platform ID (R).
-
- @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_PLATFORM_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
- @endcode
-**/
-#define MSR_CORE2_PLATFORM_ID 0x00000017
-
-/**
- MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
- ///
- UINT32 MaximumQualifiedRatio:5;
- UINT32 Reserved2:19;
- UINT32 Reserved3:18;
- ///
- /// [Bits 52:50] See Table 35-2.
- ///
- UINT32 PlatformId:3;
- UINT32 Reserved4:11;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_PLATFORM_ID_REGISTER;
-
-
-/**
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
- processor features; (R) indicates current processor configuration.
-
- @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
- AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_EBL_CR_POWERON 0x0000002A
-
-/**
- MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Note: Not all processor implements R/W.
- ///
- UINT32 DataErrorCheckingEnable:1;
- ///
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Note: Not all processor implements R/W.
- ///
- UINT32 ResponseErrorCheckingEnable:1;
- ///
- /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
- /// all processor implements R/W.
- ///
- UINT32 MCERR_DriveEnable:1;
- ///
- /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
- /// Not all processor implements R/W.
- ///
- UINT32 AddressParityEnable:1;
- UINT32 Reserved2:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
- /// all processor implements R/W.
- ///
- UINT32 BINIT_DriverEnable:1;
- ///
- /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 OutputTriStateEnable:1;
- ///
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 ExecuteBIST:1;
- ///
- /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 MCERR_ObservationEnabled:1;
- ///
- /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.
- ///
- UINT32 IntelTXTCapableChipset:1;
- ///
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 BINIT_ObservationEnabled:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
- ///
- UINT32 ResetVector:1;
- UINT32 Reserved5:1;
- ///
- /// [Bits 17:16] APIC Cluster ID (R/O).
- ///
- UINT32 APICClusterID:2;
- ///
- /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =
- /// Non-integer ratio.
- ///
- UINT32 NonIntegerBusRatio:1;
- UINT32 Reserved6:1;
- ///
- /// [Bits 21:20] Symmetric Arbitration ID (R/O).
- ///
- UINT32 SymmetricArbitrationID:2;
- ///
- /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
- ///
- UINT32 IntegerBusFrequencyRatio:5;
- UINT32 Reserved7:5;
- UINT32 Reserved8:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_EBL_CR_POWERON_REGISTER;
-
-
-/**
- Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.
-
- @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
- AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_FEATURE_CONTROL 0x0000003A
-
-/**
- MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:3;
- ///
- /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock
- /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read
- /// visible and writeable while in SMM.
- ///
- UINT32 SMRREnable:1;
- UINT32 Reserved2:28;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_FEATURE_CONTROL_REGISTER;
-
-
-/**
- Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the source instruction for one of the last four
- branches, exceptions, or interrupts taken by the processor. See also: -
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
- Interrupt, and Exception Recording (Pentium M Processors).".
-
- @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
- AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040
-#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041
-#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042
-#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043
-/// @}
-
-
-/**
- Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction for one of the last four
- branches, exceptions, or interrupts taken by the processor.
-
- @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
- AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060
-#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061
-#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062
-#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063
-/// @}
-
-
-/**
- Unique. System Management Mode Base Address register (WO in SMM)
- Model-specific implementation of SMRR-like interface, read visible and write
- only in SMM.
-
- @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;
-
- Msr.Uint64 = 0;
- AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0
-
-/**
- MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:12;
- ///
- /// [Bits 31:12] PhysBase. SMRR physical Base Address.
- ///
- UINT32 PhysBase:20;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_SMRR_PHYSBASE_REGISTER;
-
-
-/**
- Unique. System Management Mode Physical Address Mask register (WO in SMM)
- Model-specific implementation of SMRR-like interface, read visible and write
- only in SMM.
-
- @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;
-
- Msr.Uint64 = 0;
- AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1
-
-/**
- MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:11;
- ///
- /// [Bit 11] Valid. Physical address base and range mask are valid.
- ///
- UINT32 Valid:1;
- ///
- /// [Bits 31:12] PhysMask. SMRR physical address range mask.
- ///
- UINT32 PhysMask:20;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_SMRR_PHYSMASK_REGISTER;
-
-
-/**
- Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
- bus clock speed for processors based on Intel Core microarchitecture:.
-
- @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_FSB_FREQ_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
- @endcode
-**/
-#define MSR_CORE2_FSB_FREQ 0x000000CD
-
-/**
- MSR information returned for MSR index #MSR_CORE2_FSB_FREQ
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] - Scalable Bus Speed
- /// 101B: 100 MHz (FSB 400)
- /// 001B: 133 MHz (FSB 533)
- /// 011B: 167 MHz (FSB 667)
- /// 010B: 200 MHz (FSB 800)
- /// 000B: 267 MHz (FSB 1067)
- /// 100B: 333 MHz (FSB 1333)
- ///
- /// 133.33 MHz should be utilized if performing calculation with System
- /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
- /// performing calculation with System Bus Speed when encoding is 011B.
- /// 266.67 MHz should be utilized if performing calculation with System
- /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if
- /// performing calculation with System Bus Speed when encoding is 100B.
- ///
- UINT32 ScalableBusSpeed:3;
- UINT32 Reserved1:29;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_FSB_FREQ_REGISTER;
-
-
-/**
- Shared.
-
- @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
- AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_BBL_CR_CTL3 0x0000011E
-
-/**
- MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
- /// Indicates if the L2 is hardware-disabled.
- ///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:7;
- ///
- /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
- /// Disabled (default) Until this bit is set the processor will not
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
- ///
- UINT32 L2Enabled:1;
- UINT32 Reserved2:14;
- ///
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
- ///
- UINT32 L2NotPresent:1;
- UINT32 Reserved3:8;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_BBL_CR_CTL3_REGISTER;
-
-
-/**
- Shared.
-
- @param ECX MSR_CORE2_PERF_STATUS (0x00000198)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_PERF_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
- AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_PERF_STATUS 0x00000198
-
-/**
- MSR information returned for MSR index #MSR_CORE2_PERF_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Current Performance State Value.
- ///
- UINT32 CurrentPerformanceStateValue:16;
- UINT32 Reserved1:15;
- ///
- /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default
- /// is cleared.
- ///
- UINT32 XEOperation:1;
- UINT32 Reserved2:8;
- ///
- /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
- /// configured for the processor.
- ///
- UINT32 MaximumBusRatio:5;
- UINT32 Reserved3:1;
- ///
- /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio
- /// is enabled. Applies processors based on Enhanced Intel Core
- /// microarchitecture.
- ///
- UINT32 NonIntegerBusRatio:1;
- UINT32 Reserved4:17;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_PERF_STATUS_REGISTER;
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_THERM2_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
- AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_THERM2_CTL 0x0000019D
-
-/**
- MSR information returned for MSR index #MSR_CORE2_THERM2_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
- ///
- UINT32 TM_SELECT:1;
- UINT32 Reserved2:15;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_THERM2_CTL_REGISTER;
-
-
-/**
- Enable Misc. Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Fast-Strings Enable See Table 35-2.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the
- /// hardware prefetcher operation on streams of data. When clear
- /// (default), enables the prefetch queue. Disabling of the hardware
- /// prefetcher may impact processor performance.
- ///
- UINT32 HardwarePrefetcherDisable:1;
- ///
- /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
- /// the processor to indicate a pending break event within the processor 0
- /// = Indicates compatible FERR# signaling behavior This bit must be set
- /// to 1 to support XAPIC interrupt model usage.
- ///
- UINT32 FERR:1;
- ///
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
- ///
- UINT32 PEBS:1;
- ///
- /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
- /// thermal sensor indicates that the die temperature is at the
- /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
- /// TM2 will reduce the bus to core ratio and voltage according to the
- /// value last written to MSR_THERM2_CTL bits 15:0.
- /// When this bit is clear (0, default), the processor does not change
- /// the VID signals or the bus to core ratio when the processor enters a
- /// thermally managed state. The BIOS must enable this feature if the
- /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
- /// not set, this feature is not supported and BIOS must not alter the
- /// contents of the TM2 bit location. The processor is operating out of
- /// specification if both this bit and the TM1 bit are set to 0.
- ///
- UINT32 TM2:1;
- UINT32 Reserved4:2;
- ///
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
- ///
- UINT32 MONITOR:1;
- ///
- /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set
- /// to 1, the processor fetches the cache line that contains data
- /// currently required by the processor. When set to 0, the processor
- /// fetches cache lines that comprise a cache line pair (128 bytes).
- /// Single processor platforms should not set this bit. Server platforms
- /// should set or clear this bit based on platform performance observed in
- /// validation and testing. BIOS may contain a setup option that controls
- /// the setting of this bit.
- ///
- UINT32 AdjacentCacheLinePrefetchDisable:1;
- ///
- /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
- /// (R/WO) When set, this bit causes the following bits to become
- /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
- /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
- /// be set before an Enhanced Intel SpeedStep Technology transition is
- /// requested. This bit is cleared on reset.
- ///
- UINT32 EISTLock:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
- ///
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
- ///
- UINT32 XD:1;
- UINT32 Reserved9:2;
- ///
- /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU
- /// L1 data cache prefetcher is disabled. The default value after reset is
- /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is
- /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple
- /// loads from the same line done within a time limit, the DCU prefetcher
- /// assumes the next line will be required. The next line is prefetched in
- /// to the L1 data cache from memory or L2.
- ///
- UINT32 DCUPrefetcherDisable:1;
- ///
- /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that
- /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled
- /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
- /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
- /// reports the processor's support of IDA is enabled. Note: the power-on
- /// default value is used by BIOS to detect hardware support of IDA. If
- /// power-on default value is 1, IDA is available in the processor. If
- /// power-on default value is 0, IDA is not available.
- ///
- UINT32 IDADisable:1;
- ///
- /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP
- /// prefetcher is disabled. The default value after reset is 0. BIOS may
- /// write '1' to disable this feature. The IP prefetcher is an L1 data
- /// cache prefetcher. The IP prefetcher looks for sequential load history
- /// to determine whether to prefetch the next expected data into the L1
- /// cache from memory or L2.
- ///
- UINT32 IPPrefetcherDisable:1;
- UINT32 Reserved10:24;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
- that points to the MSR containing the most recent branch record. See
- MSR_LASTBRANCH_0_FROM_IP (at 40H).
-
- @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
- last branch instruction that the processor executed prior to the last
- exception that was generated or the last interrupt that was handled.
-
- @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_CORE2_LER_FROM_LIP 0x000001DD
-
-
-/**
- Unique. Last Exception Record To Linear IP (R) This area contains a pointer
- to the target of the last branch instruction that the processor executed
- prior to the last exception that was generated or the last interrupt that
- was handled.
-
- @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
- @endcode
-**/
-#define MSR_CORE2_LER_TO_LIP 0x000001DE
-
-
-/**
- Unique. Fixed-Function Performance Counter Register n (R/W).
-
- @param ECX MSR_CORE2_PERF_FIXED_CTRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
- AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
- @endcode
- @{
-**/
-#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309
-#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A
-#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B
-/// @}
-
-
-/**
- Unique. RO. This applies to processors that do not support architectural
- perfmon version 2.
-
- @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
- AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_PERF_CAPABILITIES 0x00000345
-
-/**
- MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 5:0] LBR Format. See Table 35-2.
- ///
- UINT32 LBR_FMT:6;
- ///
- /// [Bit 6] PEBS Record Format.
- ///
- UINT32 PEBS_FMT:1;
- ///
- /// [Bit 7] PEBSSaveArchRegs. See Table 35-2.
- ///
- UINT32 PEBS_ARCH_REG:1;
- UINT32 Reserved1:24;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_PERF_CAPABILITIES_REGISTER;
-
-
-/**
- Unique. Fixed-Function-Counter Control Register (R/W).
-
- @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
- AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
- @endcode
-**/
-#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D
-
-
-/**
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_CORE2_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
-**/
-#define MSR_CORE2_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".
-
- @param ECX MSR_CORE2_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);
- @endcode
-**/
-#define MSR_CORE2_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".
-
- @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
- @endcode
-**/
-#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F
-
-
-/**
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".
-
- @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390
-
-
-/**
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
- (PEBS).".
-
- @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE2_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
- ///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_PEBS_ENABLE_REGISTER;
-
-
-/**
- Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_CORE2_MC4_CTL (0x0000040C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);
- AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC4_CTL 0x0000040C
-
-
-/**
- Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_CORE2_MC4_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);
- AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC4_STATUS 0x0000040D
-
-
-/**
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC4_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_CORE2_MC4_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);
- AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC4_ADDR 0x0000040E
-
-
-/**
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_CORE2_MC3_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);
- AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC3_CTL 0x00000410
-
-
-/**
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_CORE2_MC3_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);
- AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC3_STATUS 0x00000411
-
-
-/**
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC3_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_CORE2_MC3_ADDR (0x00000412)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);
- AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC3_ADDR 0x00000412
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC3_MISC (0x00000413)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);
- AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC3_MISC 0x00000413
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC5_CTL (0x00000414)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);
- AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC5_CTL 0x00000414
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC5_STATUS (0x00000415)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);
- AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC5_STATUS 0x00000415
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC5_ADDR (0x00000416)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);
- AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC5_ADDR 0x00000416
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC5_MISC (0x00000417)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);
- AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC5_MISC 0x00000417
-
-
-/**
- Unique. Apply to Intel Xeon processor 7400 series (processor signature
- 06_1D) only. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS." and Chapter 23.
-
- @param ECX MSR_CORE2_MC6_STATUS (0x00000419)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);
- AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);
- @endcode
-**/
-#define MSR_CORE2_MC6_STATUS 0x00000419
-
-
-/**
- Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
- processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
-
- @param ECX MSR_CORE2_EMON_L3_CTR_CTLn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
- AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
- @endcode
- @{
-**/
-#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC
-#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD
-#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE
-#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF
-#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0
-#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1
-#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2
-#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3
-/// @}
-
-
-/**
- Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor
- 7400 series (processor signature 06_1D) only. See Section 17.2.2.
-
- @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
- AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
- @endcode
-**/
-#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h deleted file mode 100644 index 11956fb7f5..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h +++ /dev/null @@ -1,1074 +0,0 @@ -/** @file
- MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17.
-
-**/
-
-#ifndef __CORE_MSR_H__
-#define __CORE_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
-
- @param ECX MSR_CORE_P5_MC_ADDR (0x00000000)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
- AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
- @endcode
-**/
-#define MSR_CORE_P5_MC_ADDR 0x00000000
-
-
-/**
- Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
-
- @param ECX MSR_CORE_P5_MC_TYPE (0x00000001)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
- AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
- @endcode
-**/
-#define MSR_CORE_P5_MC_TYPE 0x00000001
-
-
-/**
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
- processor features; (R) indicates current processor configuration.
-
- @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE_EBL_CR_POWERON_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
- AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE_EBL_CR_POWERON 0x0000002A
-
-/**
- MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Note: Not all processor implements R/W.
- ///
- UINT32 DataErrorCheckingEnable:1;
- ///
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Note: Not all processor implements R/W.
- ///
- UINT32 ResponseErrorCheckingEnable:1;
- ///
- /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
- /// all processor implements R/W.
- ///
- UINT32 MCERR_DriveEnable:1;
- ///
- /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
- /// Not all processor implements R/W.
- ///
- UINT32 AddressParityEnable:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
- /// all processor implements R/W.
- ///
- UINT32 BINIT_DriverEnable:1;
- ///
- /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 OutputTriStateEnable:1;
- ///
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 ExecuteBIST:1;
- ///
- /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 MCERR_ObservationEnabled:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 BINIT_ObservationEnabled:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
- ///
- UINT32 ResetVector:1;
- UINT32 Reserved5:1;
- ///
- /// [Bits 17:16] APIC Cluster ID (R/O).
- ///
- UINT32 APICClusterID:2;
- ///
- /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
- ///
- UINT32 SystemBusFrequency:1;
- UINT32 Reserved6:1;
- ///
- /// [Bits 21:20] Symmetric Arbitration ID (R/O).
- ///
- UINT32 SymmetricArbitrationID:2;
- ///
- /// [Bits 26:22] Clock Frequency Ratio (R/O).
- ///
- UINT32 ClockFrequencyRatio:5;
- UINT32 Reserved7:5;
- UINT32 Reserved8:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_EBL_CR_POWERON_REGISTER;
-
-
-/**
- Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
- the last branch record stack: bits 31-0 hold the 'from' address and bits
- 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at
- 1C9H - Section 17.12, "Last Branch, Interrupt, and Exception Recording
- (Pentium M Processors).".
-
- @param ECX MSR_CORE_LASTBRANCH_n
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
- AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
- @endcode
- @{
-**/
-#define MSR_CORE_LASTBRANCH_0 0x00000040
-#define MSR_CORE_LASTBRANCH_1 0x00000041
-#define MSR_CORE_LASTBRANCH_2 0x00000042
-#define MSR_CORE_LASTBRANCH_3 0x00000043
-#define MSR_CORE_LASTBRANCH_4 0x00000044
-#define MSR_CORE_LASTBRANCH_5 0x00000045
-#define MSR_CORE_LASTBRANCH_6 0x00000046
-#define MSR_CORE_LASTBRANCH_7 0x00000047
-/// @}
-
-
-/**
- Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
- clock speed:.
-
- @param ECX MSR_CORE_FSB_FREQ (0x000000CD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_FSB_FREQ_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_FSB_FREQ_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE_FSB_FREQ_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
- @endcode
-**/
-#define MSR_CORE_FSB_FREQ 0x000000CD
-
-/**
- MSR information returned for MSR index #MSR_CORE_FSB_FREQ
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] - Scalable Bus Speed
- /// 101B: 100 MHz (FSB 400)
- /// 001B: 133 MHz (FSB 533)
- /// 011B: 167 MHz (FSB 667)
- ///
- /// 133.33 MHz should be utilized if performing calculation with System Bus
- /// Speed when encoding is 101B. 166.67 MHz should be utilized if
- /// performing calculation with System Bus Speed when encoding is 001B.
- ///
- UINT32 ScalableBusSpeed:3;
- UINT32 Reserved1:29;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_FSB_FREQ_REGISTER;
-
-
-/**
- Shared.
-
- @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE_BBL_CR_CTL3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
- AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE_BBL_CR_CTL3 0x0000011E
-
-/**
- MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
- /// Indicates if the L2 is hardware-disabled.
- ///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:7;
- ///
- /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
- /// Disabled (default) Until this bit is set the processor will not
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
- ///
- UINT32 L2Enabled:1;
- UINT32 Reserved2:14;
- ///
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
- ///
- UINT32 L2NotPresent:1;
- UINT32 Reserved3:8;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_BBL_CR_CTL3_REGISTER;
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_THERM2_CTL (0x0000019D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_THERM2_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_THERM2_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE_THERM2_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
- AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE_THERM2_CTL 0x0000019D
-
-/**
- MSR information returned for MSR index #MSR_CORE_THERM2_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
- ///
- UINT32 TM_SELECT:1;
- UINT32 Reserved2:15;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_THERM2_CTL_REGISTER;
-
-
-/**
- Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:3;
- ///
- /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
- /// the processor to indicate a pending break event within the processor 0
- /// = Indicates compatible FERR# signaling behavior This bit must be set
- /// to 1 to support XAPIC interrupt model usage.
- ///
- UINT32 FERR:1;
- ///
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
- ///
- UINT32 BTS:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
- /// thermal sensor indicates that the die temperature is at the
- /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
- /// TM2 will reduce the bus to core ratio and voltage according to the
- /// value last written to MSR_THERM2_CTL bits 15:0.
- /// When this bit is clear (0, default), the processor does not change
- /// the VID signals or the bus to core ratio when the processor enters a
- /// thermal managed state. If the TM2 feature flag (ECX[8]) is not set
- /// to 1 after executing CPUID with EAX = 1, then this feature is not
- /// supported and BIOS must not alter the contents of this bit location.
- /// The processor is operating out of spec if both this bit and the TM1
- /// bit are set to disabled states.
- ///
- UINT32 TM2:1;
- UINT32 Reserved5:2;
- ///
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
- /// Enhanced Intel SpeedStep Technology enabled.
- ///
- UINT32 EIST:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
- ///
- UINT32 MONITOR:1;
- UINT32 Reserved7:1;
- UINT32 Reserved8:2;
- ///
- /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this
- /// bit may cause behavior in software that depends on the availability of
- /// CPUID leaves greater than 3.
- ///
- UINT32 LimitCpuidMaxval:1;
- UINT32 Reserved9:9;
- UINT32 Reserved10:2;
- ///
- /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 35-2.
- ///
- UINT32 XD:1;
- UINT32 Reserved11:29;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
- that points to the MSR containing the most recent branch record. See
- MSR_LASTBRANCH_0_FROM_IP (at 40H).
-
- @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_CORE_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
- last branch instruction that the processor executed prior to the last
- exception that was generated or the last interrupt that was handled.
-
- @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_CORE_LER_FROM_LIP 0x000001DD
-
-
-/**
- Unique. Last Exception Record To Linear IP (R) This area contains a pointer
- to the target of the last branch instruction that the processor executed
- prior to the last exception that was generated or the last interrupt that
- was handled.
-
- @param ECX MSR_CORE_LER_TO_LIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
- @endcode
-**/
-#define MSR_CORE_LER_TO_LIP 0x000001DE
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_ROB_CR_BKUPTMPDR6 (0x000001E0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
- AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE_ROB_CR_BKUPTMPDR6 0x000001E0
-
-/**
- MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:2;
- ///
- /// [Bit 2] Fast Strings Enable bit. (Default, enabled).
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER;
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRPHYSBASEn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
- AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
- @endcode
- @{
-**/
-#define MSR_CORE_MTRRPHYSBASE0 0x00000200
-#define MSR_CORE_MTRRPHYSBASE1 0x00000202
-#define MSR_CORE_MTRRPHYSBASE2 0x00000204
-#define MSR_CORE_MTRRPHYSBASE3 0x00000206
-#define MSR_CORE_MTRRPHYSBASE4 0x00000208
-#define MSR_CORE_MTRRPHYSBASE5 0x0000020A
-#define MSR_CORE_MTRRPHYSMASK6 0x0000020D
-#define MSR_CORE_MTRRPHYSMASK7 0x0000020F
-/// @}
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
- AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
- @endcode
- @{
-**/
-#define MSR_CORE_MTRRPHYSMASK0 0x00000201
-#define MSR_CORE_MTRRPHYSMASK1 0x00000203
-#define MSR_CORE_MTRRPHYSMASK2 0x00000205
-#define MSR_CORE_MTRRPHYSMASK3 0x00000207
-#define MSR_CORE_MTRRPHYSMASK4 0x00000209
-#define MSR_CORE_MTRRPHYSMASK5 0x0000020B
-#define MSR_CORE_MTRRPHYSBASE6 0x0000020C
-#define MSR_CORE_MTRRPHYSBASE7 0x0000020E
-/// @}
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX64K_00000 0x00000250
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX16K_80000 0x00000258
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX16K_A0000 0x00000259
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX4K_C0000 0x00000268
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX4K_C8000 0x00000269
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
- @endcode
-**/
-#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F
-
-
-/**
- Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_CORE_MC4_CTL (0x0000040C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
- AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
- @endcode
-**/
-#define MSR_CORE_MC4_CTL 0x0000040C
-
-
-/**
- Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_CORE_MC4_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
- AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
- @endcode
-**/
-#define MSR_CORE_MC4_STATUS 0x0000040D
-
-
-/**
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC4_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_CORE_MC4_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
- AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
- @endcode
-**/
-#define MSR_CORE_MC4_ADDR 0x0000040E
-
-
-/**
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_CORE_MC3_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC3_CTL);
- AsmWriteMsr64 (MSR_CORE_MC3_CTL, Msr);
- @endcode
-**/
-#define MSR_CORE_MC3_CTL 0x00000410
-
-
-/**
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_CORE_MC3_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC3_STATUS);
- AsmWriteMsr64 (MSR_CORE_MC3_STATUS, Msr);
- @endcode
-**/
-#define MSR_CORE_MC3_STATUS 0x00000411
-
-
-/**
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC3_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_CORE_MC3_ADDR (0x00000412)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
- AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
- @endcode
-**/
-#define MSR_CORE_MC3_ADDR 0x00000412
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MC3_MISC (0x00000413)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
- AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
- @endcode
-**/
-#define MSR_CORE_MC3_MISC 0x00000413
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MC5_CTL (0x00000414)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
- AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
- @endcode
-**/
-#define MSR_CORE_MC5_CTL 0x00000414
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MC5_STATUS (0x00000415)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
- AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
- @endcode
-**/
-#define MSR_CORE_MC5_STATUS 0x00000415
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MC5_ADDR (0x00000416)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
- AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
- @endcode
-**/
-#define MSR_CORE_MC5_ADDR 0x00000416
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE_MC5_MISC (0x00000417)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
- AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
- @endcode
-**/
-#define MSR_CORE_MC5_MISC 0x00000417
-
-
-/**
- Unique. See Table 35-2.
-
- @param ECX MSR_CORE_IA32_EFER (0xC0000080)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_IA32_EFER_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_IA32_EFER_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE_IA32_EFER_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
- AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
- @endcode
-**/
-#define MSR_CORE_IA32_EFER 0xC0000080
-
-/**
- MSR information returned for MSR index #MSR_CORE_IA32_EFER
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:11;
- ///
- /// [Bit 11] Execute Disable Bit Enable.
- ///
- UINT32 NXE:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_IA32_EFER_REGISTER;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h deleted file mode 100644 index ae9f406863..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h +++ /dev/null @@ -1,5995 +0,0 @@ -/** @file
- MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11.
-
-**/
-
-#ifndef __HASWELL_E_MSR_H__
-#define __HASWELL_E_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Core. C-State Configuration Control (R/W) Note: C-state values are processor
- specific C-state code names, unrelated to MWAIT extension C-state parameters
- or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
-
- @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
- /// processor-specific C-state code name (consuming the least power) for
- /// the package. The default is set as factory-configured package C-state
- /// limit. The following C-state code name encodings are supported: 000b:
- /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
- /// 011b: C6 (retention) 111b: No Package C state limits. All C states
- /// supported by the processor are available.
- ///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO).
- ///
- UINT32 CFGLock:1;
- UINT32 Reserved3:9;
- ///
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).
- ///
- UINT32 C3AutoDemotion:1;
- ///
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).
- ///
- UINT32 C1AutoDemotion:1;
- ///
- /// [Bit 27] Enable C3 Undemotion (R/W).
- ///
- UINT32 C3Undemotion:1;
- ///
- /// [Bit 28] Enable C1 Undemotion (R/W).
- ///
- UINT32 C1Undemotion:1;
- ///
- /// [Bit 29] Package C State Demotion Enable (R/W).
- ///
- UINT32 CStateDemotion:1;
- ///
- /// [Bit 30] Package C State UnDemotion Enable (R/W).
- ///
- UINT32 CStateUndemotion:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- Thread. Global Machine Check Capability (R/O).
-
- @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
- @endcode
-**/
-#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Count.
- ///
- UINT32 Count:8;
- ///
- /// [Bit 8] MCG_CTL_P.
- ///
- UINT32 MCG_CTL_P:1;
- ///
- /// [Bit 9] MCG_EXT_P.
- ///
- UINT32 MCG_EXT_P:1;
- ///
- /// [Bit 10] MCP_CMCI_P.
- ///
- UINT32 MCP_CMCI_P:1;
- ///
- /// [Bit 11] MCG_TES_P.
- ///
- UINT32 MCG_TES_P:1;
- UINT32 Reserved1:4;
- ///
- /// [Bits 23:16] MCG_EXT_CNT.
- ///
- UINT32 MCG_EXT_CNT:8;
- ///
- /// [Bit 24] MCG_SER_P.
- ///
- UINT32 MCG_SER_P:1;
- ///
- /// [Bit 25] MCG_EM_P.
- ///
- UINT32 MCG_EM_P:1;
- ///
- /// [Bit 26] MCG_ELOG_P.
- ///
- UINT32 MCG_ELOG_P:1;
- UINT32 Reserved2:5;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;
-
-
-/**
- THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
- Enhancement. Accessible only while in SMM.
-
- @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
- AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:26;
- ///
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
- /// SMM code access restriction is supported and a host-space interface
- /// available to SMM handler.
- ///
- UINT32 SMM_Code_Access_Chk:1;
- ///
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
- /// SMM long flow indicator is supported and a host-space interface
- /// available to SMM handler.
- ///
- UINT32 Long_Flow_Indication:1;
- UINT32 Reserved3:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;
-
-
-/**
- Package. MC Bank Error Configuration (R/W).
-
- @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
- AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
- /// to log additional info in bits 36:32.
- ///
- UINT32 MemErrorLogEnable:1;
- UINT32 Reserved2:30;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
- @endcode
-**/
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
- /// limit of 1 core active.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
- /// limit of 2 core active.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
- /// limit of 3 core active.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
- /// limit of 4 core active.
- ///
- UINT32 Maximum4C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
- /// limit of 5 core active.
- ///
- UINT32 Maximum5C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
- /// limit of 6 core active.
- ///
- UINT32 Maximum6C:8;
- ///
- /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
- /// limit of 7 core active.
- ///
- UINT32 Maximum7C:8;
- ///
- /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
- /// limit of 8 core active.
- ///
- UINT32 Maximum8C:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
- @endcode
-**/
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
- /// limit of 9 core active.
- ///
- UINT32 Maximum9C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
- /// limit of 10 core active.
- ///
- UINT32 Maximum10C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
- /// limit of 11 core active.
- ///
- UINT32 Maximum11C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
- /// limit of 12 core active.
- ///
- UINT32 Maximum12C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
- /// limit of 13 core active.
- ///
- UINT32 Maximum13C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
- /// limit of 14 core active.
- ///
- UINT32 Maximum14C:8;
- ///
- /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
- /// limit of 15 core active.
- ///
- UINT32 Maximum15C:8;
- ///
- /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
- /// limit of 16 core active.
- ///
- UINT32 Maximum16C:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
- @endcode
-**/
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
- /// limit of 17 core active.
- ///
- UINT32 Maximum17C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
- /// limit of 18 core active.
- ///
- UINT32 Maximum18C:8;
- UINT32 Reserved1:16;
- UINT32 Reserved2:31;
- ///
- /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
- /// the processor uses override configuration specified in
- /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
- /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
- /// configuration (Default).
- ///
- UINT32 TurboRatioLimitConfigurationSemaphore:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- * Bank MC5 reports MC error from the Intel QPI 0 module.
- * Bank MC6 reports MC error from the integrated I/O module.
- * Bank MC7 reports MC error from the home agent HA 0.
- * Bank MC8 reports MC error from the home agent HA 1.
- * Banks MC9 through MC16 report MC error from each channel of the integrated
- memory controllers.
- * Bank MC17 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.
- * Bank MC18 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.
- * Bank MC19 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.
- * Bank MC20 reports MC error from the Intel QPI 1 module.
- * Bank MC21 reports MC error from the Intel QPI 2 module.
-
- @param ECX MSR_HASWELL_E_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);
- @endcode
- @{
-**/
-#define MSR_HASWELL_E_MC5_CTL 0x00000414
-#define MSR_HASWELL_E_MC6_CTL 0x00000418
-#define MSR_HASWELL_E_MC7_CTL 0x0000041C
-#define MSR_HASWELL_E_MC8_CTL 0x00000420
-#define MSR_HASWELL_E_MC9_CTL 0x00000424
-#define MSR_HASWELL_E_MC10_CTL 0x00000428
-#define MSR_HASWELL_E_MC11_CTL 0x0000042C
-#define MSR_HASWELL_E_MC12_CTL 0x00000430
-#define MSR_HASWELL_E_MC13_CTL 0x00000434
-#define MSR_HASWELL_E_MC14_CTL 0x00000438
-#define MSR_HASWELL_E_MC15_CTL 0x0000043C
-#define MSR_HASWELL_E_MC16_CTL 0x00000440
-#define MSR_HASWELL_E_MC17_CTL 0x00000444
-#define MSR_HASWELL_E_MC18_CTL 0x00000448
-#define MSR_HASWELL_E_MC19_CTL 0x0000044C
-#define MSR_HASWELL_E_MC20_CTL 0x00000450
-#define MSR_HASWELL_E_MC21_CTL 0x00000454
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_HASWELL_E_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);
- @endcode
- @{
-**/
-#define MSR_HASWELL_E_MC5_STATUS 0x00000415
-#define MSR_HASWELL_E_MC6_STATUS 0x00000419
-#define MSR_HASWELL_E_MC7_STATUS 0x0000041D
-#define MSR_HASWELL_E_MC8_STATUS 0x00000421
-#define MSR_HASWELL_E_MC9_STATUS 0x00000425
-#define MSR_HASWELL_E_MC10_STATUS 0x00000429
-#define MSR_HASWELL_E_MC11_STATUS 0x0000042D
-#define MSR_HASWELL_E_MC12_STATUS 0x00000431
-#define MSR_HASWELL_E_MC13_STATUS 0x00000435
-#define MSR_HASWELL_E_MC14_STATUS 0x00000439
-#define MSR_HASWELL_E_MC15_STATUS 0x0000043D
-#define MSR_HASWELL_E_MC16_STATUS 0x00000441
-#define MSR_HASWELL_E_MC17_STATUS 0x00000445
-#define MSR_HASWELL_E_MC18_STATUS 0x00000449
-#define MSR_HASWELL_E_MC19_STATUS 0x0000044D
-#define MSR_HASWELL_E_MC20_STATUS 0x00000451
-#define MSR_HASWELL_E_MC21_STATUS 0x00000455
-/// @}
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_HASWELL_E_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);
- @endcode
- @{
-**/
-#define MSR_HASWELL_E_MC5_ADDR 0x00000416
-#define MSR_HASWELL_E_MC6_ADDR 0x0000041A
-#define MSR_HASWELL_E_MC7_ADDR 0x0000041E
-#define MSR_HASWELL_E_MC8_ADDR 0x00000422
-#define MSR_HASWELL_E_MC9_ADDR 0x00000426
-#define MSR_HASWELL_E_MC10_ADDR 0x0000042A
-#define MSR_HASWELL_E_MC11_ADDR 0x0000042E
-#define MSR_HASWELL_E_MC12_ADDR 0x00000432
-#define MSR_HASWELL_E_MC13_ADDR 0x00000436
-#define MSR_HASWELL_E_MC14_ADDR 0x0000043A
-#define MSR_HASWELL_E_MC15_ADDR 0x0000043E
-#define MSR_HASWELL_E_MC16_ADDR 0x00000442
-#define MSR_HASWELL_E_MC17_ADDR 0x00000446
-#define MSR_HASWELL_E_MC18_ADDR 0x0000044A
-#define MSR_HASWELL_E_MC19_ADDR 0x0000044E
-#define MSR_HASWELL_E_MC20_ADDR 0x00000452
-#define MSR_HASWELL_E_MC21_ADDR 0x00000456
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_HASWELL_E_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);
- @endcode
- @{
-**/
-#define MSR_HASWELL_E_MC5_MISC 0x00000417
-#define MSR_HASWELL_E_MC6_MISC 0x0000041B
-#define MSR_HASWELL_E_MC7_MISC 0x0000041F
-#define MSR_HASWELL_E_MC8_MISC 0x00000423
-#define MSR_HASWELL_E_MC9_MISC 0x00000427
-#define MSR_HASWELL_E_MC10_MISC 0x0000042B
-#define MSR_HASWELL_E_MC11_MISC 0x0000042F
-#define MSR_HASWELL_E_MC12_MISC 0x00000433
-#define MSR_HASWELL_E_MC13_MISC 0x00000437
-#define MSR_HASWELL_E_MC14_MISC 0x0000043B
-#define MSR_HASWELL_E_MC15_MISC 0x0000043F
-#define MSR_HASWELL_E_MC16_MISC 0x00000443
-#define MSR_HASWELL_E_MC17_MISC 0x00000447
-#define MSR_HASWELL_E_MC18_MISC 0x0000044B
-#define MSR_HASWELL_E_MC19_MISC 0x0000044F
-#define MSR_HASWELL_E_MC20_MISC 0x00000453
-#define MSR_HASWELL_E_MC21_MISC 0x00000457
-/// @}
-
-
-/**
- Package. Unit Multipliers used in RAPL Interfaces (R/O).
-
- @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
- @endcode
-**/
-#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
- ///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
- ///
- /// [Bits 12:8] Package. Energy Status Units Energy related information
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
- /// micro-joules).
- ///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
- ///
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
- /// Interfaces.".
- ///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;
-
-
-/**
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
- Domain.".
-
- @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
- AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618
-
-
-/**
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
-
-
-/**
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
- RAPL Domain.".
-
- @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
- @endcode
-**/
-#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B
-
-
-/**
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
- AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C
-
-
-/**
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
- refers to processor core frequency).
-
- @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
- AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
- /// reduced below the operating system request due to assertion of
- /// external PROCHOT.
- ///
- UINT32 PROCHOT_Status:1;
- ///
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
- /// operating system request due to a thermal event.
- ///
- UINT32 ThermalStatus:1;
- ///
- /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
- /// reduced below the operating system request due to PBM limit.
- ///
- UINT32 PowerBudgetManagementStatus:1;
- ///
- /// [Bit 3] Platform Configuration Services Status (R0) When set,
- /// frequency is reduced below the operating system request due to PCS
- /// limit.
- ///
- UINT32 PlatformConfigurationServicesStatus:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
- /// When set, frequency is reduced below the operating system request
- /// because the processor has detected that utilization is low.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;
- ///
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
- /// below the operating system request due to a thermal alert from the
- /// Voltage Regulator.
- ///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
- /// reduced below the operating system request due to electrical design
- /// point constraints (e.g. maximum electrical current consumption).
- ///
- UINT32 ElectricalDesignPointStatus:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
- /// below the operating system request due to Multi-Core Turbo limits.
- ///
- UINT32 MultiCoreTurboStatus:1;
- UINT32 Reserved4:2;
- ///
- /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
- /// below max non-turbo P1.
- ///
- UINT32 FrequencyP1Status:1;
- ///
- /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
- /// set, frequency is reduced below max n-core turbo frequency.
- ///
- UINT32 TurboFrequencyLimitingStatus:1;
- ///
- /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
- /// reduced below the operating system request.
- ///
- UINT32 FrequencyLimitingStatus:1;
- ///
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 PROCHOT_Log:1;
- ///
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 ThermalLog:1;
- ///
- /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 PowerBudgetManagementLog:1;
- ///
- /// [Bit 19] Platform Configuration Services Log When set, indicates that
- /// the PCS Status bit has asserted since the log bit was last cleared.
- /// This log bit will remain set until cleared by software writing 0.
- ///
- UINT32 PlatformConfigurationServicesLog:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
- /// indicates that the AUBFC Status bit has asserted since the log bit was
- /// last cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;
- ///
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
- /// Alert Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 VRThermAlertLog:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 ElectricalDesignPointLog:1;
- UINT32 Reserved7:1;
- ///
- /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
- /// Turbo Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 MultiCoreTurboLog:1;
- UINT32 Reserved8:2;
- ///
- /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
- /// Frequency P1 Status bit has asserted since the log bit was last
- /// cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 CoreFrequencyP1Log:1;
- ///
- /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
- /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 TurboFrequencyLimitingLog:1;
- ///
- /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
- /// Frequency Limiting Status bit has asserted since the log bit was last
- /// cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 CoreFrequencyLimitingLog:1;
- UINT32 Reserved9:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;
-
-
-/**
- THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
- ECX=0):EBX.PQM[bit 12] = 1.
-
- @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
- AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
- /// occupancy monitoring all other encoding reserved..
- ///
- UINT32 EventID:8;
- UINT32 Reserved1:24;
- ///
- /// [Bits 41:32] RMID (RW).
- ///
- UINT32 RMID:10;
- UINT32 Reserved2:22;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;
-
-
-/**
- THREAD. Resource Association Register (R/W)..
-
- @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
- AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 9:0] RMID.
- ///
- UINT32 RMID:10;
- UINT32 Reserved1:22;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;
-
-
-/**
- Package. Uncore perfmon per-socket global control.
-
- @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700
-
-
-/**
- Package. Uncore perfmon per-socket global status.
-
- @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701
-
-
-/**
- Package. Uncore perfmon per-socket global configuration.
-
- @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
- AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702
-
-
-/**
- Package. Uncore U-box UCLK fixed counter control.
-
- @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703
-
-
-/**
- Package. Uncore U-box UCLK fixed counter.
-
- @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704
-
-
-/**
- Package. Uncore U-box perfmon event select for U-box counter 0.
-
- @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705
-
-
-/**
- Package. Uncore U-box perfmon event select for U-box counter 1.
-
- @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706
-
-
-/**
- Package. Uncore U-box perfmon U-box wide status.
-
- @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708
-
-
-/**
- Package. Uncore U-box perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709
-
-
-/**
- Package. Uncore U-box perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A
-
-
-/**
- Package. Uncore PCU perfmon for PCU-box-wide control.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710
-
-
-/**
- Package. Uncore PCU perfmon event select for PCU counter 0.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711
-
-
-/**
- Package. Uncore PCU perfmon event select for PCU counter 1.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712
-
-
-/**
- Package. Uncore PCU perfmon event select for PCU counter 2.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713
-
-
-/**
- Package. Uncore PCU perfmon event select for PCU counter 3.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714
-
-
-/**
- Package. Uncore PCU perfmon box-wide filter.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715
-
-
-/**
- Package. Uncore PCU perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716
-
-
-/**
- Package. Uncore PCU perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717
-
-
-/**
- Package. Uncore PCU perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718
-
-
-/**
- Package. Uncore PCU perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719
-
-
-/**
- Package. Uncore PCU perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A
-
-
-/**
- Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
-
- @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720
-
-
-/**
- Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
-
- @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721
-
-
-/**
- Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
-
- @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722
-
-
-/**
- Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
-
- @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723
-
-
-/**
- Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
-
- @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724
-
-
-/**
- Package. Uncore SBo 0 perfmon box-wide filter.
-
- @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725
-
-
-/**
- Package. Uncore SBo 0 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726
-
-
-/**
- Package. Uncore SBo 0 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727
-
-
-/**
- Package. Uncore SBo 0 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728
-
-
-/**
- Package. Uncore SBo 0 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729
-
-
-/**
- Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
-
- @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A
-
-
-/**
- Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
-
- @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B
-
-
-/**
- Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
-
- @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C
-
-
-/**
- Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
-
- @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D
-
-
-/**
- Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
-
- @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E
-
-
-/**
- Package. Uncore SBo 1 perfmon box-wide filter.
-
- @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F
-
-
-/**
- Package. Uncore SBo 1 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730
-
-
-/**
- Package. Uncore SBo 1 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731
-
-
-/**
- Package. Uncore SBo 1 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732
-
-
-/**
- Package. Uncore SBo 1 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733
-
-
-/**
- Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
-
- @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734
-
-
-/**
- Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
-
- @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735
-
-
-/**
- Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
-
- @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736
-
-
-/**
- Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
-
- @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737
-
-
-/**
- Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
-
- @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738
-
-
-/**
- Package. Uncore SBo 2 perfmon box-wide filter.
-
- @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739
-
-
-/**
- Package. Uncore SBo 2 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A
-
-
-/**
- Package. Uncore SBo 2 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B
-
-
-/**
- Package. Uncore SBo 2 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C
-
-
-/**
- Package. Uncore SBo 2 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D
-
-
-/**
- Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
-
- @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E
-
-
-/**
- Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
-
- @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F
-
-
-/**
- Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
-
- @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740
-
-
-/**
- Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
-
- @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741
-
-
-/**
- Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
-
- @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742
-
-
-/**
- Package. Uncore SBo 3 perfmon box-wide filter.
-
- @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743
-
-
-/**
- Package. Uncore SBo 3 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744
-
-
-/**
- Package. Uncore SBo 3 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745
-
-
-/**
- Package. Uncore SBo 3 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746
-
-
-/**
- Package. Uncore SBo 3 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747
-
-
-/**
- Package. Uncore C-box 0 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00
-
-
-/**
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
-
- @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01
-
-
-/**
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
-
- @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02
-
-
-/**
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
-
- @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03
-
-
-/**
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
-
- @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04
-
-
-/**
- Package. Uncore C-box 0 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05
-
-
-/**
- Package. Uncore C-box 0 perfmon box wide filter 1.
-
- @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06
-
-
-/**
- Package. Uncore C-box 0 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07
-
-
-/**
- Package. Uncore C-box 0 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08
-
-
-/**
- Package. Uncore C-box 0 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09
-
-
-/**
- Package. Uncore C-box 0 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A
-
-
-/**
- Package. Uncore C-box 0 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B
-
-
-/**
- Package. Uncore C-box 1 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10
-
-
-/**
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
-
- @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11
-
-
-/**
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
-
- @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12
-
-
-/**
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
-
- @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13
-
-
-/**
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
-
- @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14
-
-
-/**
- Package. Uncore C-box 1 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15
-
-
-/**
- Package. Uncore C-box 1 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16
-
-
-/**
- Package. Uncore C-box 1 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17
-
-
-/**
- Package. Uncore C-box 1 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18
-
-
-/**
- Package. Uncore C-box 1 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19
-
-
-/**
- Package. Uncore C-box 1 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A
-
-
-/**
- Package. Uncore C-box 1 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B
-
-
-/**
- Package. Uncore C-box 2 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20
-
-
-/**
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
-
- @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21
-
-
-/**
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
-
- @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22
-
-
-/**
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
-
- @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23
-
-
-/**
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
-
- @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24
-
-
-/**
- Package. Uncore C-box 2 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25
-
-
-/**
- Package. Uncore C-box 2 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26
-
-
-/**
- Package. Uncore C-box 2 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27
-
-
-/**
- Package. Uncore C-box 2 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28
-
-
-/**
- Package. Uncore C-box 2 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29
-
-
-/**
- Package. Uncore C-box 2 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A
-
-
-/**
- Package. Uncore C-box 2 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B
-
-
-/**
- Package. Uncore C-box 3 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30
-
-
-/**
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
-
- @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31
-
-
-/**
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
-
- @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32
-
-
-/**
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
-
- @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33
-
-
-/**
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
-
- @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34
-
-
-/**
- Package. Uncore C-box 3 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35
-
-
-/**
- Package. Uncore C-box 3 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36
-
-
-/**
- Package. Uncore C-box 3 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37
-
-
-/**
- Package. Uncore C-box 3 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38
-
-
-/**
- Package. Uncore C-box 3 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39
-
-
-/**
- Package. Uncore C-box 3 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A
-
-
-/**
- Package. Uncore C-box 3 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B
-
-
-/**
- Package. Uncore C-box 4 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40
-
-
-/**
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
-
- @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41
-
-
-/**
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
-
- @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42
-
-
-/**
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
-
- @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43
-
-
-/**
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
-
- @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44
-
-
-/**
- Package. Uncore C-box 4 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45
-
-
-/**
- Package. Uncore C-box 4 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46
-
-
-/**
- Package. Uncore C-box 4 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47
-
-
-/**
- Package. Uncore C-box 4 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48
-
-
-/**
- Package. Uncore C-box 4 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49
-
-
-/**
- Package. Uncore C-box 4 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A
-
-
-/**
- Package. Uncore C-box 4 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B
-
-
-/**
- Package. Uncore C-box 5 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50
-
-
-/**
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
-
- @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51
-
-
-/**
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
-
- @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52
-
-
-/**
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
-
- @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53
-
-
-/**
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
-
- @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54
-
-
-/**
- Package. Uncore C-box 5 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55
-
-
-/**
- Package. Uncore C-box 5 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56
-
-
-/**
- Package. Uncore C-box 5 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57
-
-
-/**
- Package. Uncore C-box 5 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58
-
-
-/**
- Package. Uncore C-box 5 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59
-
-
-/**
- Package. Uncore C-box 5 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A
-
-
-/**
- Package. Uncore C-box 5 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B
-
-
-/**
- Package. Uncore C-box 6 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60
-
-
-/**
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
-
- @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61
-
-
-/**
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
-
- @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62
-
-
-/**
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
-
- @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63
-
-
-/**
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
-
- @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64
-
-
-/**
- Package. Uncore C-box 6 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65
-
-
-/**
- Package. Uncore C-box 6 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66
-
-
-/**
- Package. Uncore C-box 6 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67
-
-
-/**
- Package. Uncore C-box 6 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68
-
-
-/**
- Package. Uncore C-box 6 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69
-
-
-/**
- Package. Uncore C-box 6 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A
-
-
-/**
- Package. Uncore C-box 6 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B
-
-
-/**
- Package. Uncore C-box 7 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70
-
-
-/**
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
-
- @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71
-
-
-/**
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
-
- @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72
-
-
-/**
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
-
- @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73
-
-
-/**
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
-
- @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74
-
-
-/**
- Package. Uncore C-box 7 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75
-
-
-/**
- Package. Uncore C-box 7 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76
-
-
-/**
- Package. Uncore C-box 7 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77
-
-
-/**
- Package. Uncore C-box 7 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78
-
-
-/**
- Package. Uncore C-box 7 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79
-
-
-/**
- Package. Uncore C-box 7 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A
-
-
-/**
- Package. Uncore C-box 7 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B
-
-
-/**
- Package. Uncore C-box 8 perfmon local box wide control.
-
- @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80
-
-
-/**
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
-
- @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81
-
-
-/**
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
-
- @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82
-
-
-/**
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
-
- @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83
-
-
-/**
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
-
- @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84
-
-
-/**
- Package. Uncore C-box 8 perfmon box wide filter0.
-
- @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85
-
-
-/**
- Package. Uncore C-box 8 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86
-
-
-/**
- Package. Uncore C-box 8 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87
-
-
-/**
- Package. Uncore C-box 8 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88
-
-
-/**
- Package. Uncore C-box 8 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89
-
-
-/**
- Package. Uncore C-box 8 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A
-
-
-/**
- Package. Uncore C-box 8 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B
-
-
-/**
- Package. Uncore C-box 9 perfmon local box wide control.
-
- @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90
-
-
-/**
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
-
- @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91
-
-
-/**
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
-
- @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92
-
-
-/**
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
-
- @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93
-
-
-/**
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
-
- @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94
-
-
-/**
- Package. Uncore C-box 9 perfmon box wide filter0.
-
- @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95
-
-
-/**
- Package. Uncore C-box 9 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96
-
-
-/**
- Package. Uncore C-box 9 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97
-
-
-/**
- Package. Uncore C-box 9 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98
-
-
-/**
- Package. Uncore C-box 9 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99
-
-
-/**
- Package. Uncore C-box 9 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A
-
-
-/**
- Package. Uncore C-box 9 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B
-
-
-/**
- Package. Uncore C-box 10 perfmon local box wide control.
-
- @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0
-
-
-/**
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
-
- @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1
-
-
-/**
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
-
- @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2
-
-
-/**
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
-
- @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3
-
-
-/**
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
-
- @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4
-
-
-/**
- Package. Uncore C-box 10 perfmon box wide filter0.
-
- @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5
-
-
-/**
- Package. Uncore C-box 10 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6
-
-
-/**
- Package. Uncore C-box 10 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7
-
-
-/**
- Package. Uncore C-box 10 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8
-
-
-/**
- Package. Uncore C-box 10 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9
-
-
-/**
- Package. Uncore C-box 10 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA
-
-
-/**
- Package. Uncore C-box 10 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB
-
-
-/**
- Package. Uncore C-box 11 perfmon local box wide control.
-
- @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0
-
-
-/**
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
-
- @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1
-
-
-/**
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
-
- @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2
-
-
-/**
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
-
- @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3
-
-
-/**
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
-
- @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4
-
-
-/**
- Package. Uncore C-box 11 perfmon box wide filter0.
-
- @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5
-
-
-/**
- Package. Uncore C-box 11 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6
-
-
-/**
- Package. Uncore C-box 11 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7
-
-
-/**
- Package. Uncore C-box 11 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8
-
-
-/**
- Package. Uncore C-box 11 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9
-
-
-/**
- Package. Uncore C-box 11 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA
-
-
-/**
- Package. Uncore C-box 11 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB
-
-
-/**
- Package. Uncore C-box 12 perfmon local box wide control.
-
- @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0
-
-
-/**
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
-
- @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1
-
-
-/**
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
-
- @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2
-
-
-/**
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
-
- @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3
-
-
-/**
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
-
- @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4
-
-
-/**
- Package. Uncore C-box 12 perfmon box wide filter0.
-
- @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5
-
-
-/**
- Package. Uncore C-box 12 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6
-
-
-/**
- Package. Uncore C-box 12 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7
-
-
-/**
- Package. Uncore C-box 12 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8
-
-
-/**
- Package. Uncore C-box 12 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9
-
-
-/**
- Package. Uncore C-box 12 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA
-
-
-/**
- Package. Uncore C-box 12 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB
-
-
-/**
- Package. Uncore C-box 13 perfmon local box wide control.
-
- @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0
-
-
-/**
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
-
- @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1
-
-
-/**
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
-
- @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2
-
-
-/**
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
-
- @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3
-
-
-/**
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
-
- @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4
-
-
-/**
- Package. Uncore C-box 13 perfmon box wide filter0.
-
- @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5
-
-
-/**
- Package. Uncore C-box 13 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6
-
-
-/**
- Package. Uncore C-box 13 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7
-
-
-/**
- Package. Uncore C-box 13 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8
-
-
-/**
- Package. Uncore C-box 13 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9
-
-
-/**
- Package. Uncore C-box 13 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA
-
-
-/**
- Package. Uncore C-box 13 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB
-
-
-/**
- Package. Uncore C-box 14 perfmon local box wide control.
-
- @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0
-
-
-/**
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
-
- @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1
-
-
-/**
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
-
- @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2
-
-
-/**
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
-
- @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3
-
-
-/**
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
-
- @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4
-
-
-/**
- Package. Uncore C-box 14 perfmon box wide filter0.
-
- @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5
-
-
-/**
- Package. Uncore C-box 14 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6
-
-
-/**
- Package. Uncore C-box 14 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7
-
-
-/**
- Package. Uncore C-box 14 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8
-
-
-/**
- Package. Uncore C-box 14 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9
-
-
-/**
- Package. Uncore C-box 14 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA
-
-
-/**
- Package. Uncore C-box 14 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB
-
-
-/**
- Package. Uncore C-box 15 perfmon local box wide control.
-
- @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0
-
-
-/**
- Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
-
- @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1
-
-
-/**
- Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
-
- @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2
-
-
-/**
- Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
-
- @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3
-
-
-/**
- Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
-
- @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4
-
-
-/**
- Package. Uncore C-box 15 perfmon box wide filter0.
-
- @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5
-
-
-/**
- Package. Uncore C-box 15 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6
-
-
-/**
- Package. Uncore C-box 15 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7
-
-
-/**
- Package. Uncore C-box 15 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8
-
-
-/**
- Package. Uncore C-box 15 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9
-
-
-/**
- Package. Uncore C-box 15 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA
-
-
-/**
- Package. Uncore C-box 15 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB
-
-
-/**
- Package. Uncore C-box 16 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00
-
-
-/**
- Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
-
- @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01
-
-
-/**
- Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
-
- @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02
-
-
-/**
- Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
-
- @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03
-
-
-/**
- Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
-
- @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04
-
-
-/**
- Package. Uncore C-box 16 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05
-
-
-/**
- Package. Uncore C-box 16 perfmon box wide filter 1.
-
- @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06
-
-
-/**
- Package. Uncore C-box 16 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07
-
-
-/**
- Package. Uncore C-box 16 perfmon counter 0.
-
- @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08
-
-
-/**
- Package. Uncore C-box 16 perfmon counter 1.
-
- @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09
-
-
-/**
- Package. Uncore C-box 16 perfmon counter 2.
-
- @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A
-
-
-/**
- Package. Uncore C-box 16 perfmon counter 3.
-
- @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B
-
-
-/**
- Package. Uncore C-box 17 perfmon for box-wide control.
-
- @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10
-
-
-/**
- Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
-
- @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11
-
-
-/**
- Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
-
- @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12
-
-
-/**
- Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
-
- @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13
-
-
-/**
- Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
-
- @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14
-
-
-/**
- Package. Uncore C-box 17 perfmon box wide filter 0.
-
- @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15
-
-
-/**
- Package. Uncore C-box 17 perfmon box wide filter1.
-
- @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16
-
-/**
- Package. Uncore C-box 17 perfmon box wide status.
-
- @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17
-
-
-/**
- Package. Uncore C-box 17 perfmon counter n.
-
- @param ECX MSR_HASWELL_E_C17_PMON_CTRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
- @endcode
- @{
-**/
-#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18
-#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19
-#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A
-#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B
-/// @}
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h deleted file mode 100644 index 78915ec7a4..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h +++ /dev/null @@ -1,2575 +0,0 @@ -/** @file
- MSR Definitions for Intel processors based on the Haswell microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10.
-
-**/
-
-#ifndef __HASWELL_MSR_H__
-#define __HASWELL_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Package.
-
- @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
- AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_PLATFORM_INFO 0x000000CE
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
- /// MHz.
- ///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:12;
- ///
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for
- /// Turbo mode is disabled.
- ///
- UINT32 RatioLimit:1;
- ///
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
- /// and when set to 0, indicates TDP Limit for Turbo mode is not
- /// programmable.
- ///
- UINT32 TDPLimit:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
- /// indicates that LPM is supported, and when set to 0, indicates LPM is
- /// not supported.
- ///
- UINT32 LowPowerModeSupport:1;
- ///
- /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
- /// TDP level available. 01: One additional TDP level available. 02: Two
- /// additional TDP level available. 11: Reserved.
- ///
- UINT32 ConfigTDPLevels:2;
- UINT32 Reserved4:5;
- ///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
- /// minimum ratio (maximum efficiency) that the processor can operates, in
- /// units of 100MHz.
- ///
- UINT32 MaximumEfficiencyRatio:8;
- ///
- /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
- /// minimum supported operating ratio in units of 100 MHz.
- ///
- UINT32 MinimumOperatingRatio:8;
- UINT32 Reserved5:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_PLATFORM_INFO_REGISTER;
-
-
-/**
- THREAD. Performance Event Select for Counter n (R/W) Supports all fields
- described inTable 35-2 and the fields below.
-
- @param ECX MSR_HASWELL_IA32_PERFEVTSELn
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186
-#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187
-#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,
- #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Event Select: Selects a performance event logic unit.
- ///
- UINT32 EventSelect:8;
- ///
- /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
- /// detect on the selected event logic.
- ///
- UINT32 UMASK:8;
- ///
- /// [Bit 16] USR: Counts while in privilege level is not ring 0.
- ///
- UINT32 USR:1;
- ///
- /// [Bit 17] OS: Counts while in privilege level is ring 0.
- ///
- UINT32 OS:1;
- ///
- /// [Bit 18] Edge: Enables edge detection if set.
- ///
- UINT32 E:1;
- ///
- /// [Bit 19] PC: enables pin control.
- ///
- UINT32 PC:1;
- ///
- /// [Bit 20] INT: enables interrupt on counter overflow.
- ///
- UINT32 INT:1;
- ///
- /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR.
- ///
- UINT32 ANY:1;
- ///
- /// [Bit 22] EN: enables the corresponding performance counter to commence
- /// counting when this bit is set.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 23] INV: invert the CMASK.
- ///
- UINT32 INV:1;
- ///
- /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
- /// performance counter increments each cycle if the event count is
- /// greater than or equal to the CMASK.
- ///
- UINT32 CMASK:8;
- UINT32 Reserved:32;
- ///
- /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,
- /// AnyThread (bit 21) should be cleared to prevent incorrect results.
- ///
- UINT32 IN_TX:1;
- UINT32 Reserved2:31;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;
-
-
-/**
- THREAD. Performance Event Select for Counter 2 (R/W) Supports all fields
- described inTable 35-2 and the fields below.
-
- @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
- AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Event Select: Selects a performance event logic unit.
- ///
- UINT32 EventSelect:8;
- ///
- /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
- /// detect on the selected event logic.
- ///
- UINT32 UMASK:8;
- ///
- /// [Bit 16] USR: Counts while in privilege level is not ring 0.
- ///
- UINT32 USR:1;
- ///
- /// [Bit 17] OS: Counts while in privilege level is ring 0.
- ///
- UINT32 OS:1;
- ///
- /// [Bit 18] Edge: Enables edge detection if set.
- ///
- UINT32 E:1;
- ///
- /// [Bit 19] PC: enables pin control.
- ///
- UINT32 PC:1;
- ///
- /// [Bit 20] INT: enables interrupt on counter overflow.
- ///
- UINT32 INT:1;
- ///
- /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR.
- ///
- UINT32 ANY:1;
- ///
- /// [Bit 22] EN: enables the corresponding performance counter to commence
- /// counting when this bit is set.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 23] INV: invert the CMASK.
- ///
- UINT32 INV:1;
- ///
- /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
- /// performance counter increments each cycle if the event count is
- /// greater than or equal to the CMASK.
- ///
- UINT32 CMASK:8;
- UINT32 Reserved:32;
- ///
- /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,
- /// AnyThread (bit 21) should be cleared to prevent incorrect results.
- ///
- UINT32 IN_TX:1;
- ///
- /// [Bit 33] IN_TXCP: see Section 18.11.5.1 When IN_TXCP=1 & IN_TX=1 and
- /// in sampling, spurious PMI may occur and transactions may continuously
- /// abort near overflow conditions. Software should favor using IN_TXCP
- /// for counting over sampling. If sampling, software should use large
- /// "sample-after" value after clearing the counter configured to use
- /// IN_TXCP and also always reset the counter even when no overflow
- /// condition was reported.
- ///
- UINT32 IN_TXCP:1;
- UINT32 Reserved2:30;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;
-
-
-/**
- Thread. Last Branch Record Filtering Select Register (R/W).
-
- @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_LBR_SELECT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
- AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_LBR_SELECT 0x000001C8
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] CPL_EQ_0.
- ///
- UINT32 CPL_EQ_0:1;
- ///
- /// [Bit 1] CPL_NEQ_0.
- ///
- UINT32 CPL_NEQ_0:1;
- ///
- /// [Bit 2] JCC.
- ///
- UINT32 JCC:1;
- ///
- /// [Bit 3] NEAR_REL_CALL.
- ///
- UINT32 NEAR_REL_CALL:1;
- ///
- /// [Bit 4] NEAR_IND_CALL.
- ///
- UINT32 NEAR_IND_CALL:1;
- ///
- /// [Bit 5] NEAR_RET.
- ///
- UINT32 NEAR_RET:1;
- ///
- /// [Bit 6] NEAR_IND_JMP.
- ///
- UINT32 NEAR_IND_JMP:1;
- ///
- /// [Bit 7] NEAR_REL_JMP.
- ///
- UINT32 NEAR_REL_JMP:1;
- ///
- /// [Bit 8] FAR_BRANCH.
- ///
- UINT32 FAR_BRANCH:1;
- ///
- /// [Bit 9] EN_CALL_STACK.
- ///
- UINT32 EN_CALL_STACK:1;
- UINT32 Reserved1:22;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_LBR_SELECT_REGISTER;
-
-
-/**
- Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines
- the interrupt response time limit used by the processor to manage transition
- to package C6 or C7 state. The latency programmed in this register is for
- the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.
- Note: C-state values are processor specific C-state code names, unrelated to
- MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
- AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_PKGC_IRTL1 0x0000060B
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
- /// that should be used to decide if the package should be put into a
- /// package C6 or C7 state.
- ///
- UINT32 InterruptResponseTimeLimit:10;
- ///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. The following time unit
- /// encodings are supported:
- ///
- /// 000b: 1 ns
- /// 001b: 32 ns
- /// 010b: 1024 ns
- /// 011b: 32768 ns
- /// 100b: 1048576 ns
- /// 101b: 33554432 ns.
- ///
- UINT32 TimeUnit:3;
- UINT32 Reserved1:2;
- ///
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
- /// valid and can be used by the processor for package C-sate management.
- ///
- UINT32 Valid:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_PKGC_IRTL1_REGISTER;
-
-
-/**
- Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines
- the interrupt response time limit used by the processor to manage transition
- to package C6 or C7 state. The latency programmed in this register is for
- the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.
- Note: C-state values are processor specific C-state code names, unrelated to
- MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
- AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_PKGC_IRTL2 0x0000060C
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
- /// that should be used to decide if the package should be put into a
- /// package C6 or C7 state.
- ///
- UINT32 InterruptResponseTimeLimit:10;
- ///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. The following time unit
- /// encodings are supported:
- ///
- /// 000b: 1 ns
- /// 001b: 32 ns
- /// 010b: 1024 ns
- /// 011b: 32768 ns
- /// 100b: 1048576 ns
- /// 101b: 33554432 ns.
- ///
- UINT32 TimeUnit:3;
- UINT32 Reserved1:2;
- ///
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
- /// valid and can be used by the processor for package C-sate management.
- ///
- UINT32 Valid:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_PKGC_IRTL2_REGISTER;
-
-
-/**
- Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
-
- @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
- @endcode
-**/
-#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613
-
-
-/**
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619
-
-
-/**
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
- RAPL Domain.".
-
- @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
- @endcode
-**/
-#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B
-
-
-/**
- Package. Base TDP Ratio (R/O).
-
- @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
- @endcode
-**/
-#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
- /// specific processor (in units of 100 MHz).
- ///
- UINT32 Config_TDP_Base:8;
- UINT32 Reserved1:24;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;
-
-
-/**
- Package. ConfigTDP Level 1 ratio and power level (R/O).
-
- @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
- @endcode
-**/
-#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
- ///
- UINT32 PKG_TDP_LVL1:15;
- UINT32 Reserved1:1;
- ///
- /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
- /// for this specific processor.
- ///
- UINT32 Config_TDP_LVL1_Ratio:8;
- UINT32 Reserved2:8;
- ///
- /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
- /// Level 1.
- ///
- UINT32 PKG_MAX_PWR_LVL1:15;
- ///
- /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
- /// Level 1.
- ///
- UINT32 PKG_MIN_PWR_LVL1:16;
- UINT32 Reserved3:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;
-
-
-/**
- Package. ConfigTDP Level 2 ratio and power level (R/O).
-
- @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
- @endcode
-**/
-#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
- ///
- UINT32 PKG_TDP_LVL2:15;
- UINT32 Reserved1:1;
- ///
- /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
- /// for this specific processor.
- ///
- UINT32 Config_TDP_LVL2_Ratio:8;
- UINT32 Reserved2:8;
- ///
- /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
- /// Level 2.
- ///
- UINT32 PKG_MAX_PWR_LVL2:15;
- ///
- /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
- /// Level 2.
- ///
- UINT32 PKG_MIN_PWR_LVL2:16;
- UINT32 Reserved3:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;
-
-
-/**
- Package. ConfigTDP Control (R/W).
-
- @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
- AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
- ///
- UINT32 TDP_LEVEL:2;
- UINT32 Reserved1:29;
- ///
- /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
- /// this register is locked until a reset.
- ///
- UINT32 Config_TDP_Lock:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;
-
-
-/**
- Package. ConfigTDP Control (R/W).
-
- @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
- AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
- /// field.
- ///
- UINT32 MAX_NON_TURBO_RATIO:8;
- UINT32 Reserved1:23;
- ///
- /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
- /// content of this register is locked until a reset.
- ///
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;
-
-
-/**
- Package. Silicon Debug Feature Control (R/W) See Table 35-2.
-
- @param ECX MSR_HASWELL_IA32_DEBUG_FEATURE (0x00000C80)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);
- AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);
- @endcode
-**/
-#define MSR_HASWELL_IA32_DEBUG_FEATURE 0x00000C80
-
-
-/**
- Core. C-State Configuration Control (R/W) Note: C-state values are processor
- specific C-state code names, unrelated to MWAIT extension C-state parameters
- or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.
-
- @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
- /// processor-specific C-state code name (consuming the least power) for
- /// the package. The default is set as factory-configured package C-state
- /// limit. The following C-state code name encodings are supported: 0000b:
- /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
- /// 0100b: C7 0101b: C7s Package C states C7 are not available to
- /// processor with signature 06_3CH.
- ///
- UINT32 Limit:4;
- UINT32 Reserved1:6;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO).
- ///
- UINT32 CFGLock:1;
- UINT32 Reserved3:9;
- ///
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).
- ///
- UINT32 C3AutoDemotion:1;
- ///
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).
- ///
- UINT32 C1AutoDemotion:1;
- ///
- /// [Bit 27] Enable C3 Undemotion (R/W).
- ///
- UINT32 C3Undemotion:1;
- ///
- /// [Bit 28] Enable C1 Undemotion (R/W).
- ///
- UINT32 C1Undemotion:1;
- UINT32 Reserved4:3;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
- Enhancement. Accessible only while in SMM.
-
- @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
- AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:26;
- ///
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
- /// SMM code access restriction is supported and the
- /// MSR_SMM_FEATURE_CONTROL is supported.
- ///
- UINT32 SMM_Code_Access_Chk:1;
- ///
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
- /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
- /// supported.
- ///
- UINT32 Long_Flow_Indication:1;
- UINT32 Reserved3:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_SMM_MCA_CAP_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);
- @endcode
-**/
-#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
- /// limit of 1 core active.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
- /// limit of 2 core active.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
- /// limit of 3 core active.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
- /// limit of 4 core active.
- ///
- UINT32 Maximum4C:8;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Package. Uncore PMU global control.
-
- @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
- AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Core 0 select.
- ///
- UINT32 PMI_Sel_Core0:1;
- ///
- /// [Bit 1] Core 1 select.
- ///
- UINT32 PMI_Sel_Core1:1;
- ///
- /// [Bit 2] Core 2 select.
- ///
- UINT32 PMI_Sel_Core2:1;
- ///
- /// [Bit 3] Core 3 select.
- ///
- UINT32 PMI_Sel_Core3:1;
- UINT32 Reserved1:15;
- UINT32 Reserved2:10;
- ///
- /// [Bit 29] Enable all uncore counters.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 30] Enable wake on PMI.
- ///
- UINT32 WakePMI:1;
- ///
- /// [Bit 31] Enable Freezing counter when overflow.
- ///
- UINT32 FREEZE:1;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;
-
-
-/**
- Package. Uncore PMU main status.
-
- @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Fixed counter overflowed.
- ///
- UINT32 Fixed:1;
- ///
- /// [Bit 1] An ARB counter overflowed.
- ///
- UINT32 ARB:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 3] A CBox counter overflowed (on any slice).
- ///
- UINT32 CBox:1;
- UINT32 Reserved2:28;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;
-
-
-/**
- Package. Uncore fixed counter control (R/W).
-
- @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
- AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:20;
- ///
- /// [Bit 20] Enable overflow propagation.
- ///
- UINT32 EnableOverflow:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 22] Enable counting.
- ///
- UINT32 EnableCounting:1;
- UINT32 Reserved3:9;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;
-
-
-/**
- Package. Uncore fixed counter.
-
- @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
- AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Current count.
- ///
- UINT32 CurrentCount:32;
- ///
- /// [Bits 47:32] Current count.
- ///
- UINT32 CurrentCountHi:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;
-
-
-/**
- Package. Uncore C-Box configuration information (R/O).
-
- @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
- ///
- UINT32 CBox:4;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;
-
-
-/**
- Package. Uncore Arb unit, performance counter 0.
-
- @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0
-
-
-/**
- Package. Uncore Arb unit, performance counter 1.
-
- @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1
-
-
-/**
- Package. Uncore Arb unit, counter 0 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2
-
-
-/**
- Package. Uncore Arb unit, counter 1 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3
-
-
-/**
- Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
- Enhancement. Accessible only while in SMM.
-
- @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
- AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
- /// further changes.
- ///
- UINT32 Lock:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
- /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
- /// logical processors are prevented from executing SMM code outside the
- /// ranges defined by the SMRR. When set to '1' any logical processor in
- /// the package that attempts to execute SMM code not within the ranges
- /// defined by the SMRR will assert an unrecoverable MCE.
- ///
- UINT32 SMM_Code_Chk_En:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;
-
-
-/**
- Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
- processors in the package. Available only while in SMM and
- MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
-
- [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
- processor of its state in a long flow of internal operation which
- delays servicing an interrupt. The corresponding bit will be set at
- the start of long events such as: Microcode Update Load, C6, WBINVD,
- Ratio Change, Throttle. The bit is automatically cleared at the end of
- each long event. The reset value of this field is 0. Only bit
- positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
- updated.
-
- [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
- processor of its state in a long flow of internal operation which
- delays servicing an interrupt. The corresponding bit will be set at
- the start of long events such as: Microcode Update Load, C6, WBINVD,
- Ratio Change, Throttle. The bit is automatically cleared at the end of
- each long event. The reset value of this field is 0. Only bit
- positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
- updated.
-
- @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);
- @endcode
-**/
-#define MSR_HASWELL_SMM_DELAYED 0x000004E2
-
-
-/**
- Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
- processors in the package. Available only while in SMM.
-
- [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
- processor of its blocked state to service an SMI. The corresponding
- bit will be set if the logical processor is in one of the following
- states: Wait For SIPI or SENTER Sleep. The reset value of this field
- is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
- ECX=PKG_LVL):EBX[15:0] can be updated.
-
-
- [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
- processor of its blocked state to service an SMI. The corresponding
- bit will be set if the logical processor is in one of the following
- states: Wait For SIPI or SENTER Sleep. The reset value of this field
- is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
- ECX=PKG_LVL):EBX[15:0] can be updated.
-
- @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);
- @endcode
-**/
-#define MSR_HASWELL_SMM_BLOCKED 0x000004E3
-
-
-/**
- Package. Unit Multipliers used in RAPL Interfaces (R/O).
-
- @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);
- @endcode
-**/
-#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
- ///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
- ///
- /// [Bits 12:8] Package. Energy Status Units Energy related information
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
- /// micro-joules).
- ///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
- ///
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
- /// Interfaces.".
- ///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;
-
-
-/**
- Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
- RAPL Domains.".
-
- @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
- AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640
-
-
-/**
- Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
- Domains.".
-
- @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641
-
-
-/**
- Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
- Domains.".
-
- @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
- AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);
- @endcode
-**/
-#define MSR_HASWELL_PP1_POLICY 0x00000642
-
-
-/**
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
- refers to processor core frequency).
-
- @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
- AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
- /// reduced below the operating system request due to assertion of
- /// external PROCHOT.
- ///
- UINT32 PROCHOT_Status:1;
- ///
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
- /// operating system request due to a thermal event.
- ///
- UINT32 ThermalStatus:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
- /// below the operating system request due to Processor Graphics driver
- /// override.
- ///
- UINT32 GraphicsDriverStatus:1;
- ///
- /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
- /// When set, frequency is reduced below the operating system request
- /// because the processor has detected that utilization is low.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;
- ///
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
- /// below the operating system request due to a thermal alert from the
- /// Voltage Regulator.
- ///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
- /// reduced below the operating system request due to electrical design
- /// point constraints (e.g. maximum electrical current consumption).
- ///
- UINT32 ElectricalDesignPointStatus:1;
- ///
- /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
- /// below the operating system request due to domain-level power limiting.
- ///
- UINT32 PLStatus:1;
- ///
- /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
- /// frequency is reduced below the operating system request due to
- /// package-level power limiting PL1.
- ///
- UINT32 PL1Status:1;
- ///
- /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
- /// frequency is reduced below the operating system request due to
- /// package-level power limiting PL2.
- ///
- UINT32 PL2Status:1;
- ///
- /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
- /// below the operating system request due to multi-core turbo limits.
- ///
- UINT32 MaxTurboLimitStatus:1;
- ///
- /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
- /// is reduced below the operating system request due to Turbo transition
- /// attenuation. This prevents performance degradation due to frequent
- /// operating ratio changes.
- ///
- UINT32 TurboTransitionAttenuationStatus:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 PROCHOT_Log:1;
- ///
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 ThermalLog:1;
- UINT32 Reserved4:2;
- ///
- /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
- /// Driver Status bit has asserted since the log bit was last cleared.
- /// This log bit will remain set until cleared by software writing 0.
- ///
- UINT32 GraphicsDriverLog:1;
- ///
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
- /// indicates that the Autonomous Utilization-Based Frequency Control
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;
- ///
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
- /// Alert Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 VRThermAlertLog:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 ElectricalDesignPointLog:1;
- ///
- /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
- /// Power Limiting Status bit has asserted since the log bit was last
- /// cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 PLLog:1;
- ///
- /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
- /// that the Package Level PL1 Power Limiting Status bit has asserted
- /// since the log bit was last cleared. This log bit will remain set until
- /// cleared by software writing 0.
- ///
- UINT32 PL1Log:1;
- ///
- /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
- /// the Package Level PL2 Power Limiting Status bit has asserted since the
- /// log bit was last cleared. This log bit will remain set until cleared
- /// by software writing 0.
- ///
- UINT32 PL2Log:1;
- ///
- /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
- /// Limit Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 MaxTurboLimitLog:1;
- ///
- /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
- /// Turbo Transition Attenuation Status bit has asserted since the log bit
- /// was last cleared. This log bit will remain set until cleared by
- /// software writing 0.
- ///
- UINT32 TurboTransitionAttenuationLog:1;
- UINT32 Reserved6:2;
- UINT32 Reserved7:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;
-
-
-/**
- Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
- (frequency refers to processor graphics frequency).
-
- @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
- AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
-
-/**
- MSR information returned for MSR index
- #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
- /// operating system request due to assertion of external PROCHOT.
- ///
- UINT32 PROCHOT_Status:1;
- ///
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
- /// operating system request due to a thermal event.
- ///
- UINT32 ThermalStatus:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
- /// below the operating system request due to Processor Graphics driver
- /// override.
- ///
- UINT32 GraphicsDriverStatus:1;
- ///
- /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
- /// When set, frequency is reduced below the operating system request
- /// because the processor has detected that utilization is low.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;
- ///
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
- /// below the operating system request due to a thermal alert from the
- /// Voltage Regulator.
- ///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
- /// reduced below the operating system request due to electrical design
- /// point constraints (e.g. maximum electrical current consumption).
- ///
- UINT32 ElectricalDesignPointStatus:1;
- ///
- /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is
- /// reduced below the operating system request due to domain-level power
- /// limiting.
- ///
- UINT32 GraphicsPowerLimitingStatus:1;
- ///
- /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
- /// frequency is reduced below the operating system request due to
- /// package-level power limiting PL1.
- ///
- UINT32 PL1STatus:1;
- ///
- /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
- /// frequency is reduced below the operating system request due to
- /// package-level power limiting PL2.
- ///
- UINT32 PL2Status:1;
- UINT32 Reserved3:4;
- ///
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 PROCHOT_Log:1;
- ///
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 ThermalLog:1;
- UINT32 Reserved4:2;
- ///
- /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
- /// Driver Status bit has asserted since the log bit was last cleared.
- /// This log bit will remain set until cleared by software writing 0.
- ///
- UINT32 GraphicsDriverLog:1;
- ///
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
- /// indicates that the Autonomous Utilization-Based Frequency Control
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;
- ///
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
- /// Alert Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 VRThermAlertLog:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 ElectricalDesignPointLog:1;
- ///
- /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
- /// Power Limiting Status bit has asserted since the log bit was last
- /// cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 CorePowerLimitingLog:1;
- ///
- /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
- /// that the Package Level PL1 Power Limiting Status bit has asserted
- /// since the log bit was last cleared. This log bit will remain set until
- /// cleared by software writing 0.
- ///
- UINT32 PL1Log:1;
- ///
- /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
- /// the Package Level PL2 Power Limiting Status bit has asserted since the
- /// log bit was last cleared. This log bit will remain set until cleared
- /// by software writing 0.
- ///
- UINT32 PL2Log:1;
- ///
- /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
- /// Limit Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 MaxTurboLimitLog:1;
- ///
- /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
- /// Turbo Transition Attenuation Status bit has asserted since the log bit
- /// was last cleared. This log bit will remain set until cleared by
- /// software writing 0.
- ///
- UINT32 TurboTransitionAttenuationLog:1;
- UINT32 Reserved6:2;
- UINT32 Reserved7:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;
-
-
-/**
- Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
- (frequency refers to ring interconnect in the uncore).
-
- @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
- AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
- /// operating system request due to assertion of external PROCHOT.
- ///
- UINT32 PROCHOT_Status:1;
- ///
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
- /// operating system request due to a thermal event.
- ///
- UINT32 ThermalStatus:1;
- UINT32 Reserved1:4;
- ///
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
- /// below the operating system request due to a thermal alert from the
- /// Voltage Regulator.
- ///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
- /// reduced below the operating system request due to electrical design
- /// point constraints (e.g. maximum electrical current consumption).
- ///
- UINT32 ElectricalDesignPointStatus:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
- /// frequency is reduced below the operating system request due to
- /// package-level power limiting PL1.
- ///
- UINT32 PL1STatus:1;
- ///
- /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
- /// frequency is reduced below the operating system request due to
- /// package-level power limiting PL2.
- ///
- UINT32 PL2Status:1;
- UINT32 Reserved4:4;
- ///
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 PROCHOT_Log:1;
- ///
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 ThermalLog:1;
- UINT32 Reserved5:2;
- ///
- /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
- /// Driver Status bit has asserted since the log bit was last cleared.
- /// This log bit will remain set until cleared by software writing 0.
- ///
- UINT32 GraphicsDriverLog:1;
- ///
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
- /// indicates that the Autonomous Utilization-Based Frequency Control
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;
- ///
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
- /// Alert Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 VRThermAlertLog:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 ElectricalDesignPointLog:1;
- ///
- /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
- /// Power Limiting Status bit has asserted since the log bit was last
- /// cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 CorePowerLimitingLog:1;
- ///
- /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
- /// that the Package Level PL1 Power Limiting Status bit has asserted
- /// since the log bit was last cleared. This log bit will remain set until
- /// cleared by software writing 0.
- ///
- UINT32 PL1Log:1;
- ///
- /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
- /// the Package Level PL2 Power Limiting Status bit has asserted since the
- /// log bit was last cleared. This log bit will remain set until cleared
- /// by software writing 0.
- ///
- UINT32 PL2Log:1;
- ///
- /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
- /// Limit Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 MaxTurboLimitLog:1;
- ///
- /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
- /// Turbo Transition Attenuation Status bit has asserted since the log bit
- /// was last cleared. This log bit will remain set until cleared by
- /// software writing 0.
- ///
- UINT32 TurboTransitionAttenuationLog:1;
- UINT32 Reserved7:2;
- UINT32 Reserved8:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;
-
-
-/**
- Package. Uncore C-Box 0, counter 0 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700
-
-
-/**
- Package. Uncore C-Box 0, counter 1 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701
-
-
-/**
- Package. Uncore C-Box 0, performance counter 0.
-
- @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706
-
-
-/**
- Package. Uncore C-Box 0, performance counter 1.
-
- @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707
-
-
-/**
- Package. Uncore C-Box 1, counter 0 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710
-
-
-/**
- Package. Uncore C-Box 1, counter 1 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711
-
-
-/**
- Package. Uncore C-Box 1, performance counter 0.
-
- @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716
-
-
-/**
- Package. Uncore C-Box 1, performance counter 1.
-
- @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717
-
-
-/**
- Package. Uncore C-Box 2, counter 0 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720
-
-
-/**
- Package. Uncore C-Box 2, counter 1 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721
-
-
-/**
- Package. Uncore C-Box 2, performance counter 0.
-
- @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726
-
-
-/**
- Package. Uncore C-Box 2, performance counter 1.
-
- @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727
-
-
-/**
- Package. Uncore C-Box 3, counter 0 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730
-
-
-/**
- Package. Uncore C-Box 3, counter 1 event select MSR.
-
- @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731
-
-
-/**
- Package. Uncore C-Box 3, performance counter 0.
-
- @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736
-
-
-/**
- Package. Uncore C-Box 3, performance counter 1.
-
- @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
- AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
- /// that this package is in processor-specific C8 states. Count at the
- /// same frequency as the TSC.
- ///
- UINT32 C8ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C8 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C8ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
- AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
- /// that this package is in processor-specific C9 states. Count at the
- /// same frequency as the TSC.
- ///
- UINT32 C9ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C9 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C9ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
- AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);
- @endcode
-**/
-#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632
-
-/**
- MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C10 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C10ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C10 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C10ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h deleted file mode 100644 index 0b08c0a8c6..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h +++ /dev/null @@ -1,2830 +0,0 @@ -/** @file
- MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9.
-
-**/
-
-#ifndef __IVY_BRIDGE_MSR_H__
-#define __IVY_BRIDGE_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Package. See http://biosbits.org.
-
- @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
- /// MHz.
- ///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:12;
- ///
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for
- /// Turbo mode is disabled.
- ///
- UINT32 RatioLimit:1;
- ///
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
- /// and when set to 0, indicates TDP Limit for Turbo mode is not
- /// programmable.
- ///
- UINT32 TDPLimit:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
- /// indicates that LPM is supported, and when set to 0, indicates LPM is
- /// not supported.
- ///
- UINT32 LowPowerModeSupport:1;
- ///
- /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
- /// TDP level available. 01: One additional TDP level available. 02: Two
- /// additional TDP level available. 11: Reserved.
- ///
- UINT32 ConfigTDPLevels:2;
- UINT32 Reserved4:5;
- ///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
- /// minimum ratio (maximum efficiency) that the processor can operates, in
- /// units of 100MHz.
- ///
- UINT32 MaximumEfficiencyRatio:8;
- ///
- /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
- /// minimum supported operating ratio in units of 100 MHz.
- ///
- UINT32 MinimumOperatingRatio:8;
- UINT32 Reserved5:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
-
-
-/**
- Core. C-State Configuration Control (R/W) Note: C-state values are
- processor specific C-state code names, unrelated to MWAIT extension C-state
- parameters or ACPI C-States. See http://biosbits.org.
-
- @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
- /// processor-specific C-state code name (consuming the least power). for
- /// the package. The default is set as factory-configured package C-state
- /// limit. The following C-state code name encodings are supported: 000b:
- /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
- /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
- /// This field cannot be used to limit package C-state to C3.
- ///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
- /// IO_read instructions sent to IO register specified by
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
- /// until next reset.
- ///
- UINT32 CFGLock:1;
- UINT32 Reserved3:9;
- ///
- /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
- /// will conditionally demote C6/C7 requests to C3 based on uncore
- /// auto-demote information.
- ///
- UINT32 C3AutoDemotion:1;
- ///
- /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
- /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
- /// auto-demote information.
- ///
- UINT32 C1AutoDemotion:1;
- ///
- /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
- /// demoted C3.
- ///
- UINT32 C3Undemotion:1;
- ///
- /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
- /// demoted C1.
- ///
- UINT32 C1Undemotion:1;
- UINT32 Reserved4:3;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- Package. Base TDP Ratio (R/O).
-
- @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
- /// specific processor (in units of 100 MHz).
- ///
- UINT32 Config_TDP_Base:8;
- UINT32 Reserved1:24;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;
-
-
-/**
- Package. ConfigTDP Level 1 ratio and power level (R/O).
-
- @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
- ///
- UINT32 PKG_TDP_LVL1:15;
- UINT32 Reserved1:1;
- ///
- /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
- /// for this specific processor.
- ///
- UINT32 Config_TDP_LVL1_Ratio:8;
- UINT32 Reserved2:8;
- ///
- /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
- /// Level 1.
- ///
- UINT32 PKG_MAX_PWR_LVL1:15;
- UINT32 Reserved3:1;
- ///
- /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
- /// Level 1.
- ///
- UINT32 PKG_MIN_PWR_LVL1:15;
- UINT32 Reserved4:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;
-
-
-/**
- Package. ConfigTDP Level 2 ratio and power level (R/O).
-
- @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
- ///
- UINT32 PKG_TDP_LVL2:15;
- UINT32 Reserved1:1;
- ///
- /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
- /// for this specific processor.
- ///
- UINT32 Config_TDP_LVL2_Ratio:8;
- UINT32 Reserved2:8;
- ///
- /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
- /// Level 2.
- ///
- UINT32 PKG_MAX_PWR_LVL2:15;
- UINT32 Reserved3:1;
- ///
- /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
- /// Level 2.
- ///
- UINT32 PKG_MIN_PWR_LVL2:15;
- UINT32 Reserved4:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;
-
-
-/**
- Package. ConfigTDP Control (R/W).
-
- @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
- ///
- UINT32 TDP_LEVEL:2;
- UINT32 Reserved1:29;
- ///
- /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
- /// this register is locked until a reset.
- ///
- UINT32 Config_TDP_Lock:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;
-
-
-/**
- Package. ConfigTDP Control (R/W).
-
- @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
- /// field.
- ///
- UINT32 MAX_NON_TURBO_RATIO:8;
- UINT32 Reserved1:23;
- ///
- /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
- /// content of this register is locked until a reset.
- ///
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;
-
-
-/**
- Package. Protected Processor Inventory Number Enable Control (R/W).
-
- @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.
- /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit
- /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to
- /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged
- /// inventory initialization agent to access MSR_PPIN. After reading
- /// MSR_PPIN, the privileged inventory initialization agent should write
- /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
- /// prevent unauthorized modification to MSR_PPIN_CTL.
- ///
- UINT32 LockOut:1;
- ///
- /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
- /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
- /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
- /// is 0.
- ///
- UINT32 Enable_PPIN:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;
-
-
-/**
- Package. Protected Processor Inventory Number (R/O). Protected Processor
- Inventory Number (R/O) A unique value within a given CPUID
- family/model/stepping signature that a privileged inventory initialization
- agent can access to identify each physical processor, when access to
- MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
- MSR_PPIN_CTL[bits 1:0] = '10b'.
-
- @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PPIN 0x0000004F
-
-
-/**
- Package. See http://biosbits.org.
-
- @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
- /// MHz.
- ///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:7;
- ///
- /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
- /// Protected Processor Inventory Number (PPIN) capability can be enabled
- /// for privileged system inventory agent to read PPIN from MSR_PPIN. When
- /// set to 0, PPIN capability is not supported. An attempt to access
- /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
- ///
- UINT32 PPIN_CAP:1;
- UINT32 Reserved3:4;
- ///
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for
- /// Turbo mode is disabled.
- ///
- UINT32 RatioLimit:1;
- ///
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
- /// and when set to 0, indicates TDP Limit for Turbo mode is not
- /// programmable.
- ///
- UINT32 TDPLimit:1;
- ///
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,
- /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
- /// specify an temperature offset.
- ///
- UINT32 TJOFFSET:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:8;
- ///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
- /// minimum ratio (maximum efficiency) that the processor can operates, in
- /// units of 100MHz.
- ///
- UINT32 MaximumEfficiencyRatio:8;
- UINT32 Reserved6:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;
-
-
-/**
- Package. MC Bank Error Configuration (R/W).
-
- @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
- /// to log additional info in bits 36:32.
- ///
- UINT32 MemErrorLogEnable:1;
- UINT32 Reserved2:30;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;
-
-
-/**
- Package.
-
- @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which
- /// PROCHOT# will be asserted. The value is degree C.
- ///
- UINT32 TemperatureTarget:8;
- ///
- /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature
- /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
- /// will assert at the offset target temperature. Write is permitted only
- /// MSR_PLATFORM_INFO.[30] is set.
- ///
- UINT32 TCCActivationOffset:4;
- UINT32 Reserved2:4;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
- /// limit of 9 core active.
- ///
- UINT32 Maximum9C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
- /// limit of 10core active.
- ///
- UINT32 Maximum10C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
- /// limit of 11 core active.
- ///
- UINT32 Maximum11C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
- /// limit of 12 core active.
- ///
- UINT32 Maximum12C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
- /// limit of 13 core active.
- ///
- UINT32 Maximum13C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
- /// limit of 14 core active.
- ///
- UINT32 Maximum14C:8;
- ///
- /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
- /// limit of 15 core active.
- ///
- UINT32 Maximum15C:8;
- UINT32 Reserved:7;
- ///
- /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
- /// the processor uses override configuration specified in
- /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
- /// uses factory-set configuration (Default).
- ///
- UINT32 TurboRatioLimitConfigurationSemaphore:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.". Bank MC5 reports MC error from the Intel
- QPI module.
-
- * Bank MC6 reports MC error from the integrated I/O module.
- * Banks MC7 and MC 8 report MC error from the two home agents.
- * Banks MC9 through MC 16 report MC error from each channel of the integrated
- memory controllers.
- * Banks MC17 through MC31 reports MC error from a specific CBo
- (core broadcast) and its corresponding slice of L3.
-
- @param ECX MSR_IVY_BRIDGE_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);
- @endcode
- @{
-**/
-#define MSR_IVY_BRIDGE_MC5_CTL 0x00000414
-#define MSR_IVY_BRIDGE_MC6_CTL 0x00000418
-#define MSR_IVY_BRIDGE_MC7_CTL 0x0000041C
-#define MSR_IVY_BRIDGE_MC8_CTL 0x00000420
-#define MSR_IVY_BRIDGE_MC9_CTL 0x00000424
-#define MSR_IVY_BRIDGE_MC10_CTL 0x00000428
-#define MSR_IVY_BRIDGE_MC11_CTL 0x0000042C
-#define MSR_IVY_BRIDGE_MC12_CTL 0x00000430
-#define MSR_IVY_BRIDGE_MC13_CTL 0x00000434
-#define MSR_IVY_BRIDGE_MC14_CTL 0x00000438
-#define MSR_IVY_BRIDGE_MC15_CTL 0x0000043C
-#define MSR_IVY_BRIDGE_MC16_CTL 0x00000440
-#define MSR_IVY_BRIDGE_MC17_CTL 0x00000444
-#define MSR_IVY_BRIDGE_MC18_CTL 0x00000448
-#define MSR_IVY_BRIDGE_MC19_CTL 0x0000044C
-#define MSR_IVY_BRIDGE_MC20_CTL 0x00000450
-#define MSR_IVY_BRIDGE_MC21_CTL 0x00000454
-#define MSR_IVY_BRIDGE_MC22_CTL 0x00000458
-#define MSR_IVY_BRIDGE_MC23_CTL 0x0000045C
-#define MSR_IVY_BRIDGE_MC24_CTL 0x00000460
-#define MSR_IVY_BRIDGE_MC25_CTL 0x00000464
-#define MSR_IVY_BRIDGE_MC26_CTL 0x00000468
-#define MSR_IVY_BRIDGE_MC27_CTL 0x0000046C
-#define MSR_IVY_BRIDGE_MC28_CTL 0x00000470
-#define MSR_IVY_BRIDGE_MC29_CTL 0x00000474
-#define MSR_IVY_BRIDGE_MC30_CTL 0x00000478
-#define MSR_IVY_BRIDGE_MC31_CTL 0x0000047C
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- Bank MC20 reports MC error from a specific CBo (core broadcast) and
- its corresponding slice of L3.
-
- @param ECX MSR_IVY_BRIDGE_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_STATUS);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_STATUS, Msr);
- @endcode
- @{
-**/
-#define MSR_IVY_BRIDGE_MC5_STATUS 0x00000415
-#define MSR_IVY_BRIDGE_MC6_STATUS 0x00000419
-#define MSR_IVY_BRIDGE_MC7_STATUS 0x0000041D
-#define MSR_IVY_BRIDGE_MC8_STATUS 0x00000421
-#define MSR_IVY_BRIDGE_MC9_STATUS 0x00000425
-#define MSR_IVY_BRIDGE_MC10_STATUS 0x00000429
-#define MSR_IVY_BRIDGE_MC11_STATUS 0x0000042D
-#define MSR_IVY_BRIDGE_MC12_STATUS 0x00000431
-#define MSR_IVY_BRIDGE_MC13_STATUS 0x00000435
-#define MSR_IVY_BRIDGE_MC14_STATUS 0x00000439
-#define MSR_IVY_BRIDGE_MC15_STATUS 0x0000043D
-#define MSR_IVY_BRIDGE_MC16_STATUS 0x00000441
-#define MSR_IVY_BRIDGE_MC17_STATUS 0x00000445
-#define MSR_IVY_BRIDGE_MC18_STATUS 0x00000449
-#define MSR_IVY_BRIDGE_MC19_STATUS 0x0000044D
-#define MSR_IVY_BRIDGE_MC20_STATUS 0x00000451
-#define MSR_IVY_BRIDGE_MC21_STATUS 0x00000455
-#define MSR_IVY_BRIDGE_MC22_STATUS 0x00000459
-#define MSR_IVY_BRIDGE_MC23_STATUS 0x0000045D
-#define MSR_IVY_BRIDGE_MC24_STATUS 0x00000461
-#define MSR_IVY_BRIDGE_MC25_STATUS 0x00000465
-#define MSR_IVY_BRIDGE_MC26_STATUS 0x00000469
-#define MSR_IVY_BRIDGE_MC27_STATUS 0x0000046D
-#define MSR_IVY_BRIDGE_MC28_STATUS 0x00000471
-#define MSR_IVY_BRIDGE_MC29_STATUS 0x00000475
-#define MSR_IVY_BRIDGE_MC30_STATUS 0x00000479
-#define MSR_IVY_BRIDGE_MC31_STATUS 0x0000047D
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_IVY_BRIDGE_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_ADDR);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_ADDR, Msr);
- @endcode
- @{
-**/
-#define MSR_IVY_BRIDGE_MC5_ADDR 0x00000416
-#define MSR_IVY_BRIDGE_MC6_ADDR 0x0000041A
-#define MSR_IVY_BRIDGE_MC7_ADDR 0x0000041E
-#define MSR_IVY_BRIDGE_MC8_ADDR 0x00000422
-#define MSR_IVY_BRIDGE_MC9_ADDR 0x00000426
-#define MSR_IVY_BRIDGE_MC10_ADDR 0x0000042A
-#define MSR_IVY_BRIDGE_MC11_ADDR 0x0000042E
-#define MSR_IVY_BRIDGE_MC12_ADDR 0x00000432
-#define MSR_IVY_BRIDGE_MC13_ADDR 0x00000436
-#define MSR_IVY_BRIDGE_MC14_ADDR 0x0000043A
-#define MSR_IVY_BRIDGE_MC15_ADDR 0x0000043E
-#define MSR_IVY_BRIDGE_MC16_ADDR 0x00000442
-#define MSR_IVY_BRIDGE_MC17_ADDR 0x00000446
-#define MSR_IVY_BRIDGE_MC18_ADDR 0x0000044A
-#define MSR_IVY_BRIDGE_MC19_ADDR 0x0000044E
-#define MSR_IVY_BRIDGE_MC20_ADDR 0x00000452
-#define MSR_IVY_BRIDGE_MC21_ADDR 0x00000456
-#define MSR_IVY_BRIDGE_MC22_ADDR 0x0000045A
-#define MSR_IVY_BRIDGE_MC23_ADDR 0x0000045E
-#define MSR_IVY_BRIDGE_MC24_ADDR 0x00000462
-#define MSR_IVY_BRIDGE_MC25_ADDR 0x00000466
-#define MSR_IVY_BRIDGE_MC26_ADDR 0x0000046A
-#define MSR_IVY_BRIDGE_MC27_ADDR 0x0000046E
-#define MSR_IVY_BRIDGE_MC28_ADDR 0x00000472
-#define MSR_IVY_BRIDGE_MC29_ADDR 0x00000476
-#define MSR_IVY_BRIDGE_MC30_ADDR 0x0000047A
-#define MSR_IVY_BRIDGE_MC31_ADDR 0x0000047E
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_IVY_BRIDGE_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_MISC);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_MISC, Msr);
- @endcode
- @{
-**/
-#define MSR_IVY_BRIDGE_MC5_MISC 0x00000417
-#define MSR_IVY_BRIDGE_MC6_MISC 0x0000041B
-#define MSR_IVY_BRIDGE_MC7_MISC 0x0000041F
-#define MSR_IVY_BRIDGE_MC8_MISC 0x00000423
-#define MSR_IVY_BRIDGE_MC9_MISC 0x00000427
-#define MSR_IVY_BRIDGE_MC10_MISC 0x0000042B
-#define MSR_IVY_BRIDGE_MC11_MISC 0x0000042F
-#define MSR_IVY_BRIDGE_MC12_MISC 0x00000433
-#define MSR_IVY_BRIDGE_MC13_MISC 0x00000437
-#define MSR_IVY_BRIDGE_MC14_MISC 0x0000043B
-#define MSR_IVY_BRIDGE_MC15_MISC 0x0000043F
-#define MSR_IVY_BRIDGE_MC16_MISC 0x00000443
-#define MSR_IVY_BRIDGE_MC17_MISC 0x00000447
-#define MSR_IVY_BRIDGE_MC18_MISC 0x0000044B
-#define MSR_IVY_BRIDGE_MC19_MISC 0x0000044F
-#define MSR_IVY_BRIDGE_MC20_MISC 0x00000453
-#define MSR_IVY_BRIDGE_MC21_MISC 0x00000457
-#define MSR_IVY_BRIDGE_MC22_MISC 0x0000045B
-#define MSR_IVY_BRIDGE_MC23_MISC 0x0000045F
-#define MSR_IVY_BRIDGE_MC24_MISC 0x00000463
-#define MSR_IVY_BRIDGE_MC25_MISC 0x00000467
-#define MSR_IVY_BRIDGE_MC26_MISC 0x0000046B
-#define MSR_IVY_BRIDGE_MC27_MISC 0x0000046F
-#define MSR_IVY_BRIDGE_MC28_MISC 0x00000473
-#define MSR_IVY_BRIDGE_MC29_MISC 0x00000477
-#define MSR_IVY_BRIDGE_MC30_MISC 0x0000047B
-#define MSR_IVY_BRIDGE_MC31_MISC 0x0000047F
-/// @}
-
-
-/**
- Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
-
- @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 5:0] Recoverable Address LSB.
- ///
- UINT32 RecoverableAddressLSB:6;
- ///
- /// [Bits 8:6] Address Mode.
- ///
- UINT32 AddressMode:3;
- UINT32 Reserved1:7;
- ///
- /// [Bits 31:16] PCI Express Requestor ID.
- ///
- UINT32 PCIExpressRequestorID:16;
- ///
- /// [Bits 39:32] PCI Express Segment Number.
- ///
- UINT32 PCIExpressSegmentNumber:8;
- UINT32 Reserved2:24;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
-
-
-/**
- Package. Package RAPL Perf Status (R/O).
-
- @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613
-
-
-/**
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
- Domain.".
-
- @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
-
-
-/**
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
-
-
-/**
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
- RAPL Domain.".
-
- @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
-
-
-/**
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C
-
-
-/**
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
-
- @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
- ///
- UINT32 PEBS_EN_PMC0:1;
- ///
- /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
- ///
- UINT32 PEBS_EN_PMC1:1;
- ///
- /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
- ///
- UINT32 PEBS_EN_PMC2:1;
- ///
- /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
- ///
- UINT32 PEBS_EN_PMC3:1;
- UINT32 Reserved1:28;
- ///
- /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
- ///
- UINT32 LL_EN_PMC0:1;
- ///
- /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
- ///
- UINT32 LL_EN_PMC1:1;
- ///
- /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
- ///
- UINT32 LL_EN_PMC2:1;
- ///
- /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
- ///
- UINT32 LL_EN_PMC3:1;
- UINT32 Reserved2:28;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;
-
-
-/**
- Package. Uncore perfmon per-socket global control.
-
- @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00
-
-
-/**
- Package. Uncore perfmon per-socket global status.
-
- @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01
-
-
-/**
- Package. Uncore perfmon per-socket global configuration.
-
- @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06
-
-
-/**
- Package. Uncore U-box perfmon U-box wide status.
-
- @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15
-
-
-/**
- Package. Uncore PCU perfmon box wide status.
-
- @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35
-
-
-/**
- Package. Uncore C-box 0 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A
-
-
-/**
- Package. Uncore C-box 1 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A
-
-
-/**
- Package. Uncore C-box 2 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A
-
-
-/**
- Package. Uncore C-box 3 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A
-
-
-/**
- Package. Uncore C-box 4 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A
-
-
-/**
- Package. Uncore C-box 5 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA
-
-
-/**
- Package. Uncore C-box 6 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA
-
-
-/**
- Package. Uncore C-box 7 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA
-
-
-/**
- Package. Uncore C-box 8 perfmon local box wide control.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04
-
-
-/**
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10
-
-
-/**
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11
-
-
-/**
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12
-
-
-/**
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13
-
-
-/**
- Package. Uncore C-box 8 perfmon box wide filter.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14
-
-
-/**
- Package. Uncore C-box 8 perfmon counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16
-
-
-/**
- Package. Uncore C-box 8 perfmon counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17
-
-
-/**
- Package. Uncore C-box 8 perfmon counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18
-
-
-/**
- Package. Uncore C-box 8 perfmon counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19
-
-
-/**
- Package. Uncore C-box 8 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A
-
-
-/**
- Package. Uncore C-box 9 perfmon local box wide control.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24
-
-
-/**
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30
-
-
-/**
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31
-
-
-/**
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32
-
-
-/**
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33
-
-
-/**
- Package. Uncore C-box 9 perfmon box wide filter.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34
-
-
-/**
- Package. Uncore C-box 9 perfmon counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36
-
-
-/**
- Package. Uncore C-box 9 perfmon counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37
-
-
-/**
- Package. Uncore C-box 9 perfmon counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38
-
-
-/**
- Package. Uncore C-box 9 perfmon counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39
-
-
-/**
- Package. Uncore C-box 9 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A
-
-
-/**
- Package. Uncore C-box 10 perfmon local box wide control.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44
-
-
-/**
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50
-
-
-/**
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51
-
-
-/**
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52
-
-
-/**
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53
-
-
-/**
- Package. Uncore C-box 10 perfmon box wide filter.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54
-
-
-/**
- Package. Uncore C-box 10 perfmon counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56
-
-
-/**
- Package. Uncore C-box 10 perfmon counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57
-
-
-/**
- Package. Uncore C-box 10 perfmon counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58
-
-
-/**
- Package. Uncore C-box 10 perfmon counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59
-
-
-/**
- Package. Uncore C-box 10 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A
-
-
-/**
- Package. Uncore C-box 11 perfmon local box wide control.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64
-
-
-/**
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70
-
-
-/**
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71
-
-
-/**
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72
-
-
-/**
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73
-
-
-/**
- Package. Uncore C-box 11 perfmon box wide filter.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74
-
-
-/**
- Package. Uncore C-box 11 perfmon counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76
-
-
-/**
- Package. Uncore C-box 11 perfmon counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77
-
-
-/**
- Package. Uncore C-box 11 perfmon counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78
-
-
-/**
- Package. Uncore C-box 11 perfmon counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79
-
-
-/**
- Package. Uncore C-box 11 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A
-
-
-/**
- Package. Uncore C-box 12 perfmon local box wide control.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84
-
-
-/**
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90
-
-
-/**
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91
-
-
-/**
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92
-
-
-/**
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93
-
-
-/**
- Package. Uncore C-box 12 perfmon box wide filter.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94
-
-
-/**
- Package. Uncore C-box 12 perfmon counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96
-
-
-/**
- Package. Uncore C-box 12 perfmon counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97
-
-
-/**
- Package. Uncore C-box 12 perfmon counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98
-
-
-/**
- Package. Uncore C-box 12 perfmon counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99
-
-
-/**
- Package. Uncore C-box 12 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A
-
-
-/**
- Package. Uncore C-box 13 perfmon local box wide control.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4
-
-
-/**
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0
-
-
-/**
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1
-
-
-/**
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2
-
-
-/**
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3
-
-
-/**
- Package. Uncore C-box 13 perfmon box wide filter.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4
-
-
-/**
- Package. Uncore C-box 13 perfmon counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6
-
-
-/**
- Package. Uncore C-box 13 perfmon counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7
-
-
-/**
- Package. Uncore C-box 13 perfmon counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8
-
-
-/**
- Package. Uncore C-box 13 perfmon counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9
-
-
-/**
- Package. Uncore C-box 13 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA
-
-
-/**
- Package. Uncore C-box 14 perfmon local box wide control.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4
-
-
-/**
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0
-
-
-/**
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1
-
-
-/**
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2
-
-
-/**
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3
-
-
-/**
- Package. Uncore C-box 14 perfmon box wide filter.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4
-
-
-/**
- Package. Uncore C-box 14 perfmon counter 0.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6
-
-
-/**
- Package. Uncore C-box 14 perfmon counter 1.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7
-
-
-/**
- Package. Uncore C-box 14 perfmon counter 2.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8
-
-
-/**
- Package. Uncore C-box 14 perfmon counter 3.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9
-
-
-/**
- Package. Uncore C-box 14 perfmon box wide filter1.
-
- @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
- @endcode
-**/
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h deleted file mode 100644 index cc24a232c5..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h +++ /dev/null @@ -1,7196 +0,0 @@ -/** @file
- MSR Definitions for Intel processors based on the Nehalem microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5.
-
-**/
-
-#ifndef __NEHALEM_MSR_H__
-#define __NEHALEM_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Package. Model Specific Platform ID (R).
-
- @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
- @endcode
-**/
-#define MSR_NEHALEM_PLATFORM_ID 0x00000017
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:18;
- ///
- /// [Bits 52:50] See Table 35-2.
- ///
- UINT32 PlatformId:3;
- UINT32 Reserved3:11;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_PLATFORM_ID_REGISTER;
-
-
-/**
- Thread. SMI Counter (R/O).
-
- @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_SMI_COUNT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
- @endcode
-**/
-#define MSR_NEHALEM_SMI_COUNT 0x00000034
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
- /// RESET.
- ///
- UINT32 SMICount:32;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_SMI_COUNT_REGISTER;
-
-
-/**
- Package. see http://biosbits.org.
-
- @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
- AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
- /// of the frequency that invariant TSC runs at. The invariant TSC
- /// frequency can be computed by multiplying this ratio by 133.33 MHz.
- ///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:12;
- ///
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for
- /// Turbo mode is disabled.
- ///
- UINT32 RatioLimit:1;
- ///
- /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)
- /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are
- /// programmable, and when set to 0, indicates TDC and TDP Limits for
- /// Turbo mode are not programmable.
- ///
- UINT32 TDC_TDPLimit:1;
- UINT32 Reserved3:2;
- UINT32 Reserved4:8;
- ///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
- /// minimum ratio (maximum efficiency) that the processor can operates, in
- /// units of 133.33MHz.
- ///
- UINT32 MaximumEfficiencyRatio:8;
- UINT32 Reserved5:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_PLATFORM_INFO_REGISTER;
-
-
-/**
- Core. C-State Configuration Control (R/W) Note: C-state values are
- processor specific C-state code names, unrelated to MWAIT extension C-state
- parameters or ACPI CStates. See http://biosbits.org.
-
- @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
- /// processor-specific C-state code name (consuming the least power). for
- /// the package. The default is set as factory-configured package C-state
- /// limit. The following C-state code name encodings are supported: 000b:
- /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
- /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package
- /// C-state limit. Note: This field cannot be used to limit package
- /// C-state to C3.
- ///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
- /// IO_read instructions sent to IO register specified by
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
- /// until next reset.
- ///
- UINT32 CFGLock:1;
- UINT32 Reserved3:8;
- ///
- /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores
- /// in a deep C-State will wake only when the event message is destined
- /// for that core. When 0, all processor cores in a deep C-State will wake
- /// for an event message.
- ///
- UINT32 InterruptFiltering:1;
- ///
- /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
- /// will conditionally demote C6/C7 requests to C3 based on uncore
- /// auto-demote information.
- ///
- UINT32 C3AutoDemotion:1;
- ///
- /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
- /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
- /// auto-demote information.
- ///
- UINT32 C1AutoDemotion:1;
- UINT32 Reserved4:5;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- Core. Power Management IO Redirection in C-state (R/W) See
- http://biosbits.org.
-
- @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
- AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
- /// visible to software for IO redirection. If IO MWAIT Redirection is
- /// enabled, reads to this address will be consumed by the power
- /// management logic and decoded to MWAIT instructions. When IO port
- /// address redirection is enabled, this is the IO port address reported
- /// to the OS/software.
- ///
- UINT32 Lvl2Base:16;
- ///
- /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
- /// maximum C-State code name to be included when IO read to MWAIT
- /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
- /// is the max C-State to include 001b - C6 is the max C-State to include
- /// 010b - C7 is the max C-State to include.
- ///
- UINT32 CStateRange:3;
- UINT32 Reserved1:13;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;
-
-
-/**
- Enable Misc. Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
- ///
- /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
- ///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
- ///
- /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
- ///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
- ///
- /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
- ///
- /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
- ///
- UINT32 XD:1;
- UINT32 Reserved9:3;
- ///
- /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
- /// that support Intel Turbo Boost Technology, the turbo mode feature is
- /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
- /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
- /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
- /// the power-on default value is used by BIOS to detect hardware support
- /// of turbo mode. If power-on default value is 1, turbo mode is available
- /// in the processor. If power-on default value is 0, turbo mode is not
- /// available.
- ///
- UINT32 TurboModeDisable:1;
- UINT32 Reserved10:25;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Thread.
-
- @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
- AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
- /// PROCHOT# will be asserted. The value is degree C.
- ///
- UINT32 TemperatureTarget:8;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;
-
-
-/**
- Miscellaneous Feature Control (R/W).
-
- @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
- AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
- /// L2 hardware prefetcher, which fetches additional lines of code or data
- /// into the L2 cache.
- ///
- UINT32 L2HardwarePrefetcherDisable:1;
- ///
- /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
- /// disables the adjacent cache line prefetcher, which fetches the cache
- /// line that comprises a cache line pair (128 bytes).
- ///
- UINT32 L2AdjacentCacheLinePrefetcherDisable:1;
- ///
- /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
- /// the L1 data cache prefetcher, which fetches the next cache line into
- /// L1 data cache.
- ///
- UINT32 DCUHardwarePrefetcherDisable:1;
- ///
- /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
- /// data cache IP prefetcher, which uses sequential load history (based on
- /// instruction Pointer of previous loads) to determine whether to
- /// prefetch additional lines.
- ///
- UINT32 DCUIPPrefetcherDisable:1;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;
-
-
-/**
- Thread. Offcore Response Event Select Register (R/W).
-
- @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
- AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6
-
-
-/**
- See http://biosbits.org.
-
- @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
- AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,
- /// enables hardware coordination of Enhanced Intel Speedstep Technology
- /// request from processor cores; When 1, disables hardware coordination
- /// of Enhanced Intel Speedstep Technology requests.
- ///
- UINT32 EISTHardwareCoordinationDisable:1;
- ///
- /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes
- /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with
- /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by
- /// CPUID.(EAX=06h):ECX[3].
- ///
- UINT32 EnergyPerformanceBiasEnable:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;
-
-
-/**
- See http://biosbits.org.
-
- @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
- AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt
- /// granularity.
- ///
- UINT32 TDPLimit:15;
- ///
- /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0
- /// indicates override is not active, and a value = 1 indicates active.
- ///
- UINT32 TDPLimitOverrideEnable:1;
- ///
- /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp
- /// granularity.
- ///
- UINT32 TDCLimit:15;
- ///
- /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0
- /// indicates override is not active, and a value = 1 indicates active.
- ///
- UINT32 TDCLimitOverrideEnable:1;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
- @endcode
-**/
-#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
- /// limit of 1 core active.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
- /// limit of 2 core active.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
- /// limit of 3 core active.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
- /// limit of 4 core active.
- ///
- UINT32 Maximum4C:8;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Core. Last Branch Record Filtering Select Register (R/W) See Section
- 17.6.2, "Filtering of Last Branch Records.".
-
- @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_LBR_SELECT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
- AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_LBR_SELECT 0x000001C8
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] CPL_EQ_0.
- ///
- UINT32 CPL_EQ_0:1;
- ///
- /// [Bit 1] CPL_NEQ_0.
- ///
- UINT32 CPL_NEQ_0:1;
- ///
- /// [Bit 2] JCC.
- ///
- UINT32 JCC:1;
- ///
- /// [Bit 3] NEAR_REL_CALL.
- ///
- UINT32 NEAR_REL_CALL:1;
- ///
- /// [Bit 4] NEAR_IND_CALL.
- ///
- UINT32 NEAR_IND_CALL:1;
- ///
- /// [Bit 5] NEAR_RET.
- ///
- UINT32 NEAR_RET:1;
- ///
- /// [Bit 6] NEAR_IND_JMP.
- ///
- UINT32 NEAR_IND_JMP:1;
- ///
- /// [Bit 7] NEAR_REL_JMP.
- ///
- UINT32 NEAR_REL_JMP:1;
- ///
- /// [Bit 8] FAR_BRANCH.
- ///
- UINT32 FAR_BRANCH:1;
- UINT32 Reserved1:23;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_LBR_SELECT_REGISTER;
-
-
-/**
- Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
- that points to the MSR containing the most recent branch record. See
- MSR_LASTBRANCH_0_FROM_IP (at 680H).
-
- @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
- last branch instruction that the processor executed prior to the last
- exception that was generated or the last interrupt that was handled.
-
- @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD
-
-
-/**
- Thread. Last Exception Record To Linear IP (R) This area contains a pointer
- to the target of the last branch instruction that the processor executed
- prior to the last exception that was generated or the last interrupt that
- was handled.
-
- @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
- @endcode
-**/
-#define MSR_NEHALEM_LER_TO_LIP 0x000001DE
-
-
-/**
- Core. Power Control Register. See http://biosbits.org.
-
- @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_POWER_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
- AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_POWER_CTL 0x000001FC
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the
- /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
- /// operating point when all execution cores enter MWAIT (C1).
- ///
- UINT32 C1EEnable:1;
- UINT32 Reserved2:30;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_POWER_CTL_REGISTER;
-
-
-/**
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Thread. (RO).
-
- @param ECX MSR_NEHALEM_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STAUS);
- @endcode
-**/
-#define MSR_NEHALEM_PERF_GLOBAL_STAUS 0x0000038E
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STAUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:29;
- ///
- /// [Bit 61] UNC_Ovf Uncore overflowed if 1.
- ///
- UINT32 Ovf_Uncore:1;
- UINT32 Reserved3:2;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER;
-
-
-/**
- Thread. (R/W).
-
- @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:29;
- ///
- /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.
- ///
- UINT32 Ovf_Uncore:1;
- UINT32 Reserved3:2;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;
-
-
-/**
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
-
- @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
- ///
- UINT32 PEBS_EN_PMC0:1;
- ///
- /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
- ///
- UINT32 PEBS_EN_PMC1:1;
- ///
- /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
- ///
- UINT32 PEBS_EN_PMC2:1;
- ///
- /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
- ///
- UINT32 PEBS_EN_PMC3:1;
- UINT32 Reserved1:28;
- ///
- /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
- ///
- UINT32 LL_EN_PMC0:1;
- ///
- /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
- ///
- UINT32 LL_EN_PMC1:1;
- ///
- /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
- ///
- UINT32 LL_EN_PMC2:1;
- ///
- /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
- ///
- UINT32 LL_EN_PMC3:1;
- UINT32 Reserved2:28;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_PEBS_ENABLE_REGISTER;
-
-
-/**
- Thread. See Section 18.7.1.2, "Load Latency Performance Monitoring
- Facility.".
-
- @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
- AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Minimum threshold latency value of tagged load operation
- /// that will be counted. (R/W).
- ///
- UINT32 MinimumThreshold:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_PEBS_LD_LAT_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
- Residency Counter. (R/O) Value since last reset that this package is in
- processor-specific C3 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
- AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
- Residency Counter. (R/O) Value since last reset that this package is in
- processor-specific C6 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
- Residency Counter. (R/O) Value since last reset that this package is in
- processor-specific C7 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
- AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA
-
-
-/**
- Core. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
- Residency Counter. (R/O) Value since last reset that this core is in
- processor-specific C3 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
- AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC
-
-
-/**
- Core. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
- Residency Counter. (R/O) Value since last reset that this core is in
- processor-specific C6 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD
-
-
-/**
- See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_NEHALEM_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC0_MISC);
- AsmWriteMsr64 (MSR_NEHALEM_MC0_MISC, Msr);
- @endcode
- @{
-**/
-#define MSR_NEHALEM_MC0_MISC 0x00000403
-#define MSR_NEHALEM_MC1_MISC 0x00000407
-#define MSR_NEHALEM_MC2_MISC 0x0000040B
-#define MSR_NEHALEM_MC3_MISC 0x0000040F
-#define MSR_NEHALEM_MC4_MISC 0x00000413
-#define MSR_NEHALEM_MC5_MISC 0x00000417
-#define MSR_NEHALEM_MC6_MISC 0x0000041B
-#define MSR_NEHALEM_MC7_MISC 0x0000041F
-#define MSR_NEHALEM_MC8_MISC 0x00000423
-#define MSR_NEHALEM_MC9_MISC 0x00000427
-#define MSR_NEHALEM_MC10_MISC 0x0000042B
-#define MSR_NEHALEM_MC11_MISC 0x0000042F
-#define MSR_NEHALEM_MC12_MISC 0x00000433
-#define MSR_NEHALEM_MC13_MISC 0x00000437
-#define MSR_NEHALEM_MC14_MISC 0x0000043B
-#define MSR_NEHALEM_MC15_MISC 0x0000043F
-#define MSR_NEHALEM_MC16_MISC 0x00000443
-#define MSR_NEHALEM_MC17_MISC 0x00000447
-#define MSR_NEHALEM_MC18_MISC 0x0000044B
-#define MSR_NEHALEM_MC19_MISC 0x0000044F
-#define MSR_NEHALEM_MC20_MISC 0x00000453
-#define MSR_NEHALEM_MC21_MISC 0x00000457
-/// @}
-
-
-/**
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_NEHALEM_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_CTL);
- AsmWriteMsr64 (MSR_NEHALEM_MC3_CTL, Msr);
- @endcode
- @{
-**/
-#define MSR_NEHALEM_MC3_CTL 0x0000040C
-#define MSR_NEHALEM_MC4_CTL 0x00000410
-#define MSR_NEHALEM_MC5_CTL 0x00000414
-#define MSR_NEHALEM_MC6_CTL 0x00000418
-#define MSR_NEHALEM_MC7_CTL 0x0000041C
-#define MSR_NEHALEM_MC8_CTL 0x00000420
-#define MSR_NEHALEM_MC9_CTL 0x00000424
-#define MSR_NEHALEM_MC10_CTL 0x00000428
-#define MSR_NEHALEM_MC11_CTL 0x0000042C
-#define MSR_NEHALEM_MC12_CTL 0x00000430
-#define MSR_NEHALEM_MC13_CTL 0x00000434
-#define MSR_NEHALEM_MC14_CTL 0x00000438
-#define MSR_NEHALEM_MC15_CTL 0x0000043C
-#define MSR_NEHALEM_MC16_CTL 0x00000440
-#define MSR_NEHALEM_MC17_CTL 0x00000444
-#define MSR_NEHALEM_MC18_CTL 0x00000448
-#define MSR_NEHALEM_MC19_CTL 0x0000044C
-#define MSR_NEHALEM_MC20_CTL 0x00000450
-#define MSR_NEHALEM_MC21_CTL 0x00000454
-/// @}
-
-
-/**
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.
-
- @param ECX MSR_NEHALEM_MCi_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_MC3_STATUS, Msr);
- @endcode
- @{
-**/
-#define MSR_NEHALEM_MC3_STATUS 0x0000040D
-#define MSR_NEHALEM_MC4_STATUS 0x00000411
-#define MSR_NEHALEM_MC5_STATUS 0x00000415
-#define MSR_NEHALEM_MC6_STATUS 0x00000419
-#define MSR_NEHALEM_MC7_STATUS 0x0000041D
-#define MSR_NEHALEM_MC8_STATUS 0x00000421
-#define MSR_NEHALEM_MC9_STATUS 0x00000425
-#define MSR_NEHALEM_MC10_STATUS 0x00000429
-#define MSR_NEHALEM_MC11_STATUS 0x0000042D
-#define MSR_NEHALEM_MC12_STATUS 0x00000431
-#define MSR_NEHALEM_MC13_STATUS 0x00000435
-#define MSR_NEHALEM_MC14_STATUS 0x00000439
-#define MSR_NEHALEM_MC15_STATUS 0x0000043D
-#define MSR_NEHALEM_MC16_STATUS 0x00000441
-#define MSR_NEHALEM_MC17_STATUS 0x00000445
-#define MSR_NEHALEM_MC18_STATUS 0x00000449
-#define MSR_NEHALEM_MC19_STATUS 0x0000044D
-#define MSR_NEHALEM_MC20_STATUS 0x00000451
-#define MSR_NEHALEM_MC21_STATUS 0x00000455
-/// @}
-
-
-/**
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs."
-
- The MSR_MC3_ADDR register is either not implemented or contains no address
- if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not
- implemented in the processor, all reads and writes to this MSR will cause a
- general-protection exception.
-
- The MSR_MC4_ADDR register is either not implemented or contains no address
- if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not
- implemented in the processor, all reads and writes to this MSR will cause a
- general-protection exception.
-
- @param ECX MSR_NEHALEM_MC3_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_ADDR);
- AsmWriteMsr64 (MSR_NEHALEM_MC3_ADDR, Msr);
- @endcode
- @{
-**/
-#define MSR_NEHALEM_MC3_ADDR 0x0000040E
-#define MSR_NEHALEM_MC4_ADDR 0x00000412
-#define MSR_NEHALEM_MC5_ADDR 0x00000416
-#define MSR_NEHALEM_MC6_ADDR 0x0000041A
-#define MSR_NEHALEM_MC7_ADDR 0x0000041E
-#define MSR_NEHALEM_MC8_ADDR 0x00000422
-#define MSR_NEHALEM_MC9_ADDR 0x00000426
-#define MSR_NEHALEM_MC10_ADDR 0x0000042A
-#define MSR_NEHALEM_MC11_ADDR 0x0000042E
-#define MSR_NEHALEM_MC12_ADDR 0x00000432
-#define MSR_NEHALEM_MC13_ADDR 0x00000436
-#define MSR_NEHALEM_MC14_ADDR 0x0000043A
-#define MSR_NEHALEM_MC15_ADDR 0x0000043E
-#define MSR_NEHALEM_MC16_ADDR 0x00000442
-#define MSR_NEHALEM_MC17_ADDR 0x00000446
-#define MSR_NEHALEM_MC18_ADDR 0x0000044A
-#define MSR_NEHALEM_MC19_ADDR 0x0000044E
-#define MSR_NEHALEM_MC20_ADDR 0x00000452
-#define MSR_NEHALEM_MC21_ADDR 0x00000456
-/// @}
-
-
-/**
- Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
- branch record registers on the last branch record stack. This part of the
- stack contains pointers to the source instruction for one of the last
- sixteen branches, exceptions, or interrupts taken by the processor. See
- also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR
- Stack.".
-
- @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
- AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680
-#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681
-#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682
-#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683
-#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684
-#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685
-#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686
-#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687
-#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688
-#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689
-#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A
-#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B
-#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C
-#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D
-#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E
-#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F
-/// @}
-
-
-/**
- Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction for one of the last sixteen
- branches, exceptions, or interrupts taken by the processor.
-
- @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
- AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0
-#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1
-#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2
-#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3
-#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4
-#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5
-#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6
-#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7
-#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8
-#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9
-#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA
-#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB
-#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC
-#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD
-#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE
-#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF
-/// @}
-
-
-/**
- Package.
-
- @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
- AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);
- @endcode
-**/
-#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301
-
-/**
- MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] From M to S (R/W).
- ///
- UINT32 FromMtoS:1;
- ///
- /// [Bit 1] From E to S (R/W).
- ///
- UINT32 FromEtoS:1;
- ///
- /// [Bit 2] From S to S (R/W).
- ///
- UINT32 FromStoS:1;
- ///
- /// [Bit 3] From F to S (R/W).
- ///
- UINT32 FromFtoS:1;
- ///
- /// [Bit 4] From M to I (R/W).
- ///
- UINT32 FromMtoI:1;
- ///
- /// [Bit 5] From E to I (R/W).
- ///
- UINT32 FromEtoI:1;
- ///
- /// [Bit 6] From S to I (R/W).
- ///
- UINT32 FromStoI:1;
- ///
- /// [Bit 7] From F to I (R/W).
- ///
- UINT32 FromFtoI:1;
- UINT32 Reserved1:24;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;
-
-
-/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
- Facility.".
-
- @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391
-
-
-/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
- Facility.".
-
- @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392
-
-
-/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
- Facility.".
-
- @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393
-
-
-/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
- Facility.".
-
- @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394
-
-
-/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
- Facility.".
-
- @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395
-
-
-/**
- Package. See Section 18.7.2.3, "Uncore Address/Opcode Match MSR.".
-
- @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396
-
-
-/**
- Package. See Section 18.7.2.2, "Uncore Performance Event Configuration
- Facility.".
-
- @param ECX MSR_NEHALEM_UNCORE_PMCi
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);
- @endcode
- @{
-**/
-#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0
-#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1
-#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2
-#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3
-#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4
-#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5
-#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6
-#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7
-/// @}
-
-/**
- Package. See Section 18.7.2.2, "Uncore Performance Event Configuration
- Facility.".
-
- @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);
- @endcode
- @{
-**/
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7
-/// @}
-
-
-/**
- Package. Uncore W-box perfmon fixed counter.
-
- @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394
-
-
-/**
- Package. Uncore U-box perfmon fixed counter control MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395
-
-
-/**
- Package. Uncore U-box perfmon global control MSR.
-
- @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00
-
-
-/**
- Package. Uncore U-box perfmon global status MSR.
-
- @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01
-
-
-/**
- Package. Uncore U-box perfmon global overflow control MSR.
-
- @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02
-
-
-/**
- Package. Uncore U-box perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10
-
-
-/**
- Package. Uncore U-box perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_U_PMON_CTR 0x00000C11
-
-
-/**
- Package. Uncore B-box 0 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20
-
-
-/**
- Package. Uncore B-box 0 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21
-
-
-/**
- Package. Uncore B-box 0 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22
-
-
-/**
- Package. Uncore B-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30
-
-
-/**
- Package. Uncore B-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31
-
-
-/**
- Package. Uncore B-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32
-
-
-/**
- Package. Uncore B-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33
-
-
-/**
- Package. Uncore B-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34
-
-
-/**
- Package. Uncore B-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35
-
-
-/**
- Package. Uncore B-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36
-
-
-/**
- Package. Uncore B-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37
-
-
-/**
- Package. Uncore S-box 0 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40
-
-
-/**
- Package. Uncore S-box 0 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41
-
-
-/**
- Package. Uncore S-box 0 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42
-
-
-/**
- Package. Uncore S-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50
-
-
-/**
- Package. Uncore S-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51
-
-
-/**
- Package. Uncore S-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52
-
-
-/**
- Package. Uncore S-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53
-
-
-/**
- Package. Uncore S-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54
-
-
-/**
- Package. Uncore S-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55
-
-
-/**
- Package. Uncore S-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56
-
-
-/**
- Package. Uncore S-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57
-
-
-/**
- Package. Uncore B-box 1 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60
-
-
-/**
- Package. Uncore B-box 1 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61
-
-
-/**
- Package. Uncore B-box 1 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62
-
-
-/**
- Package. Uncore B-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70
-
-
-/**
- Package. Uncore B-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71
-
-
-/**
- Package. Uncore B-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72
-
-
-/**
- Package. Uncore B-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73
-
-
-/**
- Package. Uncore B-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74
-
-
-/**
- Package. Uncore B-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75
-
-
-/**
- Package. Uncore B-box 1vperfmon event select MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76
-
-
-/**
- Package. Uncore B-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77
-
-
-/**
- Package. Uncore W-box perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80
-
-
-/**
- Package. Uncore W-box perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81
-
-
-/**
- Package. Uncore W-box perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82
-
-
-/**
- Package. Uncore W-box perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90
-
-
-/**
- Package. Uncore W-box perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91
-
-
-/**
- Package. Uncore W-box perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92
-
-
-/**
- Package. Uncore W-box perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93
-
-
-/**
- Package. Uncore W-box perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94
-
-
-/**
- Package. Uncore W-box perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95
-
-
-/**
- Package. Uncore W-box perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96
-
-
-/**
- Package. Uncore W-box perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97
-
-
-/**
- Package. Uncore M-box 0 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0
-
-
-/**
- Package. Uncore M-box 0 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1
-
-
-/**
- Package. Uncore M-box 0 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2
-
-
-/**
- Package. Uncore M-box 0 perfmon time stamp unit select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4
-
-
-/**
- Package. Uncore M-box 0 perfmon DSP unit select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5
-
-
-/**
- Package. Uncore M-box 0 perfmon ISS unit select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6
-
-
-/**
- Package. Uncore M-box 0 perfmon MAP unit select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7
-
-
-/**
- Package. Uncore M-box 0 perfmon MIC THR select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8
-
-
-/**
- Package. Uncore M-box 0 perfmon PGT unit select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9
-
-
-/**
- Package. Uncore M-box 0 perfmon PLD unit select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA
-
-
-/**
- Package. Uncore M-box 0 perfmon ZDP unit select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB
-
-
-/**
- Package. Uncore M-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0
-
-
-/**
- Package. Uncore M-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1
-
-
-/**
- Package. Uncore M-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2
-
-
-/**
- Package. Uncore M-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3
-
-
-/**
- Package. Uncore M-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4
-
-
-/**
- Package. Uncore M-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5
-
-
-/**
- Package. Uncore M-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6
-
-
-/**
- Package. Uncore M-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7
-
-
-/**
- Package. Uncore M-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8
-
-
-/**
- Package. Uncore M-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9
-
-
-/**
- Package. Uncore M-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA
-
-
-/**
- Package. Uncore M-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB
-
-
-/**
- Package. Uncore S-box 1 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0
-
-
-/**
- Package. Uncore S-box 1 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1
-
-
-/**
- Package. Uncore S-box 1 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2
-
-
-/**
- Package. Uncore S-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0
-
-
-/**
- Package. Uncore S-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1
-
-
-/**
- Package. Uncore S-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2
-
-
-/**
- Package. Uncore S-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3
-
-
-/**
- Package. Uncore S-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4
-
-
-/**
- Package. Uncore S-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5
-
-
-/**
- Package. Uncore S-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6
-
-
-/**
- Package. Uncore S-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7
-
-
-/**
- Package. Uncore M-box 1 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0
-
-
-/**
- Package. Uncore M-box 1 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1
-
-
-/**
- Package. Uncore M-box 1 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2
-
-
-/**
- Package. Uncore M-box 1 perfmon time stamp unit select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4
-
-
-/**
- Package. Uncore M-box 1 perfmon DSP unit select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5
-
-
-/**
- Package. Uncore M-box 1 perfmon ISS unit select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6
-
-
-/**
- Package. Uncore M-box 1 perfmon MAP unit select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7
-
-
-/**
- Package. Uncore M-box 1 perfmon MIC THR select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8
-
-
-/**
- Package. Uncore M-box 1 perfmon PGT unit select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9
-
-
-/**
- Package. Uncore M-box 1 perfmon PLD unit select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA
-
-
-/**
- Package. Uncore M-box 1 perfmon ZDP unit select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB
-
-
-/**
- Package. Uncore M-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0
-
-
-/**
- Package. Uncore M-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1
-
-
-/**
- Package. Uncore M-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2
-
-
-/**
- Package. Uncore M-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3
-
-
-/**
- Package. Uncore M-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4
-
-
-/**
- Package. Uncore M-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5
-
-
-/**
- Package. Uncore M-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6
-
-
-/**
- Package. Uncore M-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7
-
-
-/**
- Package. Uncore M-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8
-
-
-/**
- Package. Uncore M-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9
-
-
-/**
- Package. Uncore M-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA
-
-
-/**
- Package. Uncore M-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB
-
-
-/**
- Package. Uncore C-box 0 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00
-
-
-/**
- Package. Uncore C-box 0 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01
-
-
-/**
- Package. Uncore C-box 0 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02
-
-
-/**
- Package. Uncore C-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10
-
-
-/**
- Package. Uncore C-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11
-
-
-/**
- Package. Uncore C-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12
-
-
-/**
- Package. Uncore C-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13
-
-
-/**
- Package. Uncore C-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14
-
-
-/**
- Package. Uncore C-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15
-
-
-/**
- Package. Uncore C-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16
-
-
-/**
- Package. Uncore C-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17
-
-
-/**
- Package. Uncore C-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18
-
-
-/**
- Package. Uncore C-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19
-
-
-/**
- Package. Uncore C-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A
-
-
-/**
- Package. Uncore C-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B
-
-
-/**
- Package. Uncore C-box 4 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20
-
-
-/**
- Package. Uncore C-box 4 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21
-
-
-/**
- Package. Uncore C-box 4 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22
-
-
-/**
- Package. Uncore C-box 4 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30
-
-
-/**
- Package. Uncore C-box 4 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31
-
-
-/**
- Package. Uncore C-box 4 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32
-
-
-/**
- Package. Uncore C-box 4 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33
-
-
-/**
- Package. Uncore C-box 4 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34
-
-
-/**
- Package. Uncore C-box 4 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35
-
-
-/**
- Package. Uncore C-box 4 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36
-
-
-/**
- Package. Uncore C-box 4 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37
-
-
-/**
- Package. Uncore C-box 4 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38
-
-
-/**
- Package. Uncore C-box 4 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39
-
-
-/**
- Package. Uncore C-box 4 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A
-
-
-/**
- Package. Uncore C-box 4 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B
-
-
-/**
- Package. Uncore C-box 2 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40
-
-
-/**
- Package. Uncore C-box 2 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41
-
-
-/**
- Package. Uncore C-box 2 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42
-
-
-/**
- Package. Uncore C-box 2 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50
-
-
-/**
- Package. Uncore C-box 2 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51
-
-
-/**
- Package. Uncore C-box 2 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52
-
-
-/**
- Package. Uncore C-box 2 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53
-
-
-/**
- Package. Uncore C-box 2 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54
-
-
-/**
- Package. Uncore C-box 2 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55
-
-
-/**
- Package. Uncore C-box 2 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56
-
-
-/**
- Package. Uncore C-box 2 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57
-
-
-/**
- Package. Uncore C-box 2 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58
-
-
-/**
- Package. Uncore C-box 2 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59
-
-
-/**
- Package. Uncore C-box 2 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A
-
-
-/**
- Package. Uncore C-box 2 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B
-
-
-/**
- Package. Uncore C-box 6 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60
-
-
-/**
- Package. Uncore C-box 6 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61
-
-
-/**
- Package. Uncore C-box 6 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62
-
-
-/**
- Package. Uncore C-box 6 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70
-
-
-/**
- Package. Uncore C-box 6 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71
-
-
-/**
- Package. Uncore C-box 6 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72
-
-
-/**
- Package. Uncore C-box 6 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73
-
-
-/**
- Package. Uncore C-box 6 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74
-
-
-/**
- Package. Uncore C-box 6 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75
-
-
-/**
- Package. Uncore C-box 6 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76
-
-
-/**
- Package. Uncore C-box 6 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77
-
-
-/**
- Package. Uncore C-box 6 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78
-
-
-/**
- Package. Uncore C-box 6 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79
-
-
-/**
- Package. Uncore C-box 6 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A
-
-
-/**
- Package. Uncore C-box 6 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B
-
-
-/**
- Package. Uncore C-box 1 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80
-
-
-/**
- Package. Uncore C-box 1 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81
-
-
-/**
- Package. Uncore C-box 1 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82
-
-
-/**
- Package. Uncore C-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90
-
-
-/**
- Package. Uncore C-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91
-
-
-/**
- Package. Uncore C-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92
-
-
-/**
- Package. Uncore C-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93
-
-
-/**
- Package. Uncore C-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94
-
-
-/**
- Package. Uncore C-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95
-
-
-/**
- Package. Uncore C-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96
-
-
-/**
- Package. Uncore C-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97
-
-
-/**
- Package. Uncore C-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98
-
-
-/**
- Package. Uncore C-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99
-
-
-/**
- Package. Uncore C-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A
-
-
-/**
- Package. Uncore C-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B
-
-
-/**
- Package. Uncore C-box 5 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0
-
-
-/**
- Package. Uncore C-box 5 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1
-
-
-/**
- Package. Uncore C-box 5 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2
-
-
-/**
- Package. Uncore C-box 5 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0
-
-
-/**
- Package. Uncore C-box 5 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1
-
-
-/**
- Package. Uncore C-box 5 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2
-
-
-/**
- Package. Uncore C-box 5 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3
-
-
-/**
- Package. Uncore C-box 5 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4
-
-
-/**
- Package. Uncore C-box 5 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5
-
-
-/**
- Package. Uncore C-box 5 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6
-
-
-/**
- Package. Uncore C-box 5 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7
-
-
-/**
- Package. Uncore C-box 5 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8
-
-
-/**
- Package. Uncore C-box 5 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9
-
-
-/**
- Package. Uncore C-box 5 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA
-
-
-/**
- Package. Uncore C-box 5 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB
-
-
-/**
- Package. Uncore C-box 3 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0
-
-
-/**
- Package. Uncore C-box 3 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1
-
-
-/**
- Package. Uncore C-box 3 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2
-
-
-/**
- Package. Uncore C-box 3 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0
-
-
-/**
- Package. Uncore C-box 3 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1
-
-
-/**
- Package. Uncore C-box 3 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2
-
-
-/**
- Package. Uncore C-box 3 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3
-
-
-/**
- Package. Uncore C-box 3 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4
-
-
-/**
- Package. Uncore C-box 3 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5
-
-
-/**
- Package. Uncore C-box 3 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6
-
-
-/**
- Package. Uncore C-box 3 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7
-
-
-/**
- Package. Uncore C-box 3 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8
-
-
-/**
- Package. Uncore C-box 3 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9
-
-
-/**
- Package. Uncore C-box 3 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA
-
-
-/**
- Package. Uncore C-box 3 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB
-
-
-/**
- Package. Uncore C-box 7 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0
-
-
-/**
- Package. Uncore C-box 7 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1
-
-
-/**
- Package. Uncore C-box 7 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2
-
-
-/**
- Package. Uncore C-box 7 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0
-
-
-/**
- Package. Uncore C-box 7 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1
-
-
-/**
- Package. Uncore C-box 7 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2
-
-
-/**
- Package. Uncore C-box 7 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3
-
-
-/**
- Package. Uncore C-box 7 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4
-
-
-/**
- Package. Uncore C-box 7 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5
-
-
-/**
- Package. Uncore C-box 7 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6
-
-
-/**
- Package. Uncore C-box 7 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7
-
-
-/**
- Package. Uncore C-box 7 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8
-
-
-/**
- Package. Uncore C-box 7 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9
-
-
-/**
- Package. Uncore C-box 7 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA
-
-
-/**
- Package. Uncore C-box 7 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB
-
-
-/**
- Package. Uncore R-box 0 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00
-
-
-/**
- Package. Uncore R-box 0 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01
-
-
-/**
- Package. Uncore R-box 0 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02
-
-
-/**
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04
-
-
-/**
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05
-
-
-/**
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06
-
-
-/**
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07
-
-
-/**
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08
-
-
-/**
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09
-
-
-/**
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A
-
-
-/**
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B
-
-
-/**
- Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C
-
-
-/**
- Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D
-
-
-/**
- Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E
-
-
-/**
- Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F
-
-
-/**
- Package. Uncore R-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10
-
-
-/**
- Package. Uncore R-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11
-
-
-/**
- Package. Uncore R-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12
-
-
-/**
- Package. Uncore R-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13
-
-
-/**
- Package. Uncore R-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14
-
-
-/**
- Package. Uncore R-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15
-
-
-/**
- Package. Uncore R-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16
-
-
-/**
- Package. Uncore R-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17
-
-
-/**
- Package. Uncore R-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18
-
-
-/**
- Package. Uncore R-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19
-
-
-/**
- Package. Uncore R-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A
-
-
-/**
- Package. Uncore R-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B
-
-
-/**
- Package. Uncore R-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C
-
-
-/**
- Package. Uncore R-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D
-
-
-/**
- Package. Uncore R-box 0 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E
-
-
-/**
- Package. Uncore R-box 0 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F
-
-
-/**
- Package. Uncore R-box 1 perfmon local box control MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20
-
-
-/**
- Package. Uncore R-box 1 perfmon local box status MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21
-
-
-/**
- Package. Uncore R-box 1 perfmon local box overflow control MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22
-
-
-/**
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24
-
-
-/**
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25
-
-
-/**
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26
-
-
-/**
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27
-
-
-/**
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28
-
-
-/**
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29
-
-
-/**
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A
-
-
-/**
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B
-
-
-/**
- Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C
-
-
-/**
- Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D
-
-
-/**
- Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E
-
-
-/**
- Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F
-
-
-/**
- Package. Uncore R-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30
-
-
-/**
- Package. Uncore R-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31
-
-
-/**
- Package. Uncore R-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32
-
-
-/**
- Package. Uncore R-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33
-
-
-/**
- Package. Uncore R-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34
-
-
-/**
- Package. Uncore R-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35
-
-
-/**
- Package. Uncore R-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36
-
-
-/**
- Package. Uncore R-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37
-
-
-/**
- Package. Uncore R-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38
-
-
-/**
- Package. Uncore R-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39
-
-
-/**
- Package. Uncore R-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A
-
-
-/**
- Package. Uncore R-box 1perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B
-
-
-/**
- Package. Uncore R-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C
-
-
-/**
- Package. Uncore R-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D
-
-
-/**
- Package. Uncore R-box 1 perfmon event select MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E
-
-
-/**
- Package. Uncore R-box 1 perfmon counter MSR.
-
- @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F
-
-
-/**
- Package. Uncore B-box 0 perfmon local box match MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45
-
-
-/**
- Package. Uncore B-box 0 perfmon local box mask MSR.
-
- @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46
-
-
-/**
- Package. Uncore S-box 0 perfmon local box match MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49
-
-
-/**
- Package. Uncore S-box 0 perfmon local box mask MSR.
-
- @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A
-
-
-/**
- Package. Uncore B-box 1 perfmon local box match MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D
-
-
-/**
- Package. Uncore B-box 1 perfmon local box mask MSR.
-
- @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E
-
-
-/**
- Package. Uncore M-box 0 perfmon local box address match/mask config MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54
-
-
-/**
- Package. Uncore M-box 0 perfmon local box address match MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55
-
-
-/**
- Package. Uncore M-box 0 perfmon local box address mask MSR.
-
- @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56
-
-
-/**
- Package. Uncore S-box 1 perfmon local box match MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59
-
-
-/**
- Package. Uncore S-box 1 perfmon local box mask MSR.
-
- @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A
-
-
-/**
- Package. Uncore M-box 1 perfmon local box address match/mask config MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C
-
-
-/**
- Package. Uncore M-box 1 perfmon local box address match MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D
-
-
-/**
- Package. Uncore M-box 1 perfmon local box address mask MSR.
-
- @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);
- @endcode
-**/
-#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/Register/Msr/P6Msr.h deleted file mode 100644 index 7ee0b28356..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h +++ /dev/null @@ -1,1608 +0,0 @@ -/** @file
- MSR Definitions for P6 Family Processors.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19.
-
-**/
-
-#ifndef __P6_MSR_H__
-#define __P6_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- See Section 35.20, "MSRs in Pentium Processors.".
-
- @param ECX MSR_P6_P5_MC_ADDR (0x00000000)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
- AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
- @endcode
-**/
-#define MSR_P6_P5_MC_ADDR 0x00000000
-
-
-/**
- See Section 35.20, "MSRs in Pentium Processors.".
-
- @param ECX MSR_P6_P5_MC_TYPE (0x00000001)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
- AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
- @endcode
-**/
-#define MSR_P6_P5_MC_TYPE 0x00000001
-
-
-/**
- See Section 17.14, "Time-Stamp Counter.".
-
- @param ECX MSR_P6_TSC (0x00000010)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_TSC);
- AsmWriteMsr64 (MSR_P6_TSC, Msr);
- @endcode
-**/
-#define MSR_P6_TSC 0x00000010
-
-
-/**
- Platform ID (R) The operating system can use this MSR to determine "slot"
- information for the processor and the proper microcode update to load.
-
- @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
- @endcode
-**/
-#define MSR_P6_IA32_PLATFORM_ID 0x00000017
-
-/**
- MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:18;
- ///
- /// [Bits 52:50] Platform Id (R) Contains information concerning the
- /// intended platform for the processor.
- ///
- /// 52 51 50
- /// 0 0 0 Processor Flag 0.
- /// 0 0 1 Processor Flag 1
- /// 0 1 0 Processor Flag 2
- /// 0 1 1 Processor Flag 3
- /// 1 0 0 Processor Flag 4
- /// 1 0 1 Processor Flag 5
- /// 1 1 0 Processor Flag 6
- /// 1 1 1 Processor Flag 7
- ///
- UINT32 PlatformId:3;
- ///
- /// [Bits 56:53] L2 Cache Latency Read.
- ///
- UINT32 L2CacheLatencyRead:4;
- UINT32 Reserved3:3;
- ///
- /// [Bit 60] Clock Frequency Ratio Read.
- ///
- UINT32 ClockFrequencyRatioRead:1;
- UINT32 Reserved4:3;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_IA32_PLATFORM_ID_REGISTER;
-
-
-/**
- Section 10.4.4, "Local APIC Status and Location.".
-
- @param ECX MSR_P6_APIC_BASE (0x0000001B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_APIC_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_APIC_BASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_APIC_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
- AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_APIC_BASE 0x0000001B
-
-/**
- MSR information returned for MSR index #MSR_P6_APIC_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.
- ///
- UINT32 BSP:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =
- /// Disabled.
- ///
- UINT32 EN:1;
- ///
- /// [Bits 31:12] APIC Base Address.
- ///
- UINT32 ApicBase:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_APIC_BASE_REGISTER;
-
-
-/**
- Processor Hard Power-On Configuration (R/W) Enables and disables processor
- features; (R) indicates current processor configuration.
-
- @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_EBL_CR_POWERON_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
- AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_EBL_CR_POWERON 0x0000002A
-
-/**
- MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.
- ///
- UINT32 DataErrorCheckingEnable:1;
- ///
- /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)
- /// 1 = Enabled 0 = Disabled.
- ///
- UINT32 ResponseErrorCheckingEnable:1;
- ///
- /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.
- ///
- UINT32 AERR_DriveEnable:1;
- ///
- /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =
- /// Disabled.
- ///
- UINT32 BERR_Enable:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =
- /// Enabled 0 = Disabled.
- ///
- UINT32 BERR_DriverEnable:1;
- ///
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.
- ///
- UINT32 BINIT_DriverEnable:1;
- ///
- /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.
- ///
- UINT32 OutputTriStateEnable:1;
- ///
- /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.
- ///
- UINT32 ExecuteBIST:1;
- ///
- /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.
- ///
- UINT32 AERR_ObservationEnabled:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.
- ///
- UINT32 BINIT_ObservationEnabled:1;
- ///
- /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.
- ///
- UINT32 InOrderQueueDepth:1;
- ///
- /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.
- ///
- UINT32 ResetVector:1;
- ///
- /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.
- ///
- UINT32 FRCModeEnable:1;
- ///
- /// [Bits 17:16] APIC Cluster ID (R).
- ///
- UINT32 APICClusterID:2;
- ///
- /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =
- /// 133MHz 11 = Reserved.
- ///
- UINT32 SystemBusFrequency:2;
- ///
- /// [Bits 21:20] Symmetric Arbitration ID (R).
- ///
- UINT32 SymmetricArbitrationID:2;
- ///
- /// [Bits 25:22] Clock Frequency Ratio (R).
- ///
- UINT32 ClockFrequencyRatio:4;
- ///
- /// [Bit 26] Low Power Mode Enable (R/W).
- ///
- UINT32 LowPowerModeEnable:1;
- ///
- /// [Bit 27] Clock Frequency Ratio.
- ///
- UINT32 ClockFrequencyRatio1:1;
- UINT32 Reserved4:4;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_EBL_CR_POWERON_REGISTER;
-
-
-/**
- Test Control Register.
-
- @param ECX MSR_P6_TEST_CTL (0x00000033)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_TEST_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_TEST_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_TEST_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
- AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_TEST_CTL 0x00000033
-
-/**
- MSR information returned for MSR index #MSR_P6_TEST_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:30;
- ///
- /// [Bit 30] Streaming Buffer Disable.
- ///
- UINT32 StreamingBufferDisable:1;
- ///
- /// [Bit 31] Disable LOCK# Assertion for split locked access.
- ///
- UINT32 Disable_LOCK:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_TEST_CTL_REGISTER;
-
-
-/**
- BIOS Update Trigger Register.
-
- @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
- AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
- @endcode
-**/
-#define MSR_P6_BIOS_UPDT_TRIG 0x00000079
-
-
-/**
- Chunk n data register D[63:0]: used to write to and read from the L2.
-
- @param ECX MSR_P6_BBL_CR_Dn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
- AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
- @endcode
- @{
-**/
-#define MSR_P6_BBL_CR_D0 0x00000088
-#define MSR_P6_BBL_CR_D1 0x00000089
-#define MSR_P6_BBL_CR_D2 0x0000008A
-/// @}
-
-
-/**
- BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to
- write to and read from the L2 depending on the usage model.
-
- @param ECX MSR_P6_BIOS_SIGN (0x0000008B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
- AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
- @endcode
-**/
-#define MSR_P6_BIOS_SIGN 0x0000008B
-
-
-/**
-
-
- @param ECX MSR_P6_PERFCTR0 (0x000000C1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
- AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
- @endcode
- @{
-**/
-#define MSR_P6_PERFCTR0 0x000000C1
-#define MSR_P6_PERFCTR1 0x000000C2
-/// @}
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRCAP (0x000000FE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
- AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRCAP 0x000000FE
-
-
-/**
- Address register: used to send specified address (A31-A3) to L2 during cache
- initialization accesses.
-
- @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_BBL_CR_ADDR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
- AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_BBL_CR_ADDR 0x00000116
-
-/**
- MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:3;
- ///
- /// [Bits 31:3] Address bits
- ///
- UINT32 Address:29;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_BBL_CR_ADDR_REGISTER;
-
-
-/**
- Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
-
- @param ECX MSR_P6_BBL_CR_DECC (0x00000118)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
- AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
- @endcode
-**/
-#define MSR_P6_BBL_CR_DECC 0x00000118
-
-
-/**
- Control register: used to program L2 commands to be issued via cache
- configuration accesses mechanism. Also receives L2 lookup response.
-
- @param ECX MSR_P6_BBL_CR_CTL (0x00000119)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_BBL_CR_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
- AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_BBL_CR_CTL 0x00000119
-
-/**
- MSR information returned for MSR index #MSR_P6_BBL_CR_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 4:0] L2 Command
- /// Data Read w/ LRU update (RLU)
- /// Tag Read w/ Data Read (TRR)
- /// Tag Inquire (TI)
- /// L2 Control Register Read (CR)
- /// L2 Control Register Write (CW)
- /// Tag Write w/ Data Read (TWR)
- /// Tag Write w/ Data Write (TWW)
- /// Tag Write (TW).
- ///
- UINT32 L2Command:5;
- ///
- /// [Bits 6:5] State to L2
- ///
- UINT32 StateToL2:2;
- UINT32 Reserved:1;
- ///
- /// [Bits 9:8] Way to L2.
- ///
- UINT32 WayToL2:2;
- ///
- /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.
- ///
- UINT32 Way:2;
- ///
- /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.
- ///
- UINT32 MESI:2;
- ///
- /// [Bits 15:14] State from L2.
- ///
- UINT32 StateFromL2:2;
- UINT32 Reserved2:1;
- ///
- /// [Bit 17] L2 Hit.
- ///
- UINT32 L2Hit:1;
- UINT32 Reserved3:1;
- ///
- /// [Bits 20:19] User supplied ECC.
- ///
- UINT32 UserEcc:2;
- ///
- /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.
- ///
- UINT32 ProcessorNumber:1;
- UINT32 Reserved4:10;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_BBL_CR_CTL_REGISTER;
-
-
-/**
- Trigger register: used to initiate a cache configuration accesses access,
- Write only with Data = 0.
-
- @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
- AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
- @endcode
-**/
-#define MSR_P6_BBL_CR_TRIG 0x0000011A
-
-
-/**
- Busy register: indicates when a cache configuration accesses L2 command is
- in progress. D[0] = 1 = BUSY.
-
- @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
- AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);
- @endcode
-**/
-#define MSR_P6_BBL_CR_BUSY 0x0000011B
-
-
-/**
- Control register 3: used to configure the L2 Cache.
-
- @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_BBL_CR_CTL3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
- AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_BBL_CR_CTL3 0x0000011E
-
-/**
- MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] L2 Configured (read/write ).
- ///
- UINT32 L2Configured:1;
- ///
- /// [Bits 4:1] L2 Cache Latency (read/write).
- ///
- UINT32 L2CacheLatency:4;
- ///
- /// [Bit 5] ECC Check Enable (read/write).
- ///
- UINT32 ECCCheckEnable:1;
- ///
- /// [Bit 6] Address Parity Check Enable (read/write).
- ///
- UINT32 AddressParityCheckEnable:1;
- ///
- /// [Bit 7] CRTN Parity Check Enable (read/write).
- ///
- UINT32 CRTNParityCheckEnable:1;
- ///
- /// [Bit 8] L2 Enabled (read/write).
- ///
- UINT32 L2Enabled:1;
- ///
- /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way
- /// Reserved.
- ///
- UINT32 L2Associativity:2;
- ///
- /// [Bits 12:11] Number of L2 banks (read only).
- ///
- UINT32 L2Banks:2;
- ///
- /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes
- /// 1MByte 2MByte 4MBytes.
- ///
- UINT32 CacheSizePerBank:5;
- ///
- /// [Bit 18] Cache State error checking enable (read/write).
- ///
- UINT32 CacheStateErrorEnable:1;
- UINT32 Reserved1:1;
- ///
- /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes
- /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.
- ///
- UINT32 L2AddressRange:3;
- ///
- /// [Bit 23] L2 Hardware Disable (read only).
- ///
- UINT32 L2HardwareDisable:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 25] Cache bus fraction (read only).
- ///
- UINT32 CacheBusFraction:1;
- UINT32 Reserved3:6;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_BBL_CR_CTL3_REGISTER;
-
-
-/**
- CS register target for CPL 0 code.
-
- @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
- AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);
- @endcode
-**/
-#define MSR_P6_SYSENTER_CS_MSR 0x00000174
-
-
-/**
- Stack pointer for CPL 0 stack.
-
- @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
- AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);
- @endcode
-**/
-#define MSR_P6_SYSENTER_ESP_MSR 0x00000175
-
-
-/**
- CPL 0 code entry point.
-
- @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
- AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);
- @endcode
-**/
-#define MSR_P6_SYSENTER_EIP_MSR 0x00000176
-
-
-/**
-
-
- @param ECX MSR_P6_MCG_CAP (0x00000179)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
- AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);
- @endcode
-**/
-#define MSR_P6_MCG_CAP 0x00000179
-
-
-/**
-
-
- @param ECX MSR_P6_MCG_STATUS (0x0000017A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
- AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);
- @endcode
-**/
-#define MSR_P6_MCG_STATUS 0x0000017A
-
-
-/**
-
-
- @param ECX MSR_P6_MCG_CTL (0x0000017B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
- AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);
- @endcode
-**/
-#define MSR_P6_MCG_CTL 0x0000017B
-
-
-/**
-
-
- @param ECX MSR_P6_PERFEVTSELn
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_PERFEVTSEL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_PERFEVTSEL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_PERFEVTSEL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_P6_PERFEVTSEL0 0x00000186
-#define MSR_P6_PERFEVTSEL1 0x00000187
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and
- #MSR_P6_PERFEVTSEL1.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Event Select Refer to Performance Counter section for a
- /// list of event encodings.
- ///
- UINT32 EventSelect:8;
- ///
- /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable
- /// all count options.
- ///
- UINT32 UMASK:8;
- ///
- /// [Bit 16] USER Controls the counting of events at Privilege levels of
- /// 1, 2, and 3.
- ///
- UINT32 USR:1;
- ///
- /// [Bit 17] OS Controls the counting of events at Privilege level of 0.
- ///
- UINT32 OS:1;
- ///
- /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.
- ///
- UINT32 E:1;
- ///
- /// [Bit 19] PC Enabled the signaling of performance counter overflow via
- /// BP0 pin.
- ///
- UINT32 PC:1;
- ///
- /// [Bit 20] INT Enables the signaling of counter overflow via input to
- /// APIC 1 = Enable 0 = Disable.
- ///
- UINT32 INT:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 22] ENABLE Enables the counting of performance events in both
- /// counters 1 = Enable 0 = Disable.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0
- /// = Non-Inverted.
- ///
- UINT32 INV:1;
- ///
- /// [Bits 31:24] CMASK (Counter Mask).
- ///
- UINT32 CMASK:8;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_PERFEVTSEL_REGISTER;
-
-
-/**
-
-
- @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_DEBUGCTLMSR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
- AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_DEBUGCTLMSR 0x000001D9
-
-/**
- MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable/Disable Last Branch Records.
- ///
- UINT32 LBR:1;
- ///
- /// [Bit 1] Branch Trap Flag.
- ///
- UINT32 BTF:1;
- ///
- /// [Bit 2] Performance Monitoring/Break Point Pins.
- ///
- UINT32 PB0:1;
- ///
- /// [Bit 3] Performance Monitoring/Break Point Pins.
- ///
- UINT32 PB1:1;
- ///
- /// [Bit 4] Performance Monitoring/Break Point Pins.
- ///
- UINT32 PB2:1;
- ///
- /// [Bit 5] Performance Monitoring/Break Point Pins.
- ///
- UINT32 PB3:1;
- ///
- /// [Bit 6] Enable/Disable Execution Trace Messages.
- ///
- UINT32 TR:1;
- UINT32 Reserved1:25;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_DEBUGCTLMSR_REGISTER;
-
-
-/**
-
-
- @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
- AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);
- @endcode
-**/
-#define MSR_P6_LASTBRANCHFROMIP 0x000001DB
-
-
-/**
-
-
- @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
- AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);
- @endcode
-**/
-#define MSR_P6_LASTBRANCHTOIP 0x000001DC
-
-
-/**
-
-
- @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
- AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);
- @endcode
-**/
-#define MSR_P6_LASTINTFROMIP 0x000001DD
-
-
-/**
-
-
- @param ECX MSR_P6_LASTINTTOIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
- AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);
- @endcode
-**/
-#define MSR_P6_LASTINTTOIP 0x000001DE
-
-
-/**
-
-
- @param ECX MSR_P6_ROB_CR_BKUPTMPDR6 (0x000001E0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);
- AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_ROB_CR_BKUPTMPDR6 0x000001E0
-
-/**
- MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:2;
- ///
- /// [Bit 2] Fast Strings Enable bit. Default is enabled.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER;
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRPHYSBASEn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
- AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);
- @endcode
- @{
-**/
-#define MSR_P6_MTRRPHYSBASE0 0x00000200
-#define MSR_P6_MTRRPHYSBASE1 0x00000202
-#define MSR_P6_MTRRPHYSBASE2 0x00000204
-#define MSR_P6_MTRRPHYSBASE3 0x00000206
-#define MSR_P6_MTRRPHYSBASE4 0x00000208
-#define MSR_P6_MTRRPHYSBASE5 0x0000020A
-#define MSR_P6_MTRRPHYSBASE6 0x0000020C
-#define MSR_P6_MTRRPHYSBASE7 0x0000020E
-/// @}
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRPHYSMASKn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
- AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);
- @endcode
- @{
-**/
-#define MSR_P6_MTRRPHYSMASK0 0x00000201
-#define MSR_P6_MTRRPHYSMASK1 0x00000203
-#define MSR_P6_MTRRPHYSMASK2 0x00000205
-#define MSR_P6_MTRRPHYSMASK3 0x00000207
-#define MSR_P6_MTRRPHYSMASK4 0x00000209
-#define MSR_P6_MTRRPHYSMASK5 0x0000020B
-#define MSR_P6_MTRRPHYSMASK6 0x0000020D
-#define MSR_P6_MTRRPHYSMASK7 0x0000020F
-/// @}
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX64K_00000 0x00000250
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX16K_80000 0x00000258
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX16K_A0000 0x00000259
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX4K_C0000 0x00000268
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX4K_C8000 0x00000269
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX4K_D0000 0x0000026A
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX4K_D8000 0x0000026B
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX4K_E0000 0x0000026C
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX4K_E8000 0x0000026D
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX4K_F0000 0x0000026E
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);
- @endcode
-**/
-#define MSR_P6_MTRRFIX4K_F8000 0x0000026F
-
-
-/**
-
-
- @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_MTRRDEFTYPE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
- AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);
- @endcode
-**/
-#define MSR_P6_MTRRDEFTYPE 0x000002FF
-
-/**
- MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Default memory type.
- ///
- UINT32 Type:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] Fixed MTRR enable.
- ///
- UINT32 FE:1;
- ///
- /// [Bit 11] MTRR Enable.
- ///
- UINT32 E:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_MTRRDEFTYPE_REGISTER;
-
-
-/**
-
-
- @param ECX MSR_P6_MC0_CTL (0x00000400)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
- AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);
- @endcode
- @{
-**/
-#define MSR_P6_MC0_CTL 0x00000400
-#define MSR_P6_MC1_CTL 0x00000404
-#define MSR_P6_MC2_CTL 0x00000408
-#define MSR_P6_MC3_CTL 0x00000410
-#define MSR_P6_MC4_CTL 0x0000040C
-/// @}
-
-
-/**
-
- Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,
- except bits 0, 4, 57, and 61 are hardcoded to 1.
-
- @param ECX MSR_P6_MCn_STATUS
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_MC_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_MC_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_MC_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
- AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_P6_MC0_STATUS 0x00000401
-#define MSR_P6_MC1_STATUS 0x00000405
-#define MSR_P6_MC2_STATUS 0x00000409
-#define MSR_P6_MC3_STATUS 0x00000411
-#define MSR_P6_MC4_STATUS 0x0000040D
-/// @}
-
-/**
- MSR information returned for MSR index #MSR_P6_MC0_STATUS to
- #MSR_P6_MC4_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] MC_STATUS_MCACOD.
- ///
- UINT32 MC_STATUS_MCACOD:16;
- ///
- /// [Bits 31:16] MC_STATUS_MSCOD.
- ///
- UINT32 MC_STATUS_MSCOD:16;
- UINT32 Reserved:25;
- ///
- /// [Bit 57] MC_STATUS_DAM.
- ///
- UINT32 MC_STATUS_DAM:1;
- ///
- /// [Bit 58] MC_STATUS_ADDRV.
- ///
- UINT32 MC_STATUS_ADDRV:1;
- ///
- /// [Bit 59] MC_STATUS_MISCV.
- ///
- UINT32 MC_STATUS_MISCV:1;
- ///
- /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is
- /// hardcoded to 1.).
- ///
- UINT32 MC_STATUS_EN:1;
- ///
- /// [Bit 61] MC_STATUS_UC.
- ///
- UINT32 MC_STATUS_UC:1;
- ///
- /// [Bit 62] MC_STATUS_O.
- ///
- UINT32 MC_STATUS_O:1;
- ///
- /// [Bit 63] MC_STATUS_V.
- ///
- UINT32 MC_STATUS_V:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_MC_STATUS_REGISTER;
-
-
-/**
-
- MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.
-
- @param ECX MSR_P6_MC0_ADDR (0x00000402)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
- AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);
- @endcode
- @{
-**/
-#define MSR_P6_MC0_ADDR 0x00000402
-#define MSR_P6_MC1_ADDR 0x00000406
-#define MSR_P6_MC2_ADDR 0x0000040A
-#define MSR_P6_MC3_ADDR 0x00000412
-#define MSR_P6_MC4_ADDR 0x0000040E
-/// @}
-
-
-/**
- Defined in MCA architecture but not implemented in the P6 family processors.
-
- @param ECX MSR_P6_MC0_MISC (0x00000403)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
- AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);
- @endcode
- @{
-**/
-#define MSR_P6_MC0_MISC 0x00000403
-#define MSR_P6_MC1_MISC 0x00000407
-#define MSR_P6_MC2_MISC 0x0000040B
-#define MSR_P6_MC3_MISC 0x00000413
-#define MSR_P6_MC4_MISC 0x0000040F
-/// @}
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h deleted file mode 100644 index caeb5bb035..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h +++ /dev/null @@ -1,2550 +0,0 @@ -/** @file
- MSR Definitions for Pentium(R) 4 Processors.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.
-
-**/
-
-#ifndef __PENTIUM_4_MSR_H__
-#define __PENTIUM_4_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
- Determination.".
-
- @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
- AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)
- Enables and disables processor features; (R) indicates current processor
- configuration.
-
- @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
- AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state
- /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.
- /// The value in this bit is written on the deassertion of RESET#; the bit
- /// is set to 1 when the address bus signal is asserted.
- ///
- UINT32 OutputTriStateEnabled:1;
- ///
- /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST
- /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The
- /// value in this bit is written on the deassertion of RESET#; the bit is
- /// set to 1 when the address bus signal is asserted.
- ///
- UINT32 ExecuteBIST:1;
- ///
- /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue
- /// depth for the system bus is 1 (1) or up to 12 (0) as set by the
- /// strapping of A7#. The value in this bit is written on the deassertion
- /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
- ///
- UINT32 InOrderQueueDepth:1;
- ///
- /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#
- /// observation is enabled (0) or disabled (1) as determined by the
- /// strapping of A9#. The value in this bit is written on the deassertion
- /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
- ///
- UINT32 MCERR_ObservationDisabled:1;
- ///
- /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#
- /// observation is enabled (0) or disabled (1) as determined by the
- /// strapping of A10#. The value in this bit is written on the deassertion
- /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
- ///
- UINT32 BINIT_ObservationEnabled:1;
- ///
- /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID
- /// value as set by the strapping of A12# and A11#. The logical cluster ID
- /// value is written into the field on the deassertion of RESET#; the
- /// field is set to 1 when the address bus signal is asserted.
- ///
- UINT32 APICClusterID:2;
- ///
- /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled
- /// (0) or disabled (1) as set by the strapping of A15#. The value in this
- /// bit is written on the deassertion of RESET#; the bit is set to 1 when
- /// the address bus signal is asserted.
- ///
- UINT32 BusParkDisable:1;
- UINT32 Reserved1:4;
- ///
- /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set
- /// by the strapping of BR[3:0]. The logical ID value is written into the
- /// field on the deassertion of RESET#; the field is set to 1 when the
- /// address bus signal is asserted.
- ///
- UINT32 AgentID:2;
- UINT32 Reserved2:18;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)
- Enables and disables processor features.
-
- @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);
- AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the
- /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear
- /// to disabled (0, default).
- ///
- UINT32 RCNT_SCNT:1;
- ///
- /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data
- /// bus parity checking; clear to enable parity checking.
- ///
- UINT32 DataErrorCheckingDisable:1;
- ///
- /// [Bit 2] Response Error Checking Disable (R/W) Set to disable
- /// (default); clear to enable.
- ///
- UINT32 ResponseErrorCheckingDisable:1;
- ///
- /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable
- /// (default); clear to enable.
- ///
- UINT32 AddressRequestErrorCheckingDisable:1;
- ///
- /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving
- /// for initiator bus requests (default); clear to enable.
- ///
- UINT32 InitiatorMCERR_Disable:1;
- ///
- /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving
- /// for initiator internal errors (default); clear to enable.
- ///
- UINT32 InternalMCERR_Disable:1;
- ///
- /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver
- /// (default); clear to enable driver.
- ///
- UINT32 BINIT_DriverDisable:1;
- UINT32 Reserved1:25;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;
-
-
-/**
- 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of
- this MSR varies according to the MODEL value in the CPUID version
- information. The following bit field layout applies to Pentium 4 and Xeon
- Processors with MODEL encoding equal or greater than 2. (R) The field
- Indicates the current processor frequency configuration.
-
- @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);
- @endcode
-**/
-#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable
- /// bus speed: *EncodingScalable Bus Speed*
- ///
- /// 000B 100 MHz (Model 2).
- /// 000B 266 MHz (Model 3 or 4)
- /// 001B 133 MHz
- /// 010B 200 MHz
- /// 011B 166 MHz
- /// 100B 333 MHz (Model 6)
- ///
- /// 133.33 MHz should be utilized if performing calculation with System
- /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
- /// performing calculation with System Bus Speed when encoding is 011B.
- /// 266.67 MHz should be utilized if performing calculation with System
- /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33
- /// MHz should be utilized if performing calculation with System Bus
- /// Speed when encoding is 100B and model encoding = 6. All other values
- /// are reserved.
- ///
- UINT32 ScalableBusSpeed:3;
- UINT32 Reserved2:5;
- ///
- /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)
- /// The processor core clock frequency to system bus frequency ratio
- /// observed at the de-assertion of the reset pin.
- ///
- UINT32 ClockRatio:8;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;
-
-
-/**
- 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of
- this MSR varies according to the MODEL value of the CPUID version
- information. This bit field layout applies to Pentium 4 and Xeon Processors
- with MODEL encoding less than 2. Indicates current processor frequency
- configuration.
-
- @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);
- @endcode
-**/
-#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:21;
- ///
- /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable
- /// bus speed: *Encoding* *Scalable Bus Speed*
- ///
- /// 000B 100 MHz All others values reserved.
- ///
- UINT32 ScalableBusSpeed:3;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RAX 0x00000180
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RBX 0x00000181
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RCX 0x00000182
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RDX 0x00000183
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RSI 0x00000184
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RDI 0x00000185
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RBP 0x00000186
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RSP 0x00000187
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
- state at time of machine check error. When in non-64-bit modes at the time
- of the error, bits 63-32 do not contain valid data.
-
- @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_RIP 0x00000189
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,
- "IA32_MCG Extended Machine Check State MSRs.".
-
- @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_4_MCG_MISC_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_MISC 0x0000018A
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] DS When set, the bit indicates that a page assist or page
- /// fault occurred during DS normal operation. The processors response is
- /// to shut down. The bit is used as an aid for debugging DS handling
- /// code. It is the responsibility of the user (BIOS or operating system)
- /// to clear this bit for normal operation.
- ///
- UINT32 DS:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_4_MCG_MISC_REGISTER;
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated
- state-save MSRs) exist only in Intel 64 processors. These registers contain
- valid information only when the processor is operating in 64-bit mode at the
- time of the error.
-
- @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_R8 0x00000190
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,
- "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the
- associated state-save MSRs) exist only in Intel 64 processors. These
- registers contain valid information only when the processor is operating in
- 64-bit mode at the time of the error.
-
- @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_R9 0x00000191
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated
- state-save MSRs) exist only in Intel 64 processors. These registers contain
- valid information only when the processor is operating in 64-bit mode at the
- time of the error.
-
- @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_R10 0x00000192
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated
- state-save MSRs) exist only in Intel 64 processors. These registers contain
- valid information only when the processor is operating in 64-bit mode at the
- time of the error.
-
- @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_R11 0x00000193
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated
- state-save MSRs) exist only in Intel 64 processors. These registers contain
- valid information only when the processor is operating in 64-bit mode at the
- time of the error.
-
- @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_R12 0x00000194
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated
- state-save MSRs) exist only in Intel 64 processors. These registers contain
- valid information only when the processor is operating in 64-bit mode at the
- time of the error.
-
- @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_R13 0x00000195
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated
- state-save MSRs) exist only in Intel 64 processors. These registers contain
- valid information only when the processor is operating in 64-bit mode at the
- time of the error.
-
- @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_R14 0x00000196
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated
- state-save MSRs) exist only in Intel 64 processors. These registers contain
- valid information only when the processor is operating in 64-bit mode at the
- time of the error.
-
- @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MCG_R15 0x00000197
-
-
-/**
- Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:
- When read, specifies the value of the target TM2 transition last written.
- When set, it sets the next target value for TM2 transition. 4, 6. Shared.
- For Family F, Model 4 and Model 6 processors: When read, specifies the value
- of the target TM2 transition last written. Writes may cause #GP exceptions.
-
- @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);
- AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).
-
- @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Fast-Strings Enable. See Table 35-2.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.
- ///
- UINT32 FPU:1;
- ///
- /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal
- /// Monitor," and see Table 35-2.
- ///
- UINT32 TM1:1;
- ///
- /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception
- /// to be issued instead of a split-lock cycle. Operating systems that set
- /// this bit must align system structures to avoid split-lock scenarios.
- /// When the bit is clear (default), normal split-locks are issued to the
- /// bus.
- /// This debug feature is specific to the Pentium 4 processor.
- ///
- UINT32 SplitLockDisable:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level
- /// cache is disabled; when clear (default) the third-level cache is
- /// enabled. This flag is reserved for processors that do not have a
- /// third-level cache. Note that the bit controls only the third-level
- /// cache; and only if overall caching is enabled through the CD flag of
- /// control register CR0, the page-level cache controls, and/or the MTRRs.
- /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".
- ///
- UINT32 ThirdLevelCacheDisable:1;
- ///
- /// [Bit 7] Performance Monitoring Available (R) See Table 35-2.
- ///
- UINT32 PerformanceMonitoring:1;
- ///
- /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is
- /// suppressed during a Split Lock access. When clear (default), LOCK is
- /// not suppressed.
- ///
- UINT32 SuppressLockEnable:1;
- ///
- /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.
- /// When clear (default), enables the prefetch queue.
- ///
- UINT32 PrefetchQueueDisable:1;
- ///
- /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt
- /// reporting through the FERR# pin is enabled; when clear, this interrupt
- /// reporting function is disabled.
- /// When this flag is set and the processor is in the stop-clock state
- /// (STPCLK# is asserted), asserting the FERR# pin signals to the
- /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,
- /// SMI#, or RESET#) is pending and that the processor should return to
- /// normal operation to handle the interrupt. This flag does not affect
- /// the normal operation of the FERR# pin (to indicate an unmasked
- /// floatingpoint error) when the STPCLK# pin is not asserted.
- ///
- UINT32 FERR:1;
- ///
- /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See
- /// Table 35-2. When set, the processor does not support branch trace
- /// storage (BTS); when clear, BTS is supported.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] PEBS_UNAVILABLE: Precise Event Based Sampling Unavailable (R)
- /// See Table 35-2. When set, the processor does not support precise
- /// event-based sampling (PEBS); when clear, PEBS is supported.
- ///
- UINT32 PEBS:1;
- ///
- /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal
- /// sensor indicates that the die temperature is at the predetermined
- /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce
- /// the bus to core ratio and voltage according to the value last written
- /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the
- /// processor does not change the VID signals or the bus to core ratio
- /// when the processor enters a thermal managed state. If the TM2 feature
- /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then
- /// this feature is not supported and BIOS must not alter the contents of
- /// this bit location. The processor is operating out of spec if both this
- /// bit and the TM1 bit are set to disabled states.
- ///
- UINT32 TM2:1;
- UINT32 Reserved3:4;
- ///
- /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 35-2.
- ///
- UINT32 MONITOR:1;
- ///
- /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,
- /// the processor fetches the cache line of the 128-byte sector containing
- /// currently required data. When set to 0, the processor fetches both
- /// cache lines in the sector.
- /// Single processor platforms should not set this bit. Server platforms
- /// should set or clear this bit based on platform performance observed
- /// in validation and testing. BIOS may contain a setup option that
- /// controls the setting of this bit.
- ///
- UINT32 AdjacentCacheLinePrefetchDisable:1;
- UINT32 Reserved4:2;
- ///
- /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 35-2. Setting
- /// this can cause unexpected behavior to software that depends on the
- /// availability of CPUID leaves greater than 3.
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
- ///
- UINT32 xTPR_Message_Disable:1;
- ///
- /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache
- /// is placed in shared mode; when clear (default), the cache is placed in
- /// adaptive mode. This bit is only enabled for IA-32 processors that
- /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data
- /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are
- /// identical, data in L1 is shared across logical processors. Otherwise,
- /// L1 is not shared and cache use is competitive. If the Context ID
- /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,
- /// the ability to switch modes is not supported. BIOS must not alter the
- /// contents of IA32_MISC_ENABLE[24].
- ///
- UINT32 L1DataCacheContextMode:1;
- UINT32 Reserved5:7;
- UINT32 Reserved6:2;
- ///
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
- ///
- UINT32 XD:1;
- UINT32 Reserved7:29;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- 3, 4, 6. Shared. Platform Feature Requirements (R).
-
- @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);
- @endcode
-**/
-#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:18;
- ///
- /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor
- /// has specific platform requirements. The details of the platform
- /// requirements are listed in the respective data sheets of the processor.
- ///
- UINT32 PLATFORM:1;
- UINT32 Reserved2:13;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains
- a pointer to the last branch instruction that the processor executed prior
- to the last exception that was generated or the last interrupt that was
- handled. See Section 17.10.3, "Last Exception Records.". Unique. From Linear
- IP Linear address of the last branch instruction (If IA32e mode is active).
- From Linear IP Linear address of the last branch instruction. Reserved.
-
- @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area
- contains a pointer to the target of the last branch instruction that the
- processor executed prior to the last exception that was generated or the
- last interrupt that was handled. See Section 17.10.3, "Last Exception
- Records.". Unique. From Linear IP Linear address of the target of the last
- branch instruction (If IA-32e mode is active). From Linear IP Linear address
- of the target of the last branch instruction. Reserved.
-
- @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);
- @endcode
-**/
-#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug
- features are used. Bit definitions are discussed in the referenced section.
- See Section 17.10.1, "MSR_DEBUGCTLA MSR.".
-
- @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);
- AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9
-
-
-/**
- 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an
- index (0-3 or 0-15) that points to the top of the last branch record stack
- (that is, that points the index of the MSR containing the most recent branch
- record). See Section 17.10.2, "LBR Stack for Processors Based on Intel
- NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
-
- @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA
-
-
-/**
- 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record
- registers on the last branch record stack. It contains pointers to the
- source and destination instruction for one of the last four branches,
- exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
- MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
- 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
- Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording
- for Processors based on Skylake Microarchitecture.".
-
- @param ECX MSR_PENTIUM_4_LASTBRANCH_n
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
- AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB
-#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC
-#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD
-#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
-
- @param ECX MSR_PENTIUM_4_BPU_COUNTERn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
- AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300
-#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301
-#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302
-#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
-
- @param ECX MSR_PENTIUM_4_MS_COUNTERn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
- AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304
-#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305
-#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306
-#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
-
- @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
- AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308
-#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309
-#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A
-#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
-
- @param ECX MSR_PENTIUM_4_IQ_COUNTERn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
- AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C
-#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D
-#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E
-#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F
-#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310
-#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_BPU_CCCRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360
-#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361
-#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362
-#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_MS_CCCRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_MS_CCCR0 0x00000364
-#define MSR_PENTIUM_4_MS_CCCR1 0x00000365
-#define MSR_PENTIUM_4_MS_CCCR2 0x00000366
-#define MSR_PENTIUM_4_MS_CCCR3 0x00000367
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_FLAME_CCCRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368
-#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369
-#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A
-#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_IQ_CCCRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C
-#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D
-#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E
-#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F
-#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370
-#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9
-
-
-/**
- 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available
- on later processors. It is only available on processor family 0FH, models
- 01H-02H.
-
- @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA
-
-
-/**
- 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available
- on later processors. It is only available on processor family 0FH, models
- 01H-02H.
-
- @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);
- AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_ALF_ESCRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
- AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA
-#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB
-#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC
-#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD
-#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0
-#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1
-/// @}
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
-
- @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);
- AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. Precise Event-Based Sampling (PEBS) (R/W)
- Controls the enabling of precise event sampling and replay tagging.
-
- @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 12:0] See Table 19-26.
- ///
- UINT32 EventNum:13;
- UINT32 Reserved1:11;
- ///
- /// [Bit 24] UOP Tag Enables replay tagging when set.
- ///
- UINT32 UOP:1;
- ///
- /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
- /// processor when set; disables PEBS when clear (default). See Section
- /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
- /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
- /// that do not support Intel HyperThreading Technology.
- ///
- UINT32 ENABLE_PEBS_MY_THR:1;
- ///
- /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
- /// processor when set; disables PEBS when clear (default). See Section
- /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
- /// logical processor. This bit is reserved for IA-32 processors that do
- /// not support Intel Hyper-Threading Technology.
- ///
- UINT32 ENABLE_PEBS_OTH_THR:1;
- UINT32 Reserved2:5;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;
-
-
-/**
- 0, 1, 2, 3, 4, 6. Shared. See Table 19-26.
-
- @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);
- AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2
-
-
-/**
- 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch
- record registers on the last branch record stack (680H-68FH). This part of
- the stack contains pointers to the source instruction for one of the last 16
- branches, exceptions, or interrupts taken by the processor. The MSRs at
- 680H-68FH, 6C0H-6CfH are not available in processor releases before family
- 0FH, model 03H. These MSRs replace MSRs previously located at
- 1DBH-1DEH.which performed the same function for early releases. See Section
- 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording for
- Processors based on Skylake Microarchitecture.".
-
- @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
- AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680
-#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681
-#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682
-#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683
-#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684
-#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685
-#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686
-#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687
-#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688
-#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689
-#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A
-#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B
-#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C
-#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D
-#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E
-#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F
-/// @}
-
-
-/**
- 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch
- record registers on the last branch record stack (6C0H-6CFH). This part of
- the stack contains pointers to the destination instruction for one of the
- last 16 branches, exceptions, or interrupts that the processor took. See
- Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording
- for Processors based on Skylake Microarchitecture.".
-
- @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
- AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0
-#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1
-#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2
-#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3
-#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4
-#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5
-#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6
-#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7
-#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8
-#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9
-#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA
-#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB
-#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC
-#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD
-#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE
-#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF
-/// @}
-
-
-/**
- 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
- with Up to 8-MByte L3 Cache.".
-
- @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC
-
-
-/**
- 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).
-
- @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD
-
-
-/**
- 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
- with Up to 8-MByte L3 Cache.".
-
- @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE
-
-
-/**
- 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).
-
- @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF
-
-
-/**
- 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
- with Up to 8-MByte L3 Cache" for details.
-
- @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);
- AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0
-
-
-/**
- 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).
-
- @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);
- AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1
-
-
-/**
- 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.17,
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
- L3 Cache" for details.
-
- @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2
-
-
-/**
- 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.17,
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
- L3 Cache.".
-
- @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3
-
-
-/**
- 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.17,
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
- L3 Cache.".
-
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC
-
-
-/**
- 6. Shared. GBUSQ Event Control and Counter Register (R/W).
-
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD
-
-
-/**
- 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
- 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
- 8-MByte L3 Cache.".
-
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE
-
-
-/**
- 6. Shared. GSNPQ Event Control and Counter Register (R/W).
-
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF
-
-
-/**
- 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.17,
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
- L3 Cache" for details.
-
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0
-
-
-/**
- 6. Shared. FSB Event Control and Counter Register (R/W).
-
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1
-
-
-/**
- 6. Shared. FSB Event Control and Counter Register (R/W).
-
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2
-
-
-/**
- 6. Shared. FSB Event Control and Counter Register (R/W).
-
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h deleted file mode 100644 index 324fc9b88c..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h +++ /dev/null @@ -1,643 +0,0 @@ -/** @file
- MSR Definitions for Pentium M Processors.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18.
-
-**/
-
-#ifndef __PENTIUM_M_MSR_H__
-#define __PENTIUM_M_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- See Section 35.20, "MSRs in Pentium Processors.".
-
- @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
- AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
-
-
-/**
- See Section 35.20, "MSRs in Pentium Processors.".
-
- @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
- AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
-
-
-/**
- Processor Hard Power-On Configuration (R/W) Enables and disables processor
- features. (R) Indicates current processor configuration.
-
- @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
- AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
- /// Pentium M processor.
- ///
- UINT32 DataErrorCheckingEnable:1;
- ///
- /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
- /// the Pentium M processor.
- ///
- UINT32 ResponseErrorCheckingEnable:1;
- ///
- /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
- /// M processor.
- ///
- UINT32 MCERR_DriveEnable:1;
- ///
- /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
- /// M processor.
- ///
- UINT32 AddressParityEnable:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
- /// the Pentium M processor.
- ///
- UINT32 BINIT_DriverEnable:1;
- ///
- /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 OutputTriStateEnable:1;
- ///
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 ExecuteBIST:1;
- ///
- /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
- /// Always 0 on the Pentium M processor.
- ///
- UINT32 MCERR_ObservationEnabled:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
- /// Always 0 on the Pentium M processor.
- ///
- UINT32 BINIT_ObservationEnabled:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
- /// Always 0 on the Pentium M processor.
- ///
- UINT32 ResetVector:1;
- UINT32 Reserved5:1;
- ///
- /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
- /// processor.
- ///
- UINT32 APICClusterID:2;
- ///
- /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
- /// 0 on the Pentium M processor.
- ///
- UINT32 SystemBusFrequency:1;
- UINT32 Reserved6:1;
- ///
- /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
- /// M processor.
- ///
- UINT32 SymmetricArbitrationID:2;
- ///
- /// [Bits 26:22] Clock Frequency Ratio (R/O).
- ///
- UINT32 ClockFrequencyRatio:5;
- UINT32 Reserved7:5;
- UINT32 Reserved8:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
-
-
-/**
- Last Branch Record n (R/W) One of 8 last branch record registers on the last
- branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
- the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
- 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M
- Processors)".
-
- @param ECX MSR_PENTIUM_M_LASTBRANCH_n
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
- AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
-#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
-#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
-#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
-#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
-#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
-#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
-#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
-/// @}
-
-
-/**
- Reserved.
-
- @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
- AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
-
-
-/**
-
-
- @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
- AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
- /// Indicates if the L2 is hardware-disabled.
- ///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:4;
- ///
- /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
- /// cache data bus. ECC is always generated on write cycles. 1. = Disabled
- /// (default) 2. = Enabled For the Pentium M processor, ECC checking on
- /// the cache data bus is always enabled.
- ///
- UINT32 ECCCheckEnable:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
- /// Disabled (default) Until this bit is set the processor will not
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
- ///
- UINT32 L2Enabled:1;
- UINT32 Reserved3:14;
- ///
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
- ///
- UINT32 L2NotPresent:1;
- UINT32 Reserved4:8;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
-
-
-/**
-
-
- @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
- AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
- ///
- UINT32 TM_SELECT:1;
- UINT32 Reserved2:15;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_M_THERM2_CTL_REGISTER;
-
-
-/**
- Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:3;
- ///
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
- /// this bit enables the thermal control circuit (TCC) portion of the
- /// Intel Thermal Monitor feature. This allows processor clocks to be
- /// automatically modulated based on the processor's thermal sensor
- /// operation. 0 = Disabled (default). The automatic thermal control
- /// circuit enable bit determines if the thermal control circuit (TCC)
- /// will be activated when the processor's internal thermal sensor
- /// determines the processor is about to exceed its maximum operating
- /// temperature. When the TCC is activated and TM1 is enabled, the
- /// processors clocks will be forced to a 50% duty cycle. BIOS must enable
- /// this feature. The bit should not be confused with the on-demand
- /// thermal control circuit enable bit.
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
- /// monitoring enabled 0 = Performance monitoring disabled.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
- /// processor to indicate a pending break event within the processor 0 =
- /// Indicates compatible FERR# signaling behavior This bit must be set to
- /// 1 to support XAPIC interrupt model usage.
- /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
- /// support branch trace storage (BTS) 0 = BTS is supported
- ///
- UINT32 FERR:1;
- ///
- /// [Bit 11] Branch Trace Storage Unavailable (RO)
- /// 1 = Processor doesn't support branch trace storage (BTS)
- /// 0 = BTS is supported
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Precise Event Based Sampling Unavailable (RO) 1 = Processor
- /// does not support precise event-based sampling (PEBS); 0 = PEBS is
- /// supported. The Pentium M processor does not support PEBS.
- ///
- UINT32 PEBS:1;
- UINT32 Reserved5:3;
- ///
- /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
- /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
- /// processor, this bit may be configured to be read-only.
- ///
- UINT32 EIST:1;
- UINT32 Reserved6:6;
- ///
- /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
- /// disabled. xTPR messages are optional messages that allow the processor
- /// to inform the chipset of its priority. The default is processor
- /// specific.
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
- to the MSR containing the most recent branch record. See also: -
- MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.12, "Last Branch, Interrupt,
- and Exception Recording (Pentium M Processors)".
-
- @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Debug Control (R/W) Controls how several debug features are used. Bit
- definitions are discussed in the referenced section. See Section 17.12,
- "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
-
- @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
- AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
-
-
-/**
- Last Exception Record To Linear IP (R) This area contains a pointer to the
- target of the last branch instruction that the processor executed prior to
- the last exception that was generated or the last interrupt that was
- handled. See Section 17.12, "Last Branch, Interrupt, and Exception Recording
- (Pentium M Processors)" and Section 17.13.2, "Last Branch and Last Exception
- MSRs.".
-
- @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
- @endcode
-**/
-#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
-
-
-/**
- Last Exception Record From Linear IP (R) Contains a pointer to the last
- branch instruction that the processor executed prior to the last exception
- that was generated or the last interrupt that was handled. See Section
- 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M
- Processors)" and Section 17.13.2, "Last Branch and Last Exception MSRs.".
-
- @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
-
-
-/**
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_MC4_CTL 0x0000040C
-
-
-/**
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
-
-
-/**
- See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
- either not implemented or contains no address if the ADDRV flag in the
- MSR_MC4_STATUS register is clear. When not implemented in the processor, all
- reads and writes to this MSR will cause a general-protection exception.
-
- @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
-
-
-/**
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_MC3_CTL 0x00000410
-
-
-/**
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_MC3_STATUS 0x00000411
-
-
-/**
- See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
- either not implemented or contains no address if the ADDRV flag in the
- MSR_MC3_STATUS register is clear. When not implemented in the processor, all
- reads and writes to this MSR will cause a general-protection exception.
-
- @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_M_MC3_ADDR 0x00000412
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h deleted file mode 100644 index a8916b4a44..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h +++ /dev/null @@ -1,121 +0,0 @@ -/** @file
- MSR Definitions for Pentium Processors.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20.
-
-**/
-
-#ifndef __PENTIUM_MSR_H__
-#define __PENTIUM_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
-
- @param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
- AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_P5_MC_ADDR 0x00000000
-
-
-/**
- See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
-
- @param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
- AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_P5_MC_TYPE 0x00000001
-
-
-/**
- See Section 17.14, "Time-Stamp Counter.".
-
- @param ECX MSR_PENTIUM_TSC (0x00000010)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
- AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_TSC 0x00000010
-
-
-/**
- See Section 18.20.1, "Control and Event Select Register (CESR).".
-
- @param ECX MSR_PENTIUM_CESR (0x00000011)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
- AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
- @endcode
-**/
-#define MSR_PENTIUM_CESR 0x00000011
-
-
-/**
- Section 18.20.3, "Events Counted.".
-
- @param ECX MSR_PENTIUM_CTRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
- AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
- @endcode
- @{
-**/
-#define MSR_PENTIUM_CTR0 0x00000012
-#define MSR_PENTIUM_CTR1 0x00000013
-/// @}
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h deleted file mode 100644 index c41e45b414..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h +++ /dev/null @@ -1,4703 +0,0 @@ -/** @file
- MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8.
-
-**/
-
-#ifndef __SANDY_BRIDGE_MSR_H__
-#define __SANDY_BRIDGE_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Thread. SMI Counter (R/O).
-
- @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] SMI Count (R/O) Count SMIs.
- ///
- UINT32 SMICount:32;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;
-
-
-/**
- Package. See http://biosbits.org.
-
- @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
- /// MHz.
- ///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:12;
- ///
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for
- /// Turbo mode is disabled.
- ///
- UINT32 RatioLimit:1;
- ///
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
- /// and when set to 0, indicates TDP Limit for Turbo mode is not
- /// programmable.
- ///
- UINT32 TDPLimit:1;
- UINT32 Reserved3:2;
- UINT32 Reserved4:8;
- ///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
- /// minimum ratio (maximum efficiency) that the processor can operates, in
- /// units of 100MHz.
- ///
- UINT32 MaximumEfficiencyRatio:8;
- UINT32 Reserved5:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;
-
-
-/**
- Core. C-State Configuration Control (R/W) Note: C-state values are
- processor specific C-state code names, unrelated to MWAIT extension C-state
- parameters or ACPI CStates. See http://biosbits.org.
-
- @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index
- #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
- /// processor-specific C-state code name (consuming the least power). for
- /// the package. The default is set as factory-configured package C-state
- /// limit. The following C-state code name encodings are supported: 000b:
- /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
- /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
- /// This field cannot be used to limit package C-state to C3.
- ///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
- /// IO_read instructions sent to IO register specified by
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
- /// until next reset.
- ///
- UINT32 CFGLock:1;
- UINT32 Reserved3:9;
- ///
- /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
- /// will conditionally demote C6/C7 requests to C3 based on uncore
- /// auto-demote information.
- ///
- UINT32 C3AutoDemotion:1;
- ///
- /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
- /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
- /// auto-demote information.
- ///
- UINT32 C1AutoDemotion:1;
- ///
- /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
- /// demoted C3.
- ///
- UINT32 C3Undemotion:1;
- ///
- /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
- /// demoted C1.
- ///
- UINT32 C1Undemotion:1;
- UINT32 Reserved4:3;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- Core. Power Management IO Redirection in C-state (R/W) See
- http://biosbits.org.
-
- @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
- /// visible to software for IO redirection. If IO MWAIT Redirection is
- /// enabled, reads to this address will be consumed by the power
- /// management logic and decoded to MWAIT instructions. When IO port
- /// address redirection is enabled, this is the IO port address reported
- /// to the OS/software.
- ///
- UINT32 Lvl2Base:16;
- ///
- /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
- /// maximum C-State code name to be included when IO read to MWAIT
- /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
- /// is the max C-State to include 001b - C6 is the max C-State to include
- /// 010b - C7 is the max C-State to include.
- ///
- UINT32 CStateRange:3;
- UINT32 Reserved1:13;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;
-
-
-/**
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
- handler to handle unsuccessful read of this MSR.
-
- @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
- /// MSR, the configuration of AES instruction set availability is as
- /// follows: 11b: AES instructions are not available until next RESET.
- /// otherwise, AES instructions are available. Note, AES instruction set
- /// is not available if read is unsuccessful. If the configuration is not
- /// 01b, AES instruction can be mis-configured if a privileged agent
- /// unintentionally writes 11b.
- ///
- UINT32 AESConfiguration:2;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;
-
-
-/**
- Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.
-
- @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
- @endcode
- @{
-**/
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D
-/// @}
-
-
-/**
- Package.
-
- @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- ///
- /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed
- /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
- ///
- UINT32 CoreVoltage:16;
- UINT32 Reserved2:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;
-
-
-/**
- Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was
- originally named IA32_THERM_CONTROL MSR.
-
- @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A
-
-/**
- MSR information returned for MSR index
- #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%
- /// increment.
- ///
- UINT32 OnDemandClockModulationDutyCycle:4;
- ///
- /// [Bit 4] On demand Clock Modulation Enable (R/W).
- ///
- UINT32 OnDemandClockModulationEnable:1;
- UINT32 Reserved1:27;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;
-
-
-/**
- Enable Misc. Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:6;
- ///
- /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
- ///
- UINT32 PEBS:1;
- UINT32 Reserved3:3;
- ///
- /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 EIST:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
- ///
- UINT32 MONITOR:1;
- UINT32 Reserved5:3;
- ///
- /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved6:8;
- UINT32 Reserved7:2;
- ///
- /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
- ///
- UINT32 XD:1;
- UINT32 Reserved8:3;
- ///
- /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
- /// that support Intel Turbo Boost Technology, the turbo mode feature is
- /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
- /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
- /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
- /// the power-on default value is used by BIOS to detect hardware support
- /// of turbo mode. If power-on default value is 1, turbo mode is available
- /// in the processor. If power-on default value is 0, turbo mode is not
- /// available.
- ///
- UINT32 TurboModeDisable:1;
- UINT32 Reserved9:25;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Unique.
-
- @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
- /// PROCHOT# will be asserted. The value is degree C.
- ///
- UINT32 TemperatureTarget:8;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
-
-
-/**
- Miscellaneous Feature Control (R/W).
-
- @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
- /// L2 hardware prefetcher, which fetches additional lines of code or data
- /// into the L2 cache.
- ///
- UINT32 L2HardwarePrefetcherDisable:1;
- ///
- /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
- /// disables the adjacent cache line prefetcher, which fetches the cache
- /// line that comprises a cache line pair (128 bytes).
- ///
- UINT32 L2AdjacentCacheLinePrefetcherDisable:1;
- ///
- /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
- /// the L1 data cache prefetcher, which fetches the next cache line into
- /// L1 data cache.
- ///
- UINT32 DCUHardwarePrefetcherDisable:1;
- ///
- /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
- /// data cache IP prefetcher, which uses sequential load history (based on
- /// instruction Pointer of previous loads) to determine whether to
- /// prefetch additional lines.
- ///
- UINT32 DCUIPPrefetcherDisable:1;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;
-
-
-/**
- Thread. Offcore Response Event Select Register (R/W).
-
- @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6
-
-
-/**
- Thread. Offcore Response Event Select Register (R/W).
-
- @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7
-
-
-/**
- See http://biosbits.org.
-
- @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA
-
-
-/**
- Thread. Last Branch Record Filtering Select Register (R/W) See Section
- 17.6.2, "Filtering of Last Branch Records.".
-
- @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] CPL_EQ_0.
- ///
- UINT32 CPL_EQ_0:1;
- ///
- /// [Bit 1] CPL_NEQ_0.
- ///
- UINT32 CPL_NEQ_0:1;
- ///
- /// [Bit 2] JCC.
- ///
- UINT32 JCC:1;
- ///
- /// [Bit 3] NEAR_REL_CALL.
- ///
- UINT32 NEAR_REL_CALL:1;
- ///
- /// [Bit 4] NEAR_IND_CALL.
- ///
- UINT32 NEAR_IND_CALL:1;
- ///
- /// [Bit 5] NEAR_RET.
- ///
- UINT32 NEAR_RET:1;
- ///
- /// [Bit 6] NEAR_IND_JMP.
- ///
- UINT32 NEAR_IND_JMP:1;
- ///
- /// [Bit 7] NEAR_REL_JMP.
- ///
- UINT32 NEAR_REL_JMP:1;
- ///
- /// [Bit 8] FAR_BRANCH.
- ///
- UINT32 FAR_BRANCH:1;
- UINT32 Reserved1:23;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;
-
-
-/**
- Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
- that points to the MSR containing the most recent branch record. See
- MSR_LASTBRANCH_0_FROM_IP (at 680H).
-
- @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
- last branch instruction that the processor executed prior to the last
- exception that was generated or the last interrupt that was handled.
-
- @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD
-
-
-/**
- Thread. Last Exception Record To Linear IP (R) This area contains a pointer
- to the target of the last branch instruction that the processor executed
- prior to the last exception that was generated or the last interrupt that
- was handled.
-
- @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE
-
-
-/**
- Core. See http://biosbits.org.
-
- @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC
-
-
-/**
- Package. Always 0 (CMCI not supported).
-
- @param ECX MSR_SANDY_BRIDGE_MC4_CTL2 (0x00000284)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_MC4_CTL2 0x00000284
-
-
-/**
- See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
-
- @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-/**
- MSR information returned for MSR index
- #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thread. Ovf_PMC0.
- ///
- UINT32 Ovf_PMC0:1;
- ///
- /// [Bit 1] Thread. Ovf_PMC1.
- ///
- UINT32 Ovf_PMC1:1;
- ///
- /// [Bit 2] Thread. Ovf_PMC2.
- ///
- UINT32 Ovf_PMC2:1;
- ///
- /// [Bit 3] Thread. Ovf_PMC3.
- ///
- UINT32 Ovf_PMC3:1;
- ///
- /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
- ///
- UINT32 Ovf_PMC4:1;
- ///
- /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
- ///
- UINT32 Ovf_PMC5:1;
- ///
- /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
- ///
- UINT32 Ovf_PMC6:1;
- ///
- /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
- ///
- UINT32 Ovf_PMC7:1;
- UINT32 Reserved1:24;
- ///
- /// [Bit 32] Thread. Ovf_FixedCtr0.
- ///
- UINT32 Ovf_FixedCtr0:1;
- ///
- /// [Bit 33] Thread. Ovf_FixedCtr1.
- ///
- UINT32 Ovf_FixedCtr1:1;
- ///
- /// [Bit 34] Thread. Ovf_FixedCtr2.
- ///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:26;
- ///
- /// [Bit 61] Thread. Ovf_Uncore.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Thread. Ovf_BufDSSAVE.
- ///
- UINT32 Ovf_BufDSSAVE:1;
- ///
- /// [Bit 63] Thread. CondChgd.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER;
-
-
-/**
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F
-
-/**
- MSR information returned for MSR index
- #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thread. Set 1 to enable PMC0 to count.
- ///
- UINT32 PCM0_EN:1;
- ///
- /// [Bit 1] Thread. Set 1 to enable PMC1 to count.
- ///
- UINT32 PCM1_EN:1;
- ///
- /// [Bit 2] Thread. Set 1 to enable PMC2 to count.
- ///
- UINT32 PCM2_EN:1;
- ///
- /// [Bit 3] Thread. Set 1 to enable PMC3 to count.
- ///
- UINT32 PCM3_EN:1;
- ///
- /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >
- /// 4).
- ///
- UINT32 PCM4_EN:1;
- ///
- /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >
- /// 5).
- ///
- UINT32 PCM5_EN:1;
- ///
- /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >
- /// 6).
- ///
- UINT32 PCM6_EN:1;
- ///
- /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >
- /// 7).
- ///
- UINT32 PCM7_EN:1;
- UINT32 Reserved1:24;
- ///
- /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.
- ///
- UINT32 FIXED_CTR0:1;
- ///
- /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.
- ///
- UINT32 FIXED_CTR1:1;
- ///
- /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.
- ///
- UINT32 FIXED_CTR2:1;
- UINT32 Reserved2:29;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;
-
-
-/**
- See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
-
- @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
-
-/**
- MSR information returned for MSR index
- #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
- ///
- UINT32 Ovf_PMC0:1;
- ///
- /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
- ///
- UINT32 Ovf_PMC1:1;
- ///
- /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
- ///
- UINT32 Ovf_PMC2:1;
- ///
- /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
- ///
- UINT32 Ovf_PMC3:1;
- ///
- /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
- ///
- UINT32 Ovf_PMC4:1;
- ///
- /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
- ///
- UINT32 Ovf_PMC5:1;
- ///
- /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
- ///
- UINT32 Ovf_PMC6:1;
- ///
- /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
- ///
- UINT32 Ovf_PMC7:1;
- UINT32 Reserved1:24;
- ///
- /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
- ///
- UINT32 Ovf_FixedCtr0:1;
- ///
- /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
- ///
- UINT32 Ovf_FixedCtr1:1;
- ///
- /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
- ///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:26;
- ///
- /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
- ///
- UINT32 Ovf_BufDSSAVE:1;
- ///
- /// [Bit 63] Thread. Set 1 to clear CondChgd.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;
-
-
-/**
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
-
- @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
- ///
- UINT32 PEBS_EN_PMC0:1;
- ///
- /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
- ///
- UINT32 PEBS_EN_PMC1:1;
- ///
- /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
- ///
- UINT32 PEBS_EN_PMC2:1;
- ///
- /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
- ///
- UINT32 PEBS_EN_PMC3:1;
- UINT32 Reserved1:28;
- ///
- /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
- ///
- UINT32 LL_EN_PMC0:1;
- ///
- /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
- ///
- UINT32 LL_EN_PMC1:1;
- ///
- /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
- ///
- UINT32 LL_EN_PMC2:1;
- ///
- /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
- ///
- UINT32 LL_EN_PMC3:1;
- UINT32 Reserved2:27;
- ///
- /// [Bit 63] Enable Precise Store. (R/W).
- ///
- UINT32 PS_EN:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;
-
-
-/**
- Thread. see See Section 18.7.1.2, "Load Latency Performance Monitoring
- Facility.".
-
- @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Minimum threshold latency value of tagged load operation
- /// that will be counted. (R/W).
- ///
- UINT32 MinimumThreshold:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
- Residency Counter. (R/O) Value since last reset that this package is in
- processor-specific C3 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
- Residency Counter. (R/O) Value since last reset that this package is in
- processor-specific C6 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
- Residency Counter. (R/O) Value since last reset that this package is in
- processor-specific C7 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA
-
-
-/**
- Core. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
- Residency Counter. (R/O) Value since last reset that this core is in
- processor-specific C3 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC
-
-
-/**
- Core. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
- Residency Counter. (R/O) Value since last reset that this core is in
- processor-specific C6 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD
-
-
-/**
- Core. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7
- Residency Counter. (R/O) Value since last reset that this core is in
- processor-specific C7 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE
-
-
-/**
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_SANDY_BRIDGE_MC4_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_MC4_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_MC4_CTL 0x00000410
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_MC4_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU
- /// hardware detected errors.
- ///
- UINT32 PCUHardwareError:1;
- ///
- /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU
- /// controller detected errors.
- ///
- UINT32 PCUControllerError:1;
- ///
- /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU
- /// firmware detected errors.
- ///
- UINT32 PCUFirmwareError:1;
- UINT32 Reserved1:29;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_MC4_CTL_REGISTER;
-
-
-/**
- Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
-
- @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C
-
-
-/**
- Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
- "RAPL Interfaces.".
-
- @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606
-
-
-/**
- Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
- processor specific C-state code names, unrelated to MWAIT extension C-state
- parameters or ACPI CStates.
-
- @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
- /// that should be used to decide if the package should be put into a
- /// package C3 state.
- ///
- UINT32 TimeLimit:10;
- ///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. The following time unit
- /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
- /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
- ///
- UINT32 TimeUnit:3;
- UINT32 Reserved1:2;
- ///
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
- /// valid and can be used by the processor for package C-sate management.
- ///
- UINT32 Valid:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;
-
-
-/**
- Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the
- budget allocated for the package to exit from C6 to a C0 state, where
- interrupt request can be delivered to the core and serviced. Additional
- core-exit latency amy be applicable depending on the actual C-state the core
- is in. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates.
-
- @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
- /// that should be used to decide if the package should be put into a
- /// package C6 state.
- ///
- UINT32 TimeLimit:10;
- ///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. The following time unit
- /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
- /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
- ///
- UINT32 TimeUnit:3;
- UINT32 Reserved1:2;
- ///
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
- /// valid and can be used by the processor for package C-sate management.
- ///
- UINT32 Valid:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
- Residency Counter. (R/O) Value since last reset that this package is in
- processor-specific C2 states. Count at the same frequency as the TSC.
-
- @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D
-
-
-/**
- Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
- RAPL Domain.".
-
- @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610
-
-
-/**
- Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
-
- @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611
-
-
-/**
- Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
- Domain.".
-
- @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614
-
-
-/**
- Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
- RAPL Domains.".
-
- @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638
-
-
-/**
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
- Domains.".
-
- @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
-
-
-/**
- Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
- branch record registers on the last branch record stack. This part of the
- stack contains pointers to the source instruction. See also: - Last Branch
- Record Stack TOS at 1C9H - Section 17.6.1, "LBR Stack.".
-
- @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680
-#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681
-#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682
-#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683
-#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684
-#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685
-#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686
-#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687
-#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688
-#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689
-#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A
-#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B
-#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C
-#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D
-#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E
-#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F
-/// @}
-
-
-/**
- Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction.
-
- @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0
-#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1
-#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2
-#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3
-#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4
-#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5
-#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6
-#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7
-#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8
-#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9
-#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA
-#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB
-#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC
-#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD
-#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE
-#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF
-/// @}
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
- /// limit of 1 core active.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
- /// limit of 2 core active.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
- /// limit of 3 core active.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
- /// limit of 4 core active.
- ///
- UINT32 Maximum4C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
- /// limit of 5 core active.
- ///
- UINT32 Maximum5C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
- /// limit of 6 core active.
- ///
- UINT32 Maximum6C:8;
- ///
- /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
- /// limit of 7 core active.
- ///
- UINT32 Maximum7C:8;
- ///
- /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
- /// limit of 8 core active.
- ///
- UINT32 Maximum8C:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Package. Uncore PMU global control.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Core 0 select.
- ///
- UINT32 PMI_Sel_Core0:1;
- ///
- /// [Bit 1] Core 1 select.
- ///
- UINT32 PMI_Sel_Core1:1;
- ///
- /// [Bit 2] Core 2 select.
- ///
- UINT32 PMI_Sel_Core2:1;
- ///
- /// [Bit 3] Core 3 select.
- ///
- UINT32 PMI_Sel_Core3:1;
- UINT32 Reserved1:15;
- UINT32 Reserved2:10;
- ///
- /// [Bit 29] Enable all uncore counters.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 30] Enable wake on PMI.
- ///
- UINT32 WakePMI:1;
- ///
- /// [Bit 31] Enable Freezing counter when overflow.
- ///
- UINT32 FREEZE:1;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;
-
-
-/**
- Package. Uncore PMU main status.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392
-
-/**
- MSR information returned for MSR index
- #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Fixed counter overflowed.
- ///
- UINT32 Fixed:1;
- ///
- /// [Bit 1] An ARB counter overflowed.
- ///
- UINT32 ARB:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 3] A CBox counter overflowed (on any slice).
- ///
- UINT32 CBox:1;
- UINT32 Reserved2:28;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;
-
-
-/**
- Package. Uncore fixed counter control (R/W).
-
- @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:20;
- ///
- /// [Bit 20] Enable overflow propagation.
- ///
- UINT32 EnableOverflow:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 22] Enable counting.
- ///
- UINT32 EnableCounting:1;
- UINT32 Reserved3:9;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;
-
-
-/**
- Package. Uncore fixed counter.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Current count.
- ///
- UINT32 CurrentCount:32;
- ///
- /// [Bits 47:32] Current count.
- ///
- UINT32 CurrentCountHi:16;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;
-
-
-/**
- Package. Uncore C-Box configuration information (R/O).
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
- ///
- UINT32 CBox:4;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;
-
-
-/**
- Package. Uncore Arb unit, performance counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0
-
-
-/**
- Package. Uncore Arb unit, performance counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1
-
-
-/**
- Package. Uncore Arb unit, counter 0 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2
-
-
-/**
- Package. Uncore Arb unit, counter 1 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3
-
-
-/**
- Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the
- budget allocated for the package to exit from C7 to a C0 state, where
- interrupt request can be delivered to the core and serviced. Additional
- core-exit latency amy be applicable depending on the actual C-state the core
- is in. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates.
-
- @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
- /// that should be used to decide if the package should be put into a
- /// package C7 state.
- ///
- UINT32 TimeLimit:10;
- ///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. The following time unit
- /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
- /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
- ///
- UINT32 TimeUnit:3;
- UINT32 Reserved1:2;
- ///
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
- /// valid and can be used by the processor for package C-sate management.
- ///
- UINT32 Valid:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;
-
-
-/**
- Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
- Domains.".
-
- @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A
-
-
-/**
- Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
- RAPL Domains.".
-
- @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640
-
-
-/**
- Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
- Domains.".
-
- @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641
-
-
-/**
- Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
- Domains.".
-
- @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642
-
-
-/**
- Package. Uncore C-Box 0, counter 0 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700
-
-
-/**
- Package. Uncore C-Box 0, counter 1 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
-
-
-/**
- Package. Uncore C-Box 0, performance counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 (0x00000706)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706
-
-
-/**
- Package. Uncore C-Box 0, performance counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 (0x00000707)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707
-
-
-/**
- Package. Uncore C-Box 1, counter 0 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710
-
-
-/**
- Package. Uncore C-Box 1, counter 1 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711
-
-
-/**
- Package. Uncore C-Box 1, performance counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 (0x00000716)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716
-
-
-/**
- Package. Uncore C-Box 1, performance counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 (0x00000717)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717
-
-
-/**
- Package. Uncore C-Box 2, counter 0 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720
-
-
-/**
- Package. Uncore C-Box 2, counter 1 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721
-
-
-/**
- Package. Uncore C-Box 2, performance counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 (0x00000726)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726
-
-
-/**
- Package. Uncore C-Box 2, performance counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 (0x00000727)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727
-
-
-/**
- Package. Uncore C-Box 3, counter 0 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730
-
-
-/**
- Package. Uncore C-Box 3, counter 1 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
-
-
-/**
- Package. Uncore C-Box 3, performance counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 (0x00000736)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
-
-
-/**
- Package. Uncore C-Box 3, performance counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 (0x00000737)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
-
-
-/**
- Package. MC Bank Error Configuration (R/W).
-
- @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
- /// to log additional info in bits 36:32.
- ///
- UINT32 MemErrorLogEnable:1;
- UINT32 Reserved2:30;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;
-
-
-/**
- Package.
-
- @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C
-
-/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
- /// counting logic for specific events requiring additional configuration,
- /// see Table 19-9.
- ///
- UINT32 ENABLE_PEBS_NUM_ALT:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_SANDY_BRIDGE_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_CTL, Msr);
- @endcode
- @{
-**/
-#define MSR_SANDY_BRIDGE_MC5_CTL 0x00000414
-#define MSR_SANDY_BRIDGE_MC6_CTL 0x00000418
-#define MSR_SANDY_BRIDGE_MC7_CTL 0x0000041C
-#define MSR_SANDY_BRIDGE_MC8_CTL 0x00000420
-#define MSR_SANDY_BRIDGE_MC9_CTL 0x00000424
-#define MSR_SANDY_BRIDGE_MC10_CTL 0x00000428
-#define MSR_SANDY_BRIDGE_MC11_CTL 0x0000042C
-#define MSR_SANDY_BRIDGE_MC12_CTL 0x00000430
-#define MSR_SANDY_BRIDGE_MC13_CTL 0x00000434
-#define MSR_SANDY_BRIDGE_MC14_CTL 0x00000438
-#define MSR_SANDY_BRIDGE_MC15_CTL 0x0000043C
-#define MSR_SANDY_BRIDGE_MC16_CTL 0x00000440
-#define MSR_SANDY_BRIDGE_MC17_CTL 0x00000444
-#define MSR_SANDY_BRIDGE_MC18_CTL 0x00000448
-#define MSR_SANDY_BRIDGE_MC19_CTL 0x0000044C
-/// @}
-
-
-/**
- Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.
-
- @param ECX MSR_SANDY_BRIDGE_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS, Msr);
- @endcode
- @{
-**/
-#define MSR_SANDY_BRIDGE_MC5_STATUS 0x00000415
-#define MSR_SANDY_BRIDGE_MC6_STATUS 0x00000419
-#define MSR_SANDY_BRIDGE_MC7_STATUS 0x0000041D
-#define MSR_SANDY_BRIDGE_MC8_STATUS 0x00000421
-#define MSR_SANDY_BRIDGE_MC9_STATUS 0x00000425
-#define MSR_SANDY_BRIDGE_MC10_STATUS 0x00000429
-#define MSR_SANDY_BRIDGE_MC11_STATUS 0x0000042D
-#define MSR_SANDY_BRIDGE_MC12_STATUS 0x00000431
-#define MSR_SANDY_BRIDGE_MC13_STATUS 0x00000435
-#define MSR_SANDY_BRIDGE_MC14_STATUS 0x00000439
-#define MSR_SANDY_BRIDGE_MC15_STATUS 0x0000043D
-#define MSR_SANDY_BRIDGE_MC16_STATUS 0x00000441
-#define MSR_SANDY_BRIDGE_MC17_STATUS 0x00000445
-#define MSR_SANDY_BRIDGE_MC18_STATUS 0x00000449
-#define MSR_SANDY_BRIDGE_MC19_STATUS 0x0000044D
-/// @}
-
-
-/**
- Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
-
- @param ECX MSR_SANDY_BRIDGE_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR, Msr);
- @endcode
- @{
-**/
-#define MSR_SANDY_BRIDGE_MC5_ADDR 0x00000416
-#define MSR_SANDY_BRIDGE_MC6_ADDR 0x0000041A
-#define MSR_SANDY_BRIDGE_MC7_ADDR 0x0000041E
-#define MSR_SANDY_BRIDGE_MC8_ADDR 0x00000422
-#define MSR_SANDY_BRIDGE_MC9_ADDR 0x00000426
-#define MSR_SANDY_BRIDGE_MC10_ADDR 0x0000042A
-#define MSR_SANDY_BRIDGE_MC11_ADDR 0x0000042E
-#define MSR_SANDY_BRIDGE_MC12_ADDR 0x00000432
-#define MSR_SANDY_BRIDGE_MC13_ADDR 0x00000436
-#define MSR_SANDY_BRIDGE_MC14_ADDR 0x0000043A
-#define MSR_SANDY_BRIDGE_MC15_ADDR 0x0000043E
-#define MSR_SANDY_BRIDGE_MC16_ADDR 0x00000442
-#define MSR_SANDY_BRIDGE_MC17_ADDR 0x00000446
-#define MSR_SANDY_BRIDGE_MC18_ADDR 0x0000044A
-#define MSR_SANDY_BRIDGE_MC19_ADDR 0x0000044E
-/// @}
-
-
-/**
- Package. See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_SANDY_BRIDGE_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_MISC);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_MISC, Msr);
- @endcode
- @{
-**/
-#define MSR_SANDY_BRIDGE_MC5_MISC 0x00000417
-#define MSR_SANDY_BRIDGE_MC6_MISC 0x0000041B
-#define MSR_SANDY_BRIDGE_MC7_MISC 0x0000041F
-#define MSR_SANDY_BRIDGE_MC8_MISC 0x00000423
-#define MSR_SANDY_BRIDGE_MC9_MISC 0x00000427
-#define MSR_SANDY_BRIDGE_MC10_MISC 0x0000042B
-#define MSR_SANDY_BRIDGE_MC11_MISC 0x0000042F
-#define MSR_SANDY_BRIDGE_MC12_MISC 0x00000433
-#define MSR_SANDY_BRIDGE_MC13_MISC 0x00000437
-#define MSR_SANDY_BRIDGE_MC14_MISC 0x0000043B
-#define MSR_SANDY_BRIDGE_MC15_MISC 0x0000043F
-#define MSR_SANDY_BRIDGE_MC16_MISC 0x00000443
-#define MSR_SANDY_BRIDGE_MC17_MISC 0x00000447
-#define MSR_SANDY_BRIDGE_MC18_MISC 0x0000044B
-#define MSR_SANDY_BRIDGE_MC19_MISC 0x0000044F
-/// @}
-
-
-/**
- Package. Package RAPL Perf Status (R/O).
-
- @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613
-
-
-/**
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
- Domain.".
-
- @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
-
-
-/**
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
-
-
-/**
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
- RAPL Domain.".
-
- @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
-
-
-/**
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C
-
-
-/**
- Package. Uncore U-box UCLK fixed counter control.
-
- @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08
-
-
-/**
- Package. Uncore U-box UCLK fixed counter.
-
- @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09
-
-
-/**
- Package. Uncore U-box perfmon event select for U-box counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10
-
-
-/**
- Package. Uncore U-box perfmon event select for U-box counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11
-
-
-/**
- Package. Uncore U-box perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16
-
-
-/**
- Package. Uncore U-box perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17
-
-
-/**
- Package. Uncore PCU perfmon for PCU-box-wide control.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24
-
-
-/**
- Package. Uncore PCU perfmon event select for PCU counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30
-
-
-/**
- Package. Uncore PCU perfmon event select for PCU counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31
-
-
-/**
- Package. Uncore PCU perfmon event select for PCU counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32
-
-
-/**
- Package. Uncore PCU perfmon event select for PCU counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33
-
-
-/**
- Package. Uncore PCU perfmon box-wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34
-
-
-/**
- Package. Uncore PCU perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36
-
-
-/**
- Package. Uncore PCU perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37
-
-
-/**
- Package. Uncore PCU perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38
-
-
-/**
- Package. Uncore PCU perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39
-
-
-/**
- Package. Uncore C-box 0 perfmon local box wide control.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04
-
-
-/**
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10
-
-
-/**
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11
-
-
-/**
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12
-
-
-/**
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13
-
-
-/**
- Package. Uncore C-box 0 perfmon box wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14
-
-
-/**
- Package. Uncore C-box 0 perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16
-
-
-/**
- Package. Uncore C-box 0 perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17
-
-
-/**
- Package. Uncore C-box 0 perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18
-
-
-/**
- Package. Uncore C-box 0 perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19
-
-
-/**
- Package. Uncore C-box 1 perfmon local box wide control.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24
-
-
-/**
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30
-
-
-/**
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31
-
-
-/**
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32
-
-
-/**
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33
-
-
-/**
- Package. Uncore C-box 1 perfmon box wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34
-
-
-/**
- Package. Uncore C-box 1 perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36
-
-
-/**
- Package. Uncore C-box 1 perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37
-
-
-/**
- Package. Uncore C-box 1 perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38
-
-
-/**
- Package. Uncore C-box 1 perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39
-
-
-/**
- Package. Uncore C-box 2 perfmon local box wide control.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44
-
-
-/**
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50
-
-
-/**
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51
-
-
-/**
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52
-
-
-/**
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53
-
-
-/**
- Package. Uncore C-box 2 perfmon box wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54
-
-
-/**
- Package. Uncore C-box 2 perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56
-
-
-/**
- Package. Uncore C-box 2 perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57
-
-
-/**
- Package. Uncore C-box 2 perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58
-
-
-/**
- Package. Uncore C-box 2 perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59
-
-
-/**
- Package. Uncore C-box 3 perfmon local box wide control.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64
-
-
-/**
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70
-
-
-/**
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71
-
-
-/**
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72
-
-
-/**
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73
-
-
-/**
- Package. Uncore C-box 3 perfmon box wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74
-
-
-/**
- Package. Uncore C-box 3 perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76
-
-
-/**
- Package. Uncore C-box 3 perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77
-
-
-/**
- Package. Uncore C-box 3 perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78
-
-
-/**
- Package. Uncore C-box 3 perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79
-
-
-/**
- Package. Uncore C-box 4 perfmon local box wide control.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84
-
-
-/**
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90
-
-
-/**
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91
-
-
-/**
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92
-
-
-/**
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93
-
-
-/**
- Package. Uncore C-box 4 perfmon box wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94
-
-
-/**
- Package. Uncore C-box 4 perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96
-
-
-/**
- Package. Uncore C-box 4 perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97
-
-
-/**
- Package. Uncore C-box 4 perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98
-
-
-/**
- Package. Uncore C-box 4 perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99
-
-
-/**
- Package. Uncore C-box 5 perfmon local box wide control.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4
-
-
-/**
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0
-
-
-/**
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1
-
-
-/**
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2
-
-
-/**
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3
-
-
-/**
- Package. Uncore C-box 5 perfmon box wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4
-
-
-/**
- Package. Uncore C-box 5 perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6
-
-
-/**
- Package. Uncore C-box 5 perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7
-
-
-/**
- Package. Uncore C-box 5 perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8
-
-
-/**
- Package. Uncore C-box 5 perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9
-
-
-/**
- Package. Uncore C-box 6 perfmon local box wide control.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4
-
-
-/**
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0
-
-
-/**
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1
-
-
-/**
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2
-
-
-/**
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3
-
-
-/**
- Package. Uncore C-box 6 perfmon box wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4
-
-
-/**
- Package. Uncore C-box 6 perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6
-
-
-/**
- Package. Uncore C-box 6 perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7
-
-
-/**
- Package. Uncore C-box 6 perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8
-
-
-/**
- Package. Uncore C-box 6 perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9
-
-
-/**
- Package. Uncore C-box 7 perfmon local box wide control.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4
-
-
-/**
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0
-
-
-/**
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1
-
-
-/**
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2
-
-
-/**
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3
-
-
-/**
- Package. Uncore C-box 7 perfmon box wide filter.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4
-
-
-/**
- Package. Uncore C-box 7 perfmon counter 0.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6
-
-
-/**
- Package. Uncore C-box 7 perfmon counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7
-
-
-/**
- Package. Uncore C-box 7 perfmon counter 2.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8
-
-
-/**
- Package. Uncore C-box 7 perfmon counter 3.
-
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
- @endcode
-**/
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h deleted file mode 100644 index 4272375ea5..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h +++ /dev/null @@ -1,1468 +0,0 @@ -/** @file
- MSR Definitions for Intel processors based on the Silvermont microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.
-
-**/
-
-#ifndef __SILVERMONT_MSR_H__
-#define __SILVERMONT_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Shared. Model Specific Platform ID (R).
-
- @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
- @endcode
-**/
-#define MSR_SILVERMONT_PLATFORM_ID 0x00000017
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
- ///
- UINT32 MaximumQualifiedRatio:5;
- UINT32 Reserved2:19;
- UINT32 Reserved3:18;
- ///
- /// [Bits 52:50] See Table 35-2.
- ///
- UINT32 PlatformId:3;
- UINT32 Reserved4:11;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_PLATFORM_ID_REGISTER;
-
-
-/**
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
- processor features; (R) indicates current processor configuration.
-
- @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
- AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 DataErrorCheckingEnable:1;
- ///
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 ResponseErrorCheckingEnable:1;
- ///
- /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
- ///
- UINT32 AERR_DriveEnable:1;
- ///
- /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
- /// Disabled Always 0.
- ///
- UINT32 BERR_Enable:1;
- UINT32 Reserved2:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
- ///
- UINT32 BINIT_DriverEnable:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 ExecuteBIST:1;
- ///
- /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 AERR_ObservationEnabled:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 BINIT_ObservationEnabled:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
- ///
- UINT32 ResetVector:1;
- UINT32 Reserved7:1;
- ///
- /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
- ///
- UINT32 APICClusterID:2;
- UINT32 Reserved8:2;
- ///
- /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
- ///
- UINT32 SymmetricArbitrationID:2;
- ///
- /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
- ///
- UINT32 IntegerBusFrequencyRatio:5;
- UINT32 Reserved9:5;
- UINT32 Reserved10:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;
-
-
-/**
- Core. SMI Counter (R/O).
-
- @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
- @endcode
-**/
-#define MSR_SILVERMONT_SMI_COUNT 0x00000034
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
- /// RESET.
- ///
- UINT32 SMICount:32;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_SMI_COUNT_REGISTER;
-
-
-/**
- Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the source instruction for one of the last eight
- branches, exceptions, or interrupts taken by the processor. See also: -
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
- Interrupt, and Exception Recording (Pentium M Processors).".
-
- @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
- AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040
-#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041
-#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042
-#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043
-#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044
-#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045
-#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046
-#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047
-/// @}
-
-
-/**
- Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction for one of the last eight
- branches, exceptions, or interrupts taken by the processor.
-
- @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
- AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060
-#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061
-#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062
-#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063
-#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064
-#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065
-#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066
-#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067
-/// @}
-
-
-/**
- Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
- bus clock speed for processors based on Silvermont microarchitecture:.
-
- @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
- @endcode
-**/
-#define MSR_SILVERMONT_FSB_FREQ 0x000000CD
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Scalable Bus Speed
- ///
- /// Silvermont Processor Family
- /// ---------------------------
- /// 100B: 080.0 MHz
- /// 000B: 083.3 MHz
- /// 001B: 100.0 MHz
- /// 010B: 133.3 MHz
- /// 011B: 116.7 MHz
- ///
- /// Airmont Processor Family
- /// ---------------------------
- /// 0000B: 083.3 MHz
- /// 0001B: 100.0 MHz
- /// 0010B: 133.3 MHz
- /// 0011B: 116.7 MHz
- /// 0100B: 080.0 MHz
- /// 0101B: 093.3 MHz
- /// 0110B: 090.0 MHz
- /// 0111B: 088.9 MHz
- /// 1000B: 087.5 MHz
- ///
- UINT32 ScalableBusSpeed:4;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_FSB_FREQ_REGISTER;
-
-
-/**
- Shared. C-State Configuration Control (R/W) Note: C-state values are
- processor specific C-state code names, unrelated to MWAIT extension C-state
- parameters or ACPI CStates. See http://biosbits.org.
-
- @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
- /// processor-specific C-state code name (consuming the least power). for
- /// the package. The default is set as factory-configured package C-state
- /// limit. The following C-state code name encodings are supported: 000b:
- /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
- /// 100b: C4 110b: C6 111b: C7 (Silvermont only).
- ///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
- /// IO_read instructions sent to IO register specified by
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
- /// until next reset.
- ///
- UINT32 CFGLock:1;
- UINT32 Reserved3:16;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- Shared. Power Management IO Redirection in C-state (R/W) See
- http://biosbits.org.
-
- @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
- AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
- /// visible to software for IO redirection. If IO MWAIT Redirection is
- /// enabled, reads to this address will be consumed by the power
- /// management logic and decoded to MWAIT instructions. When IO port
- /// address redirection is enabled, this is the IO port address reported
- /// to the OS/software.
- ///
- UINT32 Lvl2Base:16;
- ///
- /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
- /// maximum C-State code name to be included when IO read to MWAIT
- /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
- /// is the max C-State to include 110b - C6 is the max C-State to include
- /// 111b - C7 is the max C-State to include.
- ///
- UINT32 CStateRange:3;
- UINT32 Reserved1:13;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;
-
-
-/**
- Shared.
-
- @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
- AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
- /// Indicates if the L2 is hardware-disabled.
- ///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:7;
- ///
- /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
- /// Disabled (default) Until this bit is set the processor will not
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
- ///
- UINT32 L2Enabled:1;
- UINT32 Reserved2:14;
- ///
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
- ///
- UINT32 L2NotPresent:1;
- UINT32 Reserved3:8;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;
-
-
-/**
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
- handler to handle unsuccessful read of this MSR.
-
- @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
- AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
- /// MSR, the configuration of AES instruction set availability is as
- /// follows: 11b: AES instructions are not available until next RESET.
- /// otherwise, AES instructions are available. Note, AES instruction set
- /// is not available if read is unsuccessful. If the configuration is not
- /// 01b, AES instruction can be mis-configured if a privileged agent
- /// unintentionally writes 11b.
- ///
- UINT32 AESConfiguration:2;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;
-
-
-/**
- Enable Misc. Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] Shared. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
- ///
- /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Core. Precise Event Based Sampling Unavailable (RO) See Table
- /// 35-2.
- ///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
- ///
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
- ///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
- ///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
- ///
- /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
- ///
- /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
- ///
- UINT32 XD:1;
- UINT32 Reserved9:3;
- ///
- /// [Bit 38] Shared. Turbo Mode Disable (R/W) When set to 1 on processors
- /// that support Intel Turbo Boost Technology, the turbo mode feature is
- /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
- /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
- /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
- /// the power-on default value is used by BIOS to detect hardware support
- /// of turbo mode. If power-on default value is 1, turbo mode is available
- /// in the processor. If power-on default value is 0, turbo mode is not
- /// available.
- ///
- UINT32 TurboModeDisable:1;
- UINT32 Reserved10:25;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Package.
-
- @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
- AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bits 23:16] Temperature Target (R) The default thermal throttling or
- /// PROCHOT# activation temperature in degree C, The effective temperature
- /// for thermal throttling or PROCHOT# activation is "Temperature Target"
- /// + "Target Offset".
- ///
- UINT32 TemperatureTarget:8;
- ///
- /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to
- /// adjust the throttling and PROCHOT# activation temperature from the
- /// default target specified in TEMPERATURE_TARGET (bits 23:16).
- ///
- UINT32 TargetOffset:6;
- UINT32 Reserved2:2;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;
-
-
-/**
- Shared. Offcore Response Event Select Register (R/W).
-
- @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
- AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6
-
-
-/**
- Shared. Offcore Response Event Select Register (R/W).
-
- @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
- AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode (RW).
-
- @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
- AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
- /// limit of 1 core active.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
- /// limit of 2 core active.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
- /// limit of 3 core active.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
- /// limit of 4 core active.
- ///
- UINT32 Maximum4C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
- /// limit of 5 core active.
- ///
- UINT32 Maximum5C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
- /// limit of 6 core active.
- ///
- UINT32 Maximum6C:8;
- ///
- /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
- /// limit of 7 core active.
- ///
- UINT32 Maximum7C:8;
- ///
- /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
- /// limit of 8 core active.
- ///
- UINT32 Maximum8C:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that
- points to the MSR containing the most recent branch record. See
- MSR_LASTBRANCH_0_FROM_IP (at 40H).
-
- @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Core. Last Exception Record From Linear IP (R) Contains a pointer to the
- last branch instruction that the processor executed prior to the last
- exception that was generated or the last interrupt that was handled.
-
- @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD
-
-
-/**
- Core. Last Exception Record To Linear IP (R) This area contains a pointer
- to the target of the last branch instruction that the processor executed
- prior to the last exception that was generated or the last interrupt that
- was handled.
-
- @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
- @endcode
-**/
-#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE
-
-
-/**
- Core. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Core. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
- (PEBS).".
-
- @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
- ///
- UINT32 PEBS:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
- Residency Counter. (R/O) Value since last reset that this package is in
- processor-specific C6 states. Counts at the TSC Frequency.
-
- @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA
-
-
-/**
- Core. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
- Residency Counter. (R/O) Value since last reset that this core is in
- processor-specific C6 states. Counts at the TSC Frequency.
-
- @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD
-
-
-/**
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_SILVERMONT_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);
- @endcode
- @{
-**/
-#define MSR_SILVERMONT_MC3_CTL 0x0000040C
-#define MSR_SILVERMONT_MC4_CTL 0x00000410
-#define MSR_SILVERMONT_MC5_CTL 0x00000414
-/// @}
-
-
-/**
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_SILVERMONT_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);
- @endcode
- @{
-**/
-#define MSR_SILVERMONT_MC3_STATUS 0x0000040D
-#define MSR_SILVERMONT_MC4_STATUS 0x00000411
-#define MSR_SILVERMONT_MC5_STATUS 0x00000415
-/// @}
-
-
-/**
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MCi_ADDR register
- is either not implemented or contains no address if the ADDRV flag in the
- MSR_MCi_STATUS register is clear. When not implemented in the processor, all
- reads and writes to this MSR will cause a general-protection exception.
-
- @param ECX MSR_SILVERMONT_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);
- @endcode
- @{
-**/
-#define MSR_SILVERMONT_MC3_ADDR 0x0000040E
-#define MSR_SILVERMONT_MC4_ADDR 0x00000412
-#define MSR_SILVERMONT_MC5_ADDR 0x00000416
-/// @}
-
-
-/**
- Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
-
- @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
- @endcode
-**/
-#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C
-
-
-/**
- Core. Capability Reporting Register of VM-function Controls (R/O) See Table
- 35-2.
-
- @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
- @endcode
-**/
-#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491
-
-
-/**
- Core. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1
- Residency Counter. (R/O) Value since last reset that this core is in
- processor-specific C1 states. Counts at the TSC frequency.
-
- @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
- AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660
-
-
-/**
- Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
- "RAPL Interfaces.".
-
- @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
- @endcode
-**/
-#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Power Units. Power related information (in milliWatts) is
- /// based on the multiplier, 2^PU; where PU is an unsigned integer
- /// represented by bits 3:0. Default value is 0101b, indicating power unit
- /// is in 32 milliWatts increment.
- ///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
- ///
- /// [Bits 12:8] Energy Status Units. Energy related information (in
- /// microJoules) is based on the multiplier, 2^ESU; where ESU is an
- /// unsigned integer represented by bits 12:8. Default value is 00101b,
- /// indicating energy unit is in 32 microJoules increment.
- ///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
- ///
- /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in
- /// one second.
- ///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;
-
-
-/**
- Package. PKG RAPL Power Limit Control (R/W).
-
- @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
- AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package
- /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-7.
- ///
- UINT32 Limit:15;
- ///
- /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package
- /// RAPL Domain.".
- ///
- UINT32 Enable:1;
- ///
- /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,
- /// "Package RAPL Domain.".
- ///
- UINT32 ClampingLimit:1;
- ///
- /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.
- /// If 0 is specified in bits [23:17], defaults to 1 second window.
- ///
- UINT32 Time:7;
- UINT32 Reserved1:8;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;
-
-
-/**
- Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
- and MSR_RAPL_POWER_UNIT in Table 35-7.
-
- @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611
-
-
-/**
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
- Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.
-
- @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639
-
-
-/**
- Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion
- policy. Writing a value of 0 disables core level HW demotion policy.
-
- @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
- AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
-
-
-/**
- Package. Module C6 demotion policy config MSR. Controls module (i.e. two
- cores sharing the second-level cache) C6 demotion policy. Writing a value of
- 0 disables module level HW demotion policy.
-
- @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
- AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
- @endcode
-**/
-#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
-
-
-/**
- Module. Module C6 Residency Counter (R/0) Note: C-state values are processor
- specific C-state code names, unrelated to MWAIT extension C-state parameters
- or ACPI CStates. Time that this module is in module-specific C6 states since
- last reset. Counts at 1 Mhz frequency.
-
- @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
- @endcode
-**/
-#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664
-
-
-/**
- Package. PKG RAPL Parameter (R/0).
-
- @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
- @endcode
-**/
-#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is
- /// the equivalent of thermal specification power of the package domain.
- /// The unit of this field is specified by the "Power Units" field of
- /// MSR_RAPL_POWER_UNIT.
- ///
- UINT32 ThermalSpecPower:15;
- UINT32 Reserved1:17;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;
-
-
-/**
- Package. PP0 RAPL Power Limit Control (R/W).
-
- @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
- AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
- @endcode
-**/
-#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638
-
-/**
- MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
- /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.
- ///
- UINT32 Limit:15;
- ///
- /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
- /// RAPL Domains.".
- ///
- UINT32 Enable:1;
- UINT32 Reserved1:1;
- ///
- /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time
- /// duration over which the average power must remain below
- /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time
- /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time
- /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.
- /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35
- /// second time duration. 0x8: 40 second time duration. 0x9: 45 second
- /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.
- ///
- UINT32 Time:7;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h deleted file mode 100644 index 34868f9a27..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h +++ /dev/null @@ -1,1008 +0,0 @@ -/** @file
- MSR Definitions for Intel processors based on the Skylake microarchitecture.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14.
-
-**/
-
-#ifndef __SKYLAKE_MSR_H__
-#define __SKYLAKE_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
- @endcode
-**/
-#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
- /// limit of 1 core active.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
- /// limit of 2 core active.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
- /// limit of 3 core active.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
- /// limit of 4 core active.
- ///
- UINT32 Maximum4C:8;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)
- that points to the MSR containing the most recent branch record.
-
- @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
- an 128-bit external entropy value for key derivation of an enclave.
-
- @param ECX MSR_SKYLAKE_SGXOWNER0 (0x00000300)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
- @endcode
-**/
-#define MSR_SKYLAKE_SGXOWNER0 0x00000300
-
-
-/**
- Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
- an 128-bit external entropy value for key derivation of an enclave.
-
- @param ECX MSR_SKYLAKE_SGXOWNER1 (0x00000301)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
- @endcode
-**/
-#define MSR_SKYLAKE_SGXOWNER1 0x00000301
-
-
-/**
- See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
- Counter Registers.".
-
- @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
- @endcode
-**/
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-/**
- MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thread. Ovf_PMC0.
- ///
- UINT32 Ovf_PMC0:1;
- ///
- /// [Bit 1] Thread. Ovf_PMC1.
- ///
- UINT32 Ovf_PMC1:1;
- ///
- /// [Bit 2] Thread. Ovf_PMC2.
- ///
- UINT32 Ovf_PMC2:1;
- ///
- /// [Bit 3] Thread. Ovf_PMC3.
- ///
- UINT32 Ovf_PMC3:1;
- ///
- /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
- ///
- UINT32 Ovf_PMC4:1;
- ///
- /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
- ///
- UINT32 Ovf_PMC5:1;
- ///
- /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
- ///
- UINT32 Ovf_PMC6:1;
- ///
- /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
- ///
- UINT32 Ovf_PMC7:1;
- UINT32 Reserved1:24;
- ///
- /// [Bit 32] Thread. Ovf_FixedCtr0.
- ///
- UINT32 Ovf_FixedCtr0:1;
- ///
- /// [Bit 33] Thread. Ovf_FixedCtr1.
- ///
- UINT32 Ovf_FixedCtr1:1;
- ///
- /// [Bit 34] Thread. Ovf_FixedCtr2.
- ///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:20;
- ///
- /// [Bit 55] Thread. Trace_ToPA_PMI.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 58] Thread. LBR_Frz.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] Thread. CTR_Frz.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] Thread. ASCI.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Thread. Ovf_Uncore.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Thread. Ovf_BufDSSAVE.
- ///
- UINT32 Ovf_BufDSSAVE:1;
- ///
- /// [Bit 63] Thread. CondChgd.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER;
-
-
-/**
- See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
- Counter Registers.".
-
- @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
- @endcode
-**/
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
-
-/**
- MSR information returned for MSR index
- #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
- ///
- UINT32 Ovf_PMC0:1;
- ///
- /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
- ///
- UINT32 Ovf_PMC1:1;
- ///
- /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
- ///
- UINT32 Ovf_PMC2:1;
- ///
- /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
- ///
- UINT32 Ovf_PMC3:1;
- ///
- /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
- ///
- UINT32 Ovf_PMC4:1;
- ///
- /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
- ///
- UINT32 Ovf_PMC5:1;
- ///
- /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
- ///
- UINT32 Ovf_PMC6:1;
- ///
- /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
- ///
- UINT32 Ovf_PMC7:1;
- UINT32 Reserved1:24;
- ///
- /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
- ///
- UINT32 Ovf_FixedCtr0:1;
- ///
- /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
- ///
- UINT32 Ovf_FixedCtr1:1;
- ///
- /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
- ///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:20;
- ///
- /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 58] Thread. Set 1 to clear LBR_Frz.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] Thread. Set 1 to clear CTR_Frz.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] Thread. Set 1 to clear ASCI.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
- ///
- UINT32 Ovf_BufDSSAVE:1;
- ///
- /// [Bit 63] Thread. Set 1 to clear CondChgd.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
-
-
-/**
- See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
- Counter Registers.".
-
- @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
- @endcode
-**/
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
-
-/**
- MSR information returned for MSR index
- #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.
- ///
- UINT32 Ovf_PMC0:1;
- ///
- /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.
- ///
- UINT32 Ovf_PMC1:1;
- ///
- /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.
- ///
- UINT32 Ovf_PMC2:1;
- ///
- /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.
- ///
- UINT32 Ovf_PMC3:1;
- ///
- /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).
- ///
- UINT32 Ovf_PMC4:1;
- ///
- /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).
- ///
- UINT32 Ovf_PMC5:1;
- ///
- /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).
- ///
- UINT32 Ovf_PMC6:1;
- ///
- /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).
- ///
- UINT32 Ovf_PMC7:1;
- UINT32 Reserved1:24;
- ///
- /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.
- ///
- UINT32 Ovf_FixedCtr0:1;
- ///
- /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.
- ///
- UINT32 Ovf_FixedCtr1:1;
- ///
- /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.
- ///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:20;
- ///
- /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] Thread. Set 1 to cause ASCI = 1.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.
- ///
- UINT32 Ovf_BufDSSAVE:1;
- UINT32 Reserved4:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
-
-
-/**
- Thread. FrontEnd Precise Event Condition Select (R/W).
-
- @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
- AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
- @endcode
-**/
-#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7
-
-/**
- MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Event Code Select.
- ///
- UINT32 EventCodeSelect:3;
- UINT32 Reserved1:1;
- ///
- /// [Bit 4] Event Code Select High.
- ///
- UINT32 EventCodeSelectHigh:1;
- UINT32 Reserved2:3;
- ///
- /// [Bits 19:8] IDQ_Bubble_Length Specifier.
- ///
- UINT32 IDQ_Bubble_Length:12;
- ///
- /// [Bits 22:20] IDQ_Bubble_Width Specifier.
- ///
- UINT32 IDQ_Bubble_Width:3;
- UINT32 Reserved3:9;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;
-
-
-/**
- Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both
- platform vendor hardware implementation and BIOS enablement support it. This
- MSR will read 0 if not valid.
-
- @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
- @endcode
-**/
-#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D
-
-/**
- MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Total energy consumed by all devices in the platform that
- /// receive power from integrated power delivery mechanism, Included
- /// platform devices are processor cores, SOC, memory, add-on or
- /// peripheral devices that get powered directly from the platform power
- /// delivery means. The energy units are specified in the
- /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
- ///
- UINT32 TotalEnergy:32;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;
-
-
-/**
- Thread. Productive Performance Count. (R/O). Hardware's view of workload
- scalability. See Section 14.4.5.1.
-
- @param ECX MSR_SKYLAKE_PPERF (0x0000064E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
- @endcode
-**/
-#define MSR_SKYLAKE_PPERF 0x0000064E
-
-
-/**
- Package. HDC Configuration (R/W)..
-
- @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
- AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
- @endcode
-**/
-#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652
-
-/**
- MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for
- /// MSR_PKG_HDC_DEEP_RESIDENCY.
- ///
- UINT32 PKG_Cx_Monitor:3;
- UINT32 Reserved1:29;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;
-
-
-/**
- Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.
-
- @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
- @endcode
-**/
-#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653
-
-
-/**
- Package. Accumulate the cycles the package was in C2 state and at least one
- logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.
-
- @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
- @endcode
-**/
-#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655
-
-
-/**
- Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.
-
- @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
- @endcode
-**/
-#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656
-
-
-/**
- Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate
- as the TSC. The increment each cycle is weighted by the number of processor
- cores in the package that reside in C0. If N cores are simultaneously in C0,
- then each cycle the counter increments by N.
-
- @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
- @endcode
-**/
-#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658
-
-
-/**
- Package. Any Core C0 Residency. (R/O). Increment at the same rate as the
- TSC. The increment each cycle is one if any processor core in the package is
- in C0.
-
- @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
- @endcode
-**/
-#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659
-
-
-/**
- Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate
- as the TSC. The increment each cycle is one if any processor graphic
- device's compute engines are in C0.
-
- @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
- @endcode
-**/
-#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A
-
-
-/**
- Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment
- at the same rate as the TSC. The increment each cycle is one if at least one
- compute engine of the processor graphics is in C0 and at least one processor
- core in the package is also in C0.
-
- @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
- @endcode
-**/
-#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B
-
-
-/**
- Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to
- limit power consumption of the platform devices to the specified values. The
- Long Duration power consumption is specified via Platform_Power_Limit_1 and
- Platform_Power_Limit_1_Time. The Short Duration power consumption limit is
- specified via the Platform_Power_Limit_2 with duration chosen by the
- processor. The processor implements an exponential-weighted algorithm in the
- placement of the time windows.
-
- @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
- AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
- @endcode
-**/
-#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C
-
-/**
- MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which
- /// the platform must not exceed over a time window as specified by
- /// Power_Limit_1_TIME field. The default value is the Thermal Design
- /// Power (TDP) and varies with product skus. The unit is specified in
- /// MSR_RAPLPOWER_UNIT.
- ///
- UINT32 PlatformPowerLimit1:15;
- ///
- /// [Bit 15] Enable Platform Power Limit #1. When set, enables the
- /// processor to apply control policy such that the platform power does
- /// not exceed Platform Power limit #1 over the time window specified by
- /// Power Limit #1 Time Window.
- ///
- UINT32 EnablePlatformPowerLimit1:1;
- ///
- /// [Bit 16] Platform Clamping Limitation #1. When set, allows the
- /// processor to go below the OS requested P states in order to maintain
- /// the power below specified Platform Power Limit #1 value. This bit is
- /// writeable only when CPUID (EAX=6):EAX[4] is set.
- ///
- UINT32 PlatformClampingLimitation1:1;
- ///
- /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the
- /// duration of the time window over which Platform Power Limit 1 value
- /// should be maintained for sustained long duration. This field is made
- /// up of two numbers from the following equation: Time Window = (float)
- /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =
- /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is
- /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,
- /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].
- ///
- UINT32 Time:7;
- UINT32 Reserved1:8;
- ///
- /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which
- /// the platform must not exceed over the Short Duration time window
- /// chosen by the processor. The recommended default value is 1.25 times
- /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).
- ///
- UINT32 PlatformPowerLimit2:15;
- ///
- /// [Bit 47] Enable Platform Power Limit #2. When set, enables the
- /// processor to apply control policy such that the platform power does
- /// not exceed Platform Power limit #2 over the Short Duration time window.
- ///
- UINT32 EnablePlatformPowerLimit2:1;
- ///
- /// [Bit 48] Platform Clamping Limitation #2. When set, allows the
- /// processor to go below the OS requested P states in order to maintain
- /// the power below specified Platform Power Limit #2 value.
- ///
- UINT32 PlatformClampingLimitation2:1;
- UINT32 Reserved2:14;
- ///
- /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR
- /// until system RESET.
- ///
- UINT32 Lock:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;
-
-
-/**
- Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last
- branch record registers on the last branch record stack. This part of the
- stack contains pointers to the source instruction. See also: - Last Branch
- Record Stack TOS at 1C9H - Section 17.9.
-
- @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
- AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690
-#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691
-#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692
-#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693
-#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694
-#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695
-#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696
-#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697
-#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698
-#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699
-#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A
-#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B
-#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C
-#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D
-#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E
-#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F
-/// @}
-
-/**
- Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction. See also: - Last Branch
- Record Stack TOS at 1C9H - Section 17.9.
-
- @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
- AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
- @endcode
- @{
-**/
-#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0
-#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1
-#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2
-#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3
-#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4
-#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5
-#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6
-#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7
-#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8
-#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9
-#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA
-#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB
-#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC
-#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD
-#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE
-#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF
-/// @}
-
-
-/**
- Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet
- of last branch record registers on the last branch record stack. This part
- of the stack contains flag, TSX-related and elapsed cycle information. See
- also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR
- Stack.".
-
- @param ECX MSR_SKYLAKE_LBR_INFO_n
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
- AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
- @endcode
- @{
-**/
-#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0
-#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1
-#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2
-#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3
-#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4
-#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5
-#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6
-#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7
-#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8
-#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9
-#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA
-#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB
-#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC
-#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD
-#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE
-#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF
-#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0
-#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1
-#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2
-#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3
-#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4
-#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5
-#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6
-#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7
-#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8
-#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9
-#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA
-#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB
-#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC
-#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD
-#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE
-#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF
-/// @}
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h deleted file mode 100644 index a4c6ba0845..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h +++ /dev/null @@ -1,182 +0,0 @@ -/** @file
- MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.
-
-**/
-
-#ifndef __XEON_5600_MSR_H__
-#define __XEON_5600_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
- handler to handle unsuccessful read of this MSR.
-
- @param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
- AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
-
-/**
- MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
- /// MSR, the configuration of AES instruction set availability is as
- /// follows: 11b: AES instructions are not available until next RESET.
- /// otherwise, AES instructions are available. Note, AES instruction set
- /// is not available if read is unsuccessful. If the configuration is not
- /// 01b, AES instruction can be mis-configured if a privileged agent
- /// unintentionally writes 11b.
- ///
- UINT32 AESConfiguration:2;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
-
-
-/**
- Thread. Offcore Response Event Select Register (R/W).
-
- @param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
- AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
- @endcode
-**/
-#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
- @endcode
-**/
-#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
- /// limit of 1 core active.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
- /// limit of 2 core active.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
- /// limit of 3 core active.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
- /// limit of 4 core active.
- ///
- UINT32 Maximum4C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
- /// limit of 5 core active.
- ///
- UINT32 Maximum5C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
- /// limit of 6 core active.
- ///
- UINT32 Maximum6C:8;
- UINT32 Reserved:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Package. See Table 35-2.
-
- @param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
- AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
- @endcode
-**/
-#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h deleted file mode 100644 index 43a35f2a8e..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h +++ /dev/null @@ -1,1430 +0,0 @@ -/** @file
- MSR Definitions for Intel(R) Xeon(R) Processor D product Family.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.
-
-**/
-
-#ifndef __XEON_D_MSR_H__
-#define __XEON_D_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Package. Protected Processor Inventory Number Enable Control (R/W).
-
- @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PPIN_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
- AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_PPIN_CTL 0x0000004E
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] LockOut (R/WO) See Table 35-21.
- ///
- UINT32 LockOut:1;
- ///
- /// [Bit 1] Enable_PPIN (R/W) See Table 35-21.
- ///
- UINT32 Enable_PPIN:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PPIN_CTL_REGISTER;
-
-
-/**
- Package. Protected Processor Inventory Number (R/O). Protected Processor
- Inventory Number (R/O) See Table 35-21.
-
- @param ECX MSR_XEON_D_PPIN (0x0000004F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
- @endcode
-**/
-#define MSR_XEON_D_PPIN 0x0000004F
-
-
-/**
- Package. See http://biosbits.org.
-
- @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
- AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_PLATFORM_INFO 0x000000CE
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.
- ///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:7;
- ///
- /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.
- ///
- UINT32 PPIN_CAP:1;
- UINT32 Reserved3:4;
- ///
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
- /// Table 35-21.
- ///
- UINT32 RatioLimit:1;
- ///
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
- /// Table 35-21.
- ///
- UINT32 TDPLimit:1;
- ///
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.
- ///
- UINT32 TJOFFSET:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:8;
- ///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-21.
- ///
- UINT32 MaximumEfficiencyRatio:8;
- UINT32 Reserved6:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PLATFORM_INFO_REGISTER;
-
-
-/**
- Core. C-State Configuration Control (R/W) Note: C-state values are processor
- specific C-state code names, unrelated to MWAIT extension C-state parameters
- or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
-
- @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
- /// processor-specific C-state code name (consuming the least power) for
- /// the package. The default is set as factory-configured package C-state
- /// limit. The following C-state code name encodings are supported: 000b:
- /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
- /// 011b: C6 (retention) 111b: No Package C state limits. All C states
- /// supported by the processor are available.
- ///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO).
- ///
- UINT32 CFGLock:1;
- ///
- /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
- /// will convert HALT or MWAT(C1) to MWAIT(C6).
- ///
- UINT32 CStateConversion:1;
- UINT32 Reserved3:8;
- ///
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).
- ///
- UINT32 C3AutoDemotion:1;
- ///
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).
- ///
- UINT32 C1AutoDemotion:1;
- ///
- /// [Bit 27] Enable C3 Undemotion (R/W).
- ///
- UINT32 C3Undemotion:1;
- ///
- /// [Bit 28] Enable C1 Undemotion (R/W).
- ///
- UINT32 C1Undemotion:1;
- ///
- /// [Bit 29] Package C State Demotion Enable (R/W).
- ///
- UINT32 CStateDemotion:1;
- ///
- /// [Bit 30] Package C State UnDemotion Enable (R/W).
- ///
- UINT32 CStateUndemotion:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- Thread. Global Machine Check Capability (R/O).
-
- @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);
- @endcode
-**/
-#define MSR_XEON_D_IA32_MCG_CAP 0x00000179
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Count.
- ///
- UINT32 Count:8;
- ///
- /// [Bit 8] MCG_CTL_P.
- ///
- UINT32 MCG_CTL_P:1;
- ///
- /// [Bit 9] MCG_EXT_P.
- ///
- UINT32 MCG_EXT_P:1;
- ///
- /// [Bit 10] MCP_CMCI_P.
- ///
- UINT32 MCP_CMCI_P:1;
- ///
- /// [Bit 11] MCG_TES_P.
- ///
- UINT32 MCG_TES_P:1;
- UINT32 Reserved1:4;
- ///
- /// [Bits 23:16] MCG_EXT_CNT.
- ///
- UINT32 MCG_EXT_CNT:8;
- ///
- /// [Bit 24] MCG_SER_P.
- ///
- UINT32 MCG_SER_P:1;
- ///
- /// [Bit 25] MCG_EM_P.
- ///
- UINT32 MCG_EM_P:1;
- ///
- /// [Bit 26] MCG_ELOG_P.
- ///
- UINT32 MCG_ELOG_P:1;
- UINT32 Reserved2:5;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_IA32_MCG_CAP_REGISTER;
-
-
-/**
- THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
- Enhancement. Accessible only while in SMM.
-
- @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);
- AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:26;
- ///
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
- /// SMM code access restriction is supported and a host-space interface
- /// available to SMM handler.
- ///
- UINT32 SMM_Code_Access_Chk:1;
- ///
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
- /// SMM long flow indicator is supported and a host-space interface
- /// available to SMM handler.
- ///
- UINT32 Long_Flow_Indication:1;
- UINT32 Reserved3:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_SMM_MCA_CAP_REGISTER;
-
-
-/**
- Package.
-
- @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);
- AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bits 23:16] Temperature Target (RO) See Table 35-21.
- ///
- UINT32 TemperatureTarget:8;
- ///
- /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-21.
- ///
- UINT32 TCCActivationOffset:4;
- UINT32 Reserved2:4;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);
- @endcode
-**/
-#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.
- ///
- UINT32 Maximum1C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.
- ///
- UINT32 Maximum2C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.
- ///
- UINT32 Maximum3C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.
- ///
- UINT32 Maximum4C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.
- ///
- UINT32 Maximum5C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.
- ///
- UINT32 Maximum6C:8;
- ///
- /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.
- ///
- UINT32 Maximum7C:8;
- ///
- /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.
- ///
- UINT32 Maximum8C:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);
- @endcode
-**/
-#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.
- ///
- UINT32 Maximum9C:8;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.
- ///
- UINT32 Maximum10C:8;
- ///
- /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.
- ///
- UINT32 Maximum11C:8;
- ///
- /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.
- ///
- UINT32 Maximum12C:8;
- ///
- /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.
- ///
- UINT32 Maximum13C:8;
- ///
- /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.
- ///
- UINT32 Maximum14C:8;
- ///
- /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.
- ///
- UINT32 Maximum15C:8;
- ///
- /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.
- ///
- UINT32 Maximum16C:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;
-
-
-/**
- Package. Unit Multipliers used in RAPL Interfaces (R/O).
-
- @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);
- @endcode
-**/
-#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
- ///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
- ///
- /// [Bits 12:8] Package. Energy Status Units Energy related information
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
- /// micro-joules).
- ///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
- ///
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
- /// Interfaces.".
- ///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;
-
-
-/**
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
- Domain.".
-
- @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);
- AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618
-
-
-/**
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619
-
-
-/**
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
- RAPL Domain.".
-
- @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);
- @endcode
-**/
-#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B
-
-
-/**
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);
- AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);
- @endcode
-**/
-#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C
-
-
-/**
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
- refers to processor core frequency).
-
- @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);
- AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
- /// reduced below the operating system request due to assertion of
- /// external PROCHOT.
- ///
- UINT32 PROCHOT_Status:1;
- ///
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
- /// operating system request due to a thermal event.
- ///
- UINT32 ThermalStatus:1;
- ///
- /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
- /// reduced below the operating system request due to PBM limit.
- ///
- UINT32 PowerBudgetManagementStatus:1;
- ///
- /// [Bit 3] Platform Configuration Services Status (R0) When set,
- /// frequency is reduced below the operating system request due to PCS
- /// limit.
- ///
- UINT32 PlatformConfigurationServicesStatus:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
- /// When set, frequency is reduced below the operating system request
- /// because the processor has detected that utilization is low.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;
- ///
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
- /// below the operating system request due to a thermal alert from the
- /// Voltage Regulator.
- ///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
- /// reduced below the operating system request due to electrical design
- /// point constraints (e.g. maximum electrical current consumption).
- ///
- UINT32 ElectricalDesignPointStatus:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
- /// below the operating system request due to Multi-Core Turbo limits.
- ///
- UINT32 MultiCoreTurboStatus:1;
- UINT32 Reserved4:2;
- ///
- /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
- /// below max non-turbo P1.
- ///
- UINT32 FrequencyP1Status:1;
- ///
- /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
- /// set, frequency is reduced below max n-core turbo frequency.
- ///
- UINT32 TurboFrequencyLimitingStatus:1;
- ///
- /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
- /// reduced below the operating system request.
- ///
- UINT32 FrequencyLimitingStatus:1;
- ///
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 PROCHOT_Log:1;
- ///
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 ThermalLog:1;
- ///
- /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 PowerBudgetManagementLog:1;
- ///
- /// [Bit 19] Platform Configuration Services Log When set, indicates that
- /// the PCS Status bit has asserted since the log bit was last cleared.
- /// This log bit will remain set until cleared by software writing 0.
- ///
- UINT32 PlatformConfigurationServicesLog:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
- /// indicates that the AUBFC Status bit has asserted since the log bit was
- /// last cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;
- ///
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
- /// Alert Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 VRThermAlertLog:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
- /// Status bit has asserted since the log bit was last cleared. This log
- /// bit will remain set until cleared by software writing 0.
- ///
- UINT32 ElectricalDesignPointLog:1;
- UINT32 Reserved7:1;
- ///
- /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
- /// Turbo Status bit has asserted since the log bit was last cleared. This
- /// log bit will remain set until cleared by software writing 0.
- ///
- UINT32 MultiCoreTurboLog:1;
- UINT32 Reserved8:2;
- ///
- /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
- /// Frequency P1 Status bit has asserted since the log bit was last
- /// cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 CoreFrequencyP1Log:1;
- ///
- /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
- /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
- /// has asserted since the log bit was last cleared. This log bit will
- /// remain set until cleared by software writing 0.
- ///
- UINT32 TurboFrequencyLimitingLog:1;
- ///
- /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
- /// Frequency Limiting Status bit has asserted since the log bit was last
- /// cleared. This log bit will remain set until cleared by software
- /// writing 0.
- ///
- UINT32 CoreFrequencyLimitingLog:1;
- UINT32 Reserved9:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;
-
-
-/**
- THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,
- ECX=0):EBX.PQM[bit 12] = 1.
-
- @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);
- AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3
- /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:
- /// Local memory bandwidth monitoring All other encoding reserved.
- ///
- UINT32 EventID:8;
- UINT32 Reserved1:24;
- ///
- /// [Bits 41:32] RMID (RW).
- ///
- UINT32 RMID:10;
- UINT32 Reserved2:22;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;
-
-
-/**
- THREAD. Resource Association Register (R/W).
-
- @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);
- AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 9:0] RMID.
- ///
- UINT32 RMID:10;
- UINT32 Reserved1:22;
- ///
- /// [Bits 51:32] COS (R/W).
- ///
- UINT32 COS:20;
- UINT32 Reserved2:12;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;
-
-
-/**
- Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
- ECX=1):EDX.COS_MAX[15:0] >= n.
-
- @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
- AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
- @endcode
- @{
-**/
-#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90
-#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91
-#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92
-#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93
-#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94
-#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95
-#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96
-#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97
-#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98
-#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99
-#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A
-#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B
-#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C
-#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D
-#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E
-#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0
- to #MSR_XEON_D_IA32_L3_QOS_MASK_15.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.
- ///
- UINT32 CBM:20;
- UINT32 Reserved2:12;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;
-
-
-/**
- Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
- RW if MSR_PLATFORM_INFO.[28] = 1.
-
- @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);
- @endcode
-**/
-#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:31;
- ///
- /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
- /// the processor uses override configuration specified in
- /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor
- /// uses factory-set configuration (Default).
- ///
- UINT32 TurboRatioLimitConfigurationSemaphore:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- * Bank MC5 reports MC error from the Intel QPI 0 module.
- * Bank MC6 reports MC error from the integrated I/O module.
- * Bank MC7 reports MC error from the home agent HA 0.
- * Bank MC8 reports MC error from the home agent HA 1.
- * Banks MC9 through MC16 report MC error from each channel of the integrated
- memory controllers.
- * Bank MC17 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.
- * Bank MC18 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.
- * Bank MC19 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.
- * Bank MC20 reports MC error from the Intel QPI 1 module.
- * Bank MC21 reports MC error from the Intel QPI 2 module.
-
- @param ECX MSR_XEON_D_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_MC5_CTL);
- AsmWriteMsr64 (MSR_XEON_D_MC5_CTL, Msr);
- @endcode
- @{
-**/
-#define MSR_XEON_D_MC5_CTL 0x00000414
-#define MSR_XEON_D_MC6_CTL 0x00000418
-#define MSR_XEON_D_MC7_CTL 0x0000041C
-#define MSR_XEON_D_MC8_CTL 0x00000420
-#define MSR_XEON_D_MC9_CTL 0x00000424
-#define MSR_XEON_D_MC10_CTL 0x00000428
-#define MSR_XEON_D_MC11_CTL 0x0000042C
-#define MSR_XEON_D_MC12_CTL 0x00000430
-#define MSR_XEON_D_MC13_CTL 0x00000434
-#define MSR_XEON_D_MC14_CTL 0x00000438
-#define MSR_XEON_D_MC15_CTL 0x0000043C
-#define MSR_XEON_D_MC16_CTL 0x00000440
-#define MSR_XEON_D_MC17_CTL 0x00000444
-#define MSR_XEON_D_MC18_CTL 0x00000448
-#define MSR_XEON_D_MC19_CTL 0x0000044C
-#define MSR_XEON_D_MC20_CTL 0x00000450
-#define MSR_XEON_D_MC21_CTL 0x00000454
-/// @}
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_XEON_D_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_STATUS);
- AsmWriteMsr64 (MSR_XEON_D_MC6_STATUS, Msr);
- @endcode
- @{
-**/
-#define MSR_XEON_D_MC5_STATUS 0x00000415
-#define MSR_XEON_D_MC6_STATUS 0x00000419
-#define MSR_XEON_D_MC7_STATUS 0x0000041D
-#define MSR_XEON_D_MC8_STATUS 0x00000421
-#define MSR_XEON_D_MC9_STATUS 0x00000425
-#define MSR_XEON_D_MC10_STATUS 0x00000429
-#define MSR_XEON_D_MC11_STATUS 0x0000042D
-#define MSR_XEON_D_MC12_STATUS 0x00000431
-#define MSR_XEON_D_MC13_STATUS 0x00000435
-#define MSR_XEON_D_MC14_STATUS 0x00000439
-#define MSR_XEON_D_MC15_STATUS 0x0000043D
-#define MSR_XEON_D_MC16_STATUS 0x00000441
-#define MSR_XEON_D_MC17_STATUS 0x00000445
-#define MSR_XEON_D_MC18_STATUS 0x00000449
-#define MSR_XEON_D_MC19_STATUS 0x0000044D
-#define MSR_XEON_D_MC20_STATUS 0x00000451
-#define MSR_XEON_D_MC21_STATUS 0x00000455
-/// @}
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_XEON_D_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_ADDR);
- AsmWriteMsr64 (MSR_XEON_D_MC6_ADDR, Msr);
- @endcode
- @{
-**/
-#define MSR_XEON_D_MC5_ADDR 0x00000416
-#define MSR_XEON_D_MC6_ADDR 0x0000041A
-#define MSR_XEON_D_MC7_ADDR 0x0000041E
-#define MSR_XEON_D_MC8_ADDR 0x00000422
-#define MSR_XEON_D_MC9_ADDR 0x00000426
-#define MSR_XEON_D_MC10_ADDR 0x0000042A
-#define MSR_XEON_D_MC11_ADDR 0x0000042E
-#define MSR_XEON_D_MC12_ADDR 0x00000432
-#define MSR_XEON_D_MC13_ADDR 0x00000436
-#define MSR_XEON_D_MC14_ADDR 0x0000043A
-#define MSR_XEON_D_MC15_ADDR 0x0000043E
-#define MSR_XEON_D_MC16_ADDR 0x00000442
-#define MSR_XEON_D_MC17_ADDR 0x00000446
-#define MSR_XEON_D_MC18_ADDR 0x0000044A
-#define MSR_XEON_D_MC19_ADDR 0x0000044E
-#define MSR_XEON_D_MC20_ADDR 0x00000452
-#define MSR_XEON_D_MC21_ADDR 0x00000456
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_XEON_D_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_MISC);
- AsmWriteMsr64 (MSR_XEON_D_MC6_MISC, Msr);
- @endcode
- @{
-**/
-#define MSR_XEON_D_MC5_MISC 0x00000417
-#define MSR_XEON_D_MC6_MISC 0x0000041B
-#define MSR_XEON_D_MC7_MISC 0x0000041F
-#define MSR_XEON_D_MC8_MISC 0x00000423
-#define MSR_XEON_D_MC9_MISC 0x00000427
-#define MSR_XEON_D_MC10_MISC 0x0000042B
-#define MSR_XEON_D_MC11_MISC 0x0000042F
-#define MSR_XEON_D_MC12_MISC 0x00000433
-#define MSR_XEON_D_MC13_MISC 0x00000437
-#define MSR_XEON_D_MC14_MISC 0x0000043B
-#define MSR_XEON_D_MC15_MISC 0x0000043F
-#define MSR_XEON_D_MC16_MISC 0x00000443
-#define MSR_XEON_D_MC17_MISC 0x00000447
-#define MSR_XEON_D_MC18_MISC 0x0000044B
-#define MSR_XEON_D_MC19_MISC 0x0000044F
-#define MSR_XEON_D_MC20_MISC 0x00000453
-#define MSR_XEON_D_MC21_MISC 0x00000457
-/// @}
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_XEON_D_PKG_C8_RESIDENCY (0x00000630)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_PKG_C8_RESIDENCY 0x00000630
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PKG_C8_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
- /// that this package is in processor-specific C8 states. Count at the
- /// same frequency as the TSC.
- ///
- UINT32 C8ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C8 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C8ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_XEON_D_PKG_C9_RESIDENCY (0x00000631)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_PKG_C9_RESIDENCY 0x00000631
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PKG_C9_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
- /// that this package is in processor-specific C9 states. Count at the
- /// same frequency as the TSC.
- ///
- UINT32 C9ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C9 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C9ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_XEON_D_PKG_C10_RESIDENCY (0x00000632)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_PKG_C10_RESIDENCY 0x00000632
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PKG_C10_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C10 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C10ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C10 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C10ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER;
-
-
-/**
- Package. Cache Allocation Technology Configuration (R/W).
-
- @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);
- AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.
- ///
- UINT32 CAT:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h deleted file mode 100644 index b95f963b1e..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h +++ /dev/null @@ -1,254 +0,0 @@ -/** @file
- MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.
-
-**/
-
-#ifndef __XEON_E7_MSR_H__
-#define __XEON_E7_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Package. Reserved Attempt to read/write will cause #UD.
-
- @param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
- AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
- @endcode
-**/
-#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD
-
-
-/**
- Package. Uncore C-box 8 perfmon local box control MSR.
-
- @param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40
-
-
-/**
- Package. Uncore C-box 8 perfmon local box status MSR.
-
- @param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41
-
-
-/**
- Package. Uncore C-box 8 perfmon local box overflow control MSR.
-
- @param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42
-
-
-/**
- Package. Uncore C-box 8 perfmon event select MSR.
-
- @param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
- @endcode
- @{
-**/
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A
-/// @}
-
-
-/**
- Package. Uncore C-box 8 perfmon counter MSR.
-
- @param ECX MSR_XEON_E7_C8_PMON_CTRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
- @endcode
- @{
-**/
-#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51
-#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53
-#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55
-#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57
-#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59
-#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B
-/// @}
-
-
-/**
- Package. Uncore C-box 9 perfmon local box control MSR.
-
- @param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
- @endcode
-**/
-#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0
-
-
-/**
- Package. Uncore C-box 9 perfmon local box status MSR.
-
- @param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
- @endcode
-**/
-#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1
-
-
-/**
- Package. Uncore C-box 9 perfmon local box overflow control MSR.
-
- @param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
- @endcode
-**/
-#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2
-
-
-/**
- Package. Uncore C-box 9 perfmon event select MSR.
-
- @param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
- @endcode
- @{
-**/
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA
-/// @}
-
-
-/**
- Package. Uncore C-box 9 perfmon counter MSR.
-
- @param ECX MSR_XEON_E7_C9_PMON_CTRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
- @endcode
- @{
-**/
-#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1
-#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3
-#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5
-#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7
-#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9
-#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB
-/// @}
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h deleted file mode 100644 index 6695b69161..0000000000 --- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h +++ /dev/null @@ -1,1426 +0,0 @@ -/** @file
- MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.
-
-**/
-
-#ifndef __XEON_PHI_MSR_H__
-#define __XEON_PHI_MSR_H__
-
-#include <Register/ArchitecturalMsr.h>
-
-/**
- Thread. SMI Counter (R/O).
-
- @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
- @endcode
-**/
-#define MSR_XEON_PHI_SMI_COUNT 0x00000034
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] SMI Count (R/O).
- ///
- UINT32 SMICount:32;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_SMI_COUNT_REGISTER;
-
-
-/**
- Package. See http://biosbits.org.
-
- @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
- AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
- /// MHz.
- ///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:12;
- ///
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for
- /// Turbo mode is disabled.
- ///
- UINT32 RatioLimit:1;
- ///
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
- /// and when set to 0, indicates TDP Limit for Turbo mode is not
- /// programmable.
- ///
- UINT32 TDPLimit:1;
- UINT32 Reserved3:2;
- UINT32 Reserved4:8;
- ///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
- /// minimum ratio (maximum efficiency) that the processor can operates, in
- /// units of 100MHz.
- ///
- UINT32 MaximumEfficiencyRatio:8;
- UINT32 Reserved5:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
-
-
-/**
- Module. C-State Configuration Control (R/W).
-
- @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code
- /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
- /// Retention 011b: C6 Retention 111b: No limit.
- ///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
- ///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
- ///
- /// [Bit 15] CFG Lock (R/WO).
- ///
- UINT32 CFGLock:1;
- UINT32 Reserved3:16;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;
-
-
-/**
- Module. Power Management IO Redirection in C-state (R/W).
-
- @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
- AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] LVL_2 Base Address (R/W).
- ///
- UINT32 Lvl2Base:16;
- ///
- /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
- /// maximum C-State code name to be included when IO read to MWAIT
- /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
- /// is the max C-State to include 110b - C6 is the max C-State to include.
- ///
- UINT32 CStateRange:3;
- UINT32 Reserved1:13;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
-
-
-/**
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
- handler to handle unsuccessful read of this MSR.
-
- @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
- AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
- /// MSR, the configuration of AES instruction set availability is as
- /// follows: 11b: AES instructions are not available until next RESET.
- /// otherwise, AES instructions are available. Note, AES instruction set
- /// is not available if read is unsuccessful. If the configuration is not
- /// 01b, AES instruction can be mis-configured if a privileged agent
- /// unintentionally writes 11b.
- ///
- UINT32 AESConfiguration:2;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
-
-
-/**
- Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Fast-Strings Enable.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W).
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Performance Monitoring Available (R).
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
- ///
- /// [Bit 11] Branch Trace Storage Unavailable (RO).
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Precise Event Based Sampling Unavailable (RO).
- ///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
- ///
- /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
- ///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 18] ENABLE MONITOR FSM (R/W).
- ///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
- ///
- /// [Bit 22] Limit CPUID Maxval (R/W).
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] xTPR Message Disable (R/W).
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
- ///
- /// [Bit 34] XD Bit Disable (R/W).
- ///
- UINT32 XD:1;
- UINT32 Reserved9:3;
- ///
- /// [Bit 38] Turbo Mode Disable (R/W).
- ///
- UINT32 TurboModeDisable:1;
- UINT32 Reserved10:25;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Package.
-
- @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
- AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:16;
- ///
- /// [Bits 23:16] Temperature Target (R).
- ///
- UINT32 TemperatureTarget:8;
- ///
- /// [Bits 29:24] Target Offset (R/W).
- ///
- UINT32 TargetOffset:6;
- UINT32 Reserved2:2;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;
-
-
-/**
- Shared. Offcore Response Event Select Register (R/W).
-
- @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
- AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
-
-
-/**
- Shared. Offcore Response Event Select Register (R/W).
-
- @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
- AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
-
-
-/**
- Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
-
- @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
- AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:1;
- ///
- /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
- /// processor cores which operates under the maximum ratio limit for group
- /// 0.
- ///
- UINT32 MaxCoresGroup0:7;
- ///
- /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
- /// ratio limit when the number of active cores are not more than the
- /// group 0 maximum core count.
- ///
- UINT32 MaxRatioLimitGroup0:8;
- ///
- /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
- /// Group 1, which includes the specified number of additional cores plus
- /// the cores in group 0, operates under the group 1 turbo max ratio limit
- /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
- ///
- UINT32 MaxIncrementalCoresGroup1:5;
- ///
- /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
- /// integer specifying the ratio decrement relative to the Max ratio limit
- /// to Group 0.
- ///
- UINT32 DeltaRatioGroup1:3;
- ///
- /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
- /// Group 2, which includes the specified number of additional cores plus
- /// all the cores in group 1, operates under the group 2 turbo max ratio
- /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
- ///
- UINT32 MaxIncrementalCoresGroup2:5;
- ///
- /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
- /// integer specifying the ratio decrement relative to the Max ratio limit
- /// for Group 1.
- ///
- UINT32 DeltaRatioGroup2:3;
- ///
- /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
- /// Group 3, which includes the specified number of additional cores plus
- /// all the cores in group 2, operates under the group 3 turbo max ratio
- /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
- ///
- UINT32 MaxIncrementalCoresGroup3:5;
- ///
- /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
- /// integer specifying the ratio decrement relative to the Max ratio limit
- /// for Group 2.
- ///
- UINT32 DeltaRatioGroup3:3;
- ///
- /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
- /// Group 4, which includes the specified number of additional cores plus
- /// all the cores in group 3, operates under the group 4 turbo max ratio
- /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
- ///
- UINT32 MaxIncrementalCoresGroup4:5;
- ///
- /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
- /// integer specifying the ratio decrement relative to the Max ratio limit
- /// for Group 3.
- ///
- UINT32 DeltaRatioGroup4:3;
- ///
- /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
- /// Group 5, which includes the specified number of additional cores plus
- /// all the cores in group 4, operates under the group 5 turbo max ratio
- /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
- ///
- UINT32 MaxIncrementalCoresGroup5:5;
- ///
- /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
- /// integer specifying the ratio decrement relative to the Max ratio limit
- /// for Group 4.
- ///
- UINT32 DeltaRatioGroup5:3;
- ///
- /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
- /// Group 6, which includes the specified number of additional cores plus
- /// all the cores in group 5, operates under the group 6 turbo max ratio
- /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
- ///
- UINT32 MaxIncrementalCoresGroup6:5;
- ///
- /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
- /// integer specifying the ratio decrement relative to the Max ratio limit
- /// for Group 5.
- ///
- UINT32 DeltaRatioGroup6:3;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;
-
-
-/**
- Thread. Last Branch Record Filtering Select Register (R/W).
-
- @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
- AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_LBR_SELECT 0x000001C8
-
-
-/**
- Thread. Last Branch Record Stack TOS (R/W).
-
- @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
- AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
-
-
-/**
- Thread. Last Exception Record From Linear IP (R).
-
- @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
- @endcode
-**/
-#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
-
-
-/**
- Thread. Last Exception Record To Linear IP (R).
-
- @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
- @endcode
-**/
-#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
-
-
-/**
- Thread. See Table 35-2.
-
- @param ECX MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Thread. See Table 35-2.
-
- @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
- Residency Counter. (R/O).
-
- @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
-
-
-/**
- Package. Package C6 Residency Counter. (R/O).
-
- @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
-
-
-/**
- Package. Package C7 Residency Counter. (R/O).
-
- @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
-
-
-/**
- Module. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
- Residency Counter. (R/O).
-
- @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
-
-
-/**
- Module. Module C6 Residency Counter. (R/O).
-
- @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
-
-
-/**
- Core. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
- Residency Counter. (R/O).
-
- @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
-
-
-/**
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_XEON_PHI_MC3_CTL (0x0000040C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC3_CTL 0x0000040C
-
-
-/**
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_XEON_PHI_MC3_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC3_STATUS 0x0000040D
-
-
-/**
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
-
- @param ECX MSR_XEON_PHI_MC3_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC3_ADDR 0x0000040E
-
-
-/**
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_XEON_PHI_MC4_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC4_CTL 0x00000410
-
-
-/**
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_XEON_PHI_MC4_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC4_STATUS 0x00000411
-
-
-/**
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register
- is either not implemented or contains no address if the ADDRV flag in the
- MSR_MC4_STATUS register is clear. When not implemented in the processor, all
- reads and writes to this MSR will cause a general-protection exception.
-
- @param ECX MSR_XEON_PHI_MC4_ADDR (0x00000412)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC4_ADDR 0x00000412
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_XEON_PHI_MC5_CTL (0x00000414)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC5_CTL 0x00000414
-
-
-/**
- Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_XEON_PHI_MC5_STATUS (0x00000415)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC5_STATUS 0x00000415
-
-
-/**
- Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
-
- @param ECX MSR_XEON_PHI_MC5_ADDR (0x00000416)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_MC5_ADDR 0x00000416
-
-
-/**
- Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
-
- @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
- @endcode
-**/
-#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
-
-
-/**
- Core. Capability Reporting Register of VM-function Controls (R/O) See Table
- 35-2.
-
- @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
- @endcode
-**/
-#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
-
-
-/**
- Package. Unit Multipliers used in RAPL Interfaces (R/O).
-
- @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
- @endcode
-**/
-#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
- ///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
- ///
- /// [Bits 12:8] Package. Energy Status Units Energy related information
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
- /// micro-joules).
- ///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
- ///
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
- /// Interfaces.".
- ///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
- Residency Counter. (R/O).
-
- @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
-
-
-/**
- Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
- RAPL Domain.".
-
- @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
-
-
-/**
- Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
-
- @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
-
-
-/**
- Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
-
- @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
-
-
-/**
- Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
- Domain.".
-
- @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
-
-
-/**
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
- Domain.".
-
- @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
- AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
-
-
-/**
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
-
-
-/**
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
- RAPL Domain.".
-
- @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
- @endcode
-**/
-#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
-
-
-/**
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
-
- @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
- AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
-
-
-/**
- Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
- RAPL Domains.".
-
- @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
- AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
-
-
-/**
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
- Domains.".
-
- @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
- @endcode
-**/
-#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
-
-
-/**
- Package. Base TDP Ratio (R/O) See Table 35-20.
-
- @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
- @endcode
-**/
-#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
-
-
-/**
- Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-20.
-
- @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
- @endcode
-**/
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
-
-
-/**
- Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-20.
-
- @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
- @endcode
-**/
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
-
-
-/**
- Package. ConfigTDP Control (R/W) See Table 35-20.
-
- @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
- AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
-
-
-/**
- Package. ConfigTDP Control (R/W) See Table 35-20.
-
- @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
- AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
- @endcode
-**/
-#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
-
-
-/**
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
- refers to processor core frequency).
-
- @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
- AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
- @endcode
-**/
-#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
-
-/**
- MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] PROCHOT Status (R0).
- ///
- UINT32 PROCHOT_Status:1;
- ///
- /// [Bit 1] Thermal Status (R0).
- ///
- UINT32 ThermalStatus:1;
- UINT32 Reserved1:4;
- ///
- /// [Bit 6] VR Therm Alert Status (R0).
- ///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 8] Electrical Design Point Status (R0).
- ///
- UINT32 ElectricalDesignPointStatus:1;
- UINT32 Reserved3:23;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;
-
-#endif
diff --git a/UefiCpuPkg/Include/Register/SmramSaveStateMap.h b/UefiCpuPkg/Include/Register/SmramSaveStateMap.h deleted file mode 100644 index a7c7562df8..0000000000 --- a/UefiCpuPkg/Include/Register/SmramSaveStateMap.h +++ /dev/null @@ -1,190 +0,0 @@ -/** @file
-SMRAM Save State Map Definitions.
-
-SMRAM Save State Map definitions based on contents of the
-Intel(R) 64 and IA-32 Architectures Software Developer's Manual
- Volume 3C, Section 34.4 SMRAM
- Volume 3C, Section 34.5 SMI Handler Execution Environment
- Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
-
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __SMRAM_SAVE_STATE_MAP_H__
-#define __SMRAM_SAVE_STATE_MAP_H__
-
-///
-/// Default SMBASE address
-///
-#define SMM_DEFAULT_SMBASE 0x30000
-
-///
-/// Offset of SMM handler from SMBASE
-///
-#define SMM_HANDLER_OFFSET 0x8000
-
-///
-/// Offset of SMRAM Save State Map from SMBASE
-///
-#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00
-
-#pragma pack (1)
-
-///
-/// 32-bit SMRAM Save State Map
-///
-typedef struct {
- UINT8 Reserved[0x200]; // 7c00h
- // Padded an extra 0x200 bytes so 32-bit and 64-bit
- // SMRAM Save State Maps are the same size
- UINT8 Reserved1[0xf8]; // 7e00h
- UINT32 SMBASE; // 7ef8h
- UINT32 SMMRevId; // 7efch
- UINT16 IORestart; // 7f00h
- UINT16 AutoHALTRestart; // 7f02h
- UINT8 Reserved2[0x9C]; // 7f08h
- UINT32 IOMemAddr; // 7fa0h
- UINT32 IOMisc; // 7fa4h
- UINT32 _ES; // 7fa8h
- UINT32 _CS; // 7fach
- UINT32 _SS; // 7fb0h
- UINT32 _DS; // 7fb4h
- UINT32 _FS; // 7fb8h
- UINT32 _GS; // 7fbch
- UINT32 Reserved3; // 7fc0h
- UINT32 _TR; // 7fc4h
- UINT32 _DR7; // 7fc8h
- UINT32 _DR6; // 7fcch
- UINT32 _EAX; // 7fd0h
- UINT32 _ECX; // 7fd4h
- UINT32 _EDX; // 7fd8h
- UINT32 _EBX; // 7fdch
- UINT32 _ESP; // 7fe0h
- UINT32 _EBP; // 7fe4h
- UINT32 _ESI; // 7fe8h
- UINT32 _EDI; // 7fech
- UINT32 _EIP; // 7ff0h
- UINT32 _EFLAGS; // 7ff4h
- UINT32 _CR3; // 7ff8h
- UINT32 _CR0; // 7ffch
-} SMRAM_SAVE_STATE_MAP32;
-
-///
-/// 64-bit SMRAM Save State Map
-///
-typedef struct {
- UINT8 Reserved1[0x1d0]; // 7c00h
- UINT32 GdtBaseHiDword; // 7dd0h
- UINT32 LdtBaseHiDword; // 7dd4h
- UINT32 IdtBaseHiDword; // 7dd8h
- UINT8 Reserved2[0xc]; // 7ddch
- UINT64 IO_EIP; // 7de8h
- UINT8 Reserved3[0x50]; // 7df0h
- UINT32 _CR4; // 7e40h
- UINT8 Reserved4[0x48]; // 7e44h
- UINT32 GdtBaseLoDword; // 7e8ch
- UINT32 Reserved5; // 7e90h
- UINT32 IdtBaseLoDword; // 7e94h
- UINT32 Reserved6; // 7e98h
- UINT32 LdtBaseLoDword; // 7e9ch
- UINT8 Reserved7[0x38]; // 7ea0h
- UINT64 EptVmxControl; // 7ed8h
- UINT32 EnEptVmxControl; // 7ee0h
- UINT8 Reserved8[0x14]; // 7ee4h
- UINT32 SMBASE; // 7ef8h
- UINT32 SMMRevId; // 7efch
- UINT16 IORestart; // 7f00h
- UINT16 AutoHALTRestart; // 7f02h
- UINT8 Reserved9[0x18]; // 7f04h
- UINT64 _R15; // 7f1ch
- UINT64 _R14;
- UINT64 _R13;
- UINT64 _R12;
- UINT64 _R11;
- UINT64 _R10;
- UINT64 _R9;
- UINT64 _R8;
- UINT64 _RAX; // 7f5ch
- UINT64 _RCX;
- UINT64 _RDX;
- UINT64 _RBX;
- UINT64 _RSP;
- UINT64 _RBP;
- UINT64 _RSI;
- UINT64 _RDI;
- UINT64 IOMemAddr; // 7f9ch
- UINT32 IOMisc; // 7fa4h
- UINT32 _ES; // 7fa8h
- UINT32 _CS;
- UINT32 _SS;
- UINT32 _DS;
- UINT32 _FS;
- UINT32 _GS;
- UINT32 _LDTR; // 7fc0h
- UINT32 _TR;
- UINT64 _DR7; // 7fc8h
- UINT64 _DR6;
- UINT64 _RIP; // 7fd8h
- UINT64 IA32_EFER; // 7fe0h
- UINT64 _RFLAGS; // 7fe8h
- UINT64 _CR3; // 7ff0h
- UINT64 _CR0; // 7ff8h
-} SMRAM_SAVE_STATE_MAP64;
-
-///
-/// Union of 32-bit and 64-bit SMRAM Save State Maps
-///
-typedef union {
- SMRAM_SAVE_STATE_MAP32 x86;
- SMRAM_SAVE_STATE_MAP64 x64;
-} SMRAM_SAVE_STATE_MAP;
-
-///
-/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map
-///
-#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004
-
-///
-/// SMRAM Save State Map IOMisc I/O Length Values
-///
-#define SMM_IO_LENGTH_BYTE 0x01
-#define SMM_IO_LENGTH_WORD 0x02
-#define SMM_IO_LENGTH_DWORD 0x04
-
-///
-/// SMRAM Save State Map IOMisc I/O Instruction Type Values
-///
-#define SMM_IO_TYPE_IN_IMMEDIATE 0x9
-#define SMM_IO_TYPE_IN_DX 0x1
-#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8
-#define SMM_IO_TYPE_OUT_DX 0x0
-#define SMM_IO_TYPE_INS 0x3
-#define SMM_IO_TYPE_OUTS 0x2
-#define SMM_IO_TYPE_REP_INS 0x7
-#define SMM_IO_TYPE_REP_OUTS 0x6
-
-///
-/// SMRAM Save State Map IOMisc structure
-///
-typedef union {
- struct {
- UINT32 SmiFlag:1;
- UINT32 Length:3;
- UINT32 Type:4;
- UINT32 Reserved1:8;
- UINT32 Port:16;
- } Bits;
- UINT32 Uint32;
-} SMRAM_SAVE_STATE_IOMISC;
-
-#pragma pack ()
-
-#endif
|