diff options
| author | Michael Kinney <michael.d.kinney@intel.com> | 2016-11-29 06:36:51 +0800 |
|---|---|---|
| committer | Feng Tian <feng.tian@intel.com> | 2016-12-19 09:32:43 +0800 |
| commit | 09119a00cccaa08b28b7e2449998ba4c7aa4b0f8 (patch) | |
| tree | 3b07c9a53b4c604899a2095b287d5295891d155c /UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm | |
| parent | 4c6351db25eaf24335933ce3499258d7b48a57b2 (diff) | |
| download | edk2-platforms-09119a00cccaa08b28b7e2449998ba4c7aa4b0f8.tar.xz | |
UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance
Add a new instances of the SmmCpuFeaturesLib that is used by
platforms to enable the SMI Transfer Monitor(STM) feature.
This new instance is in the same directory as the default
SmmCpuFeaturesLib instance in order to share source files.
The DSC file is updated to build both SmmCpuFeatureLib
instances and to build two versions of the PiSmmCpuDxeSmm
module using each of the SmmCpuFeatureLib instances.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm')
| -rw-r--r-- | UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm | 170 |
1 files changed, 170 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm new file mode 100644 index 0000000000..7c04ad91f2 --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm @@ -0,0 +1,170 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiException.asm
+;
+; Abstract:
+;
+; Exception handlers used in SM mode
+;
+;-------------------------------------------------------------------------------
+
+ .686p
+ .model flat,C
+
+EXTERNDEF gcStmPsd:BYTE
+
+EXTERNDEF SmmStmExceptionHandler:PROC
+EXTERNDEF SmmStmSetup:PROC
+EXTERNDEF SmmStmTeardown:PROC
+
+CODE_SEL = 08h
+DATA_SEL = 20h
+TSS_SEL = 40h
+
+ .data
+
+gcStmPsd LABEL BYTE
+ DB 'TXTPSSIG'
+ DW PSD_SIZE
+ DW 1 ; Version
+ DD 0 ; LocalApicId
+ DB 05h ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
+ DB 0 ; BIOS to STM
+ DB 0 ; STM to BIOS
+ DB 0
+ DW CODE_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW TSS_SEL
+ DW 0
+ DQ 0 ; SmmCr3
+ DQ _OnStmSetup
+ DQ _OnStmTeardown
+ DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
+ DQ 0 ; SmmSmiHandlerRsp
+ DQ 0
+ DD 0
+ DD 80010100h ; RequiredStmSmmRevId
+ DQ _OnException
+ DQ 0 ; ExceptionStack
+ DW DATA_SEL
+ DW 01Fh ; ExceptionFilter
+ DD 0
+ DQ 0
+ DQ 0 ; BiosHwResourceRequirementsPtr
+ DQ 0 ; AcpiRsdp
+ DB 0 ; PhysicalAddressBits
+PSD_SIZE = $ - offset gcStmPsd
+
+ .code
+;------------------------------------------------------------------------------
+; SMM Exception handlers
+;------------------------------------------------------------------------------
+_OnException PROC
+ mov ecx, esp
+ push ecx
+ call SmmStmExceptionHandler
+ add esp, 4
+
+ mov ebx, eax
+ mov eax, 4
+ DB 0fh, 01h, 0c1h ; VMCALL
+ jmp $
+_OnException ENDP
+
+_OnStmSetup PROC
+;
+; Check XD disable bit
+;
+ xor esi, esi
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @StmXdDone1
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone1:
+ push esi
+
+ call SmmStmSetup
+
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @f
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz @f
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+@@:
+
+ rsm
+_OnStmSetup ENDP
+
+_OnStmTeardown PROC
+;
+; Check XD disable bit
+;
+ xor esi, esi
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @StmXdDone2
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone2:
+ push esi
+
+ call SmmStmTeardown
+
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @f
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz @f
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+@@:
+
+ rsm
+_OnStmTeardown ENDP
+
+ END
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