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| author | Michael Kinney <michael.d.kinney@intel.com> | 2015-12-24 00:13:47 +0000 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-02-25 09:46:20 +0800 |
| commit | 7233344929570e0d41e0774eb1216d2f9b5c6b19 (patch) | |
| tree | d1daf60f4e3909638ef9524e9acfe2bed5340565 /UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | |
| parent | bf6e577dbaaf387e47cf008219931dfcacb18943 (diff) | |
| download | edk2-platforms-7233344929570e0d41e0774eb1216d2f9b5c6b19.tar.xz | |
UefiCpuPkg/PiSmmCpuDxeSmm: Fix failure when PcdCpuSmmDebug is TRUE
If PcdCpuSmmDebug is set to TRUE, then the first time the function
CpuSmmDebugEntry () is called during the first normal SMI, the
registers DR6 or DR7 may be set to invalid values due to gSmst
not being fully initialized yet. Instead, use gSmmCpuPrivate that
is fully initialized for the first SMI to look up CpuSaveState
for the currently executing CPU.
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19502 6f19259b-4bc3-4df7-8a09-765794883524
(cherry picked from commit 3eed6dda20149609ceb8b50318a780f1a1422341)
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 620b0136c5..79b7c90a80 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -943,7 +943,7 @@ SmmStartupThisAp ( }
/**
- This funciton sets DR6 & DR7 according to SMM save state, before running SMM C code.
+ This function sets DR6 & DR7 according to SMM save state, before running SMM C code.
They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.
NOTE: It might not be appreciated in runtime since it might
@@ -961,7 +961,7 @@ CpuSmmDebugEntry ( SMRAM_SAVE_STATE_MAP *CpuSaveState;
if (FeaturePcdGet (PcdCpuSmmDebug)) {
- CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
+ CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
AsmWriteDr6 (CpuSaveState->x86._DR6);
AsmWriteDr7 (CpuSaveState->x86._DR7);
@@ -973,7 +973,7 @@ CpuSmmDebugEntry ( }
/**
- This funciton restores DR6 & DR7 to SMM save state.
+ This function restores DR6 & DR7 to SMM save state.
NOTE: It might not be appreciated in runtime since it might
conflict with OS debugging facilities. Turn them off in RELEASE.
@@ -990,7 +990,7 @@ CpuSmmDebugExit ( SMRAM_SAVE_STATE_MAP *CpuSaveState;
if (FeaturePcdGet (PcdCpuSmmDebug)) {
- CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
+ CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();
CpuSaveState->x86._DR6 = (UINT32)AsmReadDr6 ();
|