diff options
| author | Yao, Jiewen <jiewen.yao@intel.com> | 2015-11-26 07:01:08 +0000 |
|---|---|---|
| committer | jyao1 <jyao1@Edk2> | 2015-11-26 07:01:08 +0000 |
| commit | 8e496a7abcb78c36b0af47ed473096ef7f171606 (patch) | |
| tree | 780d46ef05f34a2c82220006b79cfdc8e7f70fee /UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | |
| parent | 989edf1633ab9a9fc9904c90b1a49ae84c5bbbe2 (diff) | |
| download | edk2-platforms-8e496a7abcb78c36b0af47ed473096ef7f171606.tar.xz | |
Always set WP in CR0.
Always set RW+P bit for page table by default.
So that we can use write-protection for code later.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18960 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index ff4e28ec58..ec4ec9b067 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -557,9 +557,9 @@ InitPaging ( // Split it
for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {
- Pt[Level4] = Address + ((Level4 << 12) | IA32_PG_RW | IA32_PG_P);
+ Pt[Level4] = Address + ((Level4 << 12) | PAGE_ATTRIBUTE_BITS);
} // end for PT
- *Pte = (UINTN)Pt | IA32_PG_RW | IA32_PG_P;
+ *Pte = (UINTN)Pt | PAGE_ATTRIBUTE_BITS;
} // end if IsAddressSplit
} // end for PTE
} // end for PDE
@@ -608,7 +608,7 @@ InitPaging ( //
// Patch to remove Present flag and RW flag
//
- *Pte = *Pte & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));
+ *Pte = *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
if (Nx && mXdSupported) {
*Pte = *Pte | IA32_PG_NX;
@@ -621,7 +621,7 @@ InitPaging ( }
for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {
if (!IsAddressValid (Address, &Nx)) {
- *Pt = *Pt & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));
+ *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
if (Nx && mXdSupported) {
*Pt = *Pt | IA32_PG_NX;
@@ -1244,7 +1244,7 @@ RestorePageTableBelow4G ( //
PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));
PageTable[PTIndex] |= (UINT64)IA32_PG_PS;
- PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);
+ PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;
if ((ErrorCode & IA32_PF_EC_ID) != 0) {
PageTable[PTIndex] &= ~IA32_PG_NX;
}
@@ -1277,7 +1277,7 @@ RestorePageTableBelow4G ( // Set new entry
//
PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));
- PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);
+ PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;
if ((ErrorCode & IA32_PF_EC_ID) != 0) {
PageTable[PTIndex] &= ~IA32_PG_NX;
}
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