diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2014-08-18 23:03:46 +0000 |
|---|---|---|
| committer | jljusten <jljusten@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-18 23:03:46 +0000 |
| commit | eee1d2ca9078742157c843562f1188eb96473322 (patch) | |
| tree | 7609cb1cb555df09eb50a6a116e694a83421b55d /UefiCpuPkg/ResetVector/Vtf0/Ia16 | |
| parent | 5a1f324d946cb1be2dc1226752b1965d6633232f (diff) | |
| download | edk2-platforms-eee1d2ca9078742157c843562f1188eb96473322.tar.xz | |
UefiCpuPkg VTF0 X64: Build page tables in NASM code
Previously, we would build the page tables in
Tools/FixupForRawSection.py.
In order to let NASM build VTF0 from source during the EDK II build
process, we need to move this into the VTF0 NASM code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15822 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'UefiCpuPkg/ResetVector/Vtf0/Ia16')
| -rw-r--r-- | UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm index 610b956eb3..142d9f3212 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm @@ -2,7 +2,7 @@ ; @file
; First code executed by processor after resetting.
;
-; Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -17,6 +17,19 @@ BITS 16 ALIGN 16
+;
+; Pad the image size to 4k when page tables are in VTF0
+;
+; If the VTF0 image has page tables built in, then we need to make
+; sure the end of VTF0 is 4k above where the page tables end.
+;
+; This is required so the page tables will be 4k aligned when VTF0 is
+; located just below 0x100000000 (4GB) in the firmware device.
+;
+%ifdef ALIGN_TOP_TO_4K_FOR_PAGING
+ TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0
+%endif
+
applicationProcessorEntryPoint:
;
; Application Processors entry point
@@ -25,7 +38,7 @@ applicationProcessorEntryPoint: ; location. (0xffffffe0) This allows the Local APIC Startup IPI to be
; used to wake up the application processors.
;
- jmp short EarlyApInitReal16
+ jmp EarlyApInitReal16
ALIGN 8
@@ -50,7 +63,7 @@ resetVector: ;
nop
nop
- jmp short EarlyBspInitReal16
+ jmp EarlyBspInitReal16
ALIGN 16
|