UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

1 files changed, 58 insertions, 0 deletions

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index 78915ec7a4..f7cb6ce39f 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -42,6 +42,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);

   AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.

 **/

 #define MSR_HASWELL_PLATFORM_INFO                0x000000CE

 

@@ -126,6 +127,9 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);

   AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.

+        MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.

+        MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.

   @{

 **/

 #define MSR_HASWELL_IA32_PERFEVTSEL0             0x00000186

@@ -226,6 +230,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);

   AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.

 **/

 #define MSR_HASWELL_IA32_PERFEVTSEL2             0x00000188

 

@@ -330,6 +335,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);

   AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.

 **/

 #define MSR_HASWELL_LBR_SELECT                   0x000001C8

 

@@ -416,6 +422,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);

   AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.

 **/

 #define MSR_HASWELL_PKGC_IRTL1                   0x0000060B

 

@@ -487,6 +494,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);

   AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.

 **/

 #define MSR_HASWELL_PKGC_IRTL2                   0x0000060C

 

@@ -550,6 +558,7 @@ typedef union {
 

   Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);

   @endcode

+  @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.

 **/

 #define MSR_HASWELL_PKG_PERF_STATUS              0x00000613

 

@@ -567,6 +576,7 @@ typedef union {
 

   Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);

   @endcode

+  @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.

 **/

 #define MSR_HASWELL_DRAM_ENERGY_STATUS           0x00000619

 

@@ -585,6 +595,7 @@ typedef union {
 

   Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);

   @endcode

+  @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.

 **/

 #define MSR_HASWELL_DRAM_PERF_STATUS             0x0000061B

 

@@ -604,6 +615,7 @@ typedef union {
 

   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);

   @endcode

+  @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.

 **/

 #define MSR_HASWELL_CONFIG_TDP_NOMINAL           0x00000648

 

@@ -649,6 +661,7 @@ typedef union {
 

   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);

   @endcode

+  @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.

 **/

 #define MSR_HASWELL_CONFIG_TDP_LEVEL1            0x00000649

 

@@ -705,6 +718,7 @@ typedef union {
 

   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);

   @endcode

+  @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.

 **/

 #define MSR_HASWELL_CONFIG_TDP_LEVEL2            0x0000064A

 

@@ -762,6 +776,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);

   AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.

 **/

 #define MSR_HASWELL_CONFIG_TDP_CONTROL           0x0000064B

 

@@ -812,6 +827,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);

   AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.

 **/

 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO       0x0000064C

 

@@ -861,6 +877,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);

   AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);

   @endcode

+  @note MSR_HASWELL_IA32_DEBUG_FEATURE is defined as IA32_DEBUG_FEATURE in SDM.

 **/

 #define MSR_HASWELL_IA32_DEBUG_FEATURE           0x00000C80

 

@@ -883,6 +900,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);

   AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

 **/

 #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL       0x000000E2

 

@@ -962,6 +980,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);

   AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.

 **/

 #define MSR_HASWELL_SMM_MCA_CAP                  0x0000017D

 

@@ -1012,6 +1031,7 @@ typedef union {
 

   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);

   @endcode

+  @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

 **/

 #define MSR_HASWELL_TURBO_RATIO_LIMIT            0x000001AD

 

@@ -1072,6 +1092,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);

   AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.

 **/

 #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL         0x00000391

 

@@ -1142,6 +1163,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);

   AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.

 **/

 #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS       0x00000392

 

@@ -1196,6 +1218,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);

   AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.

 **/

 #define MSR_HASWELL_UNC_PERF_FIXED_CTRL          0x00000394

 

@@ -1247,6 +1270,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);

   AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.

 **/

 #define MSR_HASWELL_UNC_PERF_FIXED_CTR           0x00000395

 

@@ -1290,6 +1314,7 @@ typedef union {
 

   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_CONFIG               0x00000396

 

@@ -1333,6 +1358,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.

 **/

 #define MSR_HASWELL_UNC_ARB_PERFCTR0             0x000003B0

 

@@ -1351,6 +1377,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.

 **/

 #define MSR_HASWELL_UNC_ARB_PERFCTR1             0x000003B1

 

@@ -1369,6 +1396,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.

 **/

 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0          0x000003B2

 

@@ -1387,6 +1415,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.

 **/

 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1          0x000003B3

 

@@ -1408,6 +1437,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);

   AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.

 **/

 #define MSR_HASWELL_SMM_FEATURE_CONTROL          0x000004E0

 

@@ -1481,6 +1511,7 @@ typedef union {
 

   Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);

   @endcode

+  @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.

 **/

 #define MSR_HASWELL_SMM_DELAYED                  0x000004E2

 

@@ -1514,6 +1545,7 @@ typedef union {
 

   Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);

   @endcode

+  @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.

 **/

 #define MSR_HASWELL_SMM_BLOCKED                  0x000004E3

 

@@ -1533,6 +1565,7 @@ typedef union {
 

   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);

   @endcode

+  @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.

 **/

 #define MSR_HASWELL_RAPL_POWER_UNIT              0x00000606

 

@@ -1591,6 +1624,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);

   AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);

   @endcode

+  @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.

 **/

 #define MSR_HASWELL_PP1_POWER_LIMIT              0x00000640

 

@@ -1609,6 +1643,7 @@ typedef union {
 

   Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);

   @endcode

+  @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.

 **/

 #define MSR_HASWELL_PP1_ENERGY_STATUS            0x00000641

 

@@ -1628,6 +1663,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);

   AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);

   @endcode

+  @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.

 **/

 #define MSR_HASWELL_PP1_POLICY                   0x00000642

 

@@ -1649,6 +1685,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);

   AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.

 **/

 #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS      0x00000690

 

@@ -1831,6 +1868,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);

   AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.

 **/

 #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS  0x000006B0

 

@@ -2002,6 +2040,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);

   AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.

 **/

 #define MSR_HASWELL_RING_PERF_LIMIT_REASONS      0x000006B1

 

@@ -2152,6 +2191,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0        0x00000700

 

@@ -2170,6 +2210,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1        0x00000701

 

@@ -2188,6 +2229,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_0_PERFCTR0           0x00000706

 

@@ -2206,6 +2248,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_0_PERFCTR1           0x00000707

 

@@ -2224,6 +2267,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0        0x00000710

 

@@ -2242,6 +2286,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1        0x00000711

 

@@ -2260,6 +2305,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_1_PERFCTR0           0x00000716

 

@@ -2278,6 +2324,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_1_PERFCTR1           0x00000717

 

@@ -2296,6 +2343,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0        0x00000720

 

@@ -2314,6 +2362,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1        0x00000721

 

@@ -2332,6 +2381,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_2_PERFCTR0           0x00000726

 

@@ -2350,6 +2400,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_2_PERFCTR1           0x00000727

 

@@ -2368,6 +2419,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0        0x00000730

 

@@ -2386,6 +2438,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1        0x00000731

 

@@ -2404,6 +2457,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_3_PERFCTR0           0x00000736

 

@@ -2422,6 +2476,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);

   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);

   @endcode

+  @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.

 **/

 #define MSR_HASWELL_UNC_CBO_3_PERFCTR1           0x00000737

 

@@ -2443,6 +2498,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);

   AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.

 **/

 #define MSR_HASWELL_PKG_C8_RESIDENCY             0x00000630

 

@@ -2492,6 +2548,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);

   AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.

 **/

 #define MSR_HASWELL_PKG_C9_RESIDENCY             0x00000631

 

@@ -2541,6 +2598,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);

   AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);

   @endcode

+  @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.

 **/

 #define MSR_HASWELL_PKG_C10_RESIDENCY            0x00000632