diff options
| author | rsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524> | 2012-04-11 01:41:29 +0000 |
|---|---|---|
| committer | rsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524> | 2012-04-11 01:41:29 +0000 |
| commit | 0779e5bfb0df775cbe02924ef9db4bd58f871ed5 (patch) | |
| tree | f6204c2cd99d83ce4d46459c806150397bf71398 /UefiCpuPkg | |
| parent | 48604ef952b5470dd38656b97ac081e3e917fc5e (diff) | |
| download | edk2-platforms-0779e5bfb0df775cbe02924ef9db4bd58f871ed5.tar.xz | |
UefiCpuPkg MtrrLib: For MtrrSetAllMtrrs(), do not set FE/E bits in IA32_MTRR_DEF_TYPE MSR after the MSR is restored.
Signed-off-by: Sun Rui <rui.sun@intel.com>
Reviewed-by: Fan Jeff <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13182 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 38 |
1 files changed, 27 insertions, 11 deletions
diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index bcf5e20459..b598d51b4b 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -1,7 +1,7 @@ /** @file
MTRR setting library
- Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -203,27 +203,21 @@ PreMtrrChange ( return Value;
}
-
/**
Cleaning up after programming MTRRs.
This function will do some clean up after programming MTRRs:
- enable MTRR caching functionality, and enable cache
+ Flush all TLBs, re-enable caching, restore CR4.
@param Cr4 CR4 value to restore
**/
VOID
-PostMtrrChange (
- UINTN Cr4
+PostMtrrChangeEnableCache (
+ IN UINTN Cr4
)
{
//
- // Enable Cache MTRR
- //
- AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 3);
-
- //
// Flush all TLBs
//
CpuFlushTlb ();
@@ -239,6 +233,28 @@ PostMtrrChange ( AsmWriteCr4 (Cr4);
}
+/**
+ Cleaning up after programming MTRRs.
+
+ This function will do some clean up after programming MTRRs:
+ enable MTRR caching functionality, and enable cache
+
+ @param Cr4 CR4 value to restore
+
+**/
+VOID
+PostMtrrChange (
+ IN UINTN Cr4
+ )
+{
+ //
+ // Enable Cache MTRR
+ //
+ AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 3);
+
+ PostMtrrChangeEnableCache (Cr4);
+}
+
/**
Programs fixed MTRRs registers.
@@ -1502,7 +1518,7 @@ MtrrSetAllMtrrs ( //
AsmWriteMsr64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, MtrrSetting->MtrrDefType);
- PostMtrrChange (Cr4);
+ PostMtrrChangeEnableCache (Cr4);
return MtrrSetting;
}
|