diff options
| author | Tim He <tim.he@intel.com> | 2015-08-04 02:55:02 +0000 |
|---|---|---|
| committer | timhe <timhe@Edk2> | 2015-08-04 02:55:02 +0000 |
| commit | 6f2ef18e8097c4fa11dd6ff5fdd0152c2c61ffc5 (patch) | |
| tree | bcc19b4b8196f40d7fb8cb6509ab4859503b009f /Vlv2TbltDevicePkg/PlatformPei | |
| parent | c5d5379937629f3061d08b8d9a3386a40152ca2c (diff) | |
| download | edk2-platforms-6f2ef18e8097c4fa11dd6ff5fdd0152c2c61ffc5.tar.xz | |
Vlv2TbltDevicePkg: Sync the branch changes to trunk.
Support compatible board, and fixed some bugs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tim He <tim.he@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18149 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'Vlv2TbltDevicePkg/PlatformPei')
| -rw-r--r-- | Vlv2TbltDevicePkg/PlatformPei/Platform.c | 64 |
1 files changed, 61 insertions, 3 deletions
diff --git a/Vlv2TbltDevicePkg/PlatformPei/Platform.c b/Vlv2TbltDevicePkg/PlatformPei/Platform.c index 23be887ca4..ec5e4b3458 100644 --- a/Vlv2TbltDevicePkg/PlatformPei/Platform.c +++ b/Vlv2TbltDevicePkg/PlatformPei/Platform.c @@ -192,6 +192,57 @@ PeiSmbusExec ( );
+/**
+
+ Detemine compatible board
+ @return 0: Not compatible board
+ 1: Compatible board
+
+**/
+UINT32
+DetermineCompatibleBoard (
+ void
+ )
+{
+ UINTN PciD31F0RegBase = 0;
+ UINT32 GpioValue = 0;
+ UINT32 TmpVal = 0;
+ UINT32 MmioConf0 = 0;
+ UINT32 MmioPadval = 0;
+ UINT32 PConf0Offset = 0x200; //GPIO_S5_4 pad_conf0 register offset
+ UINT32 PValueOffset = 0x208; //GPIO_S5_4 pad_value register offset
+ UINT32 SSUSOffset = 0x2000;
+ UINT32 IoBase = 0;
+
+ DEBUG ((EFI_D_ERROR, "DetermineCompatibleBoard() Entry\n"));
+ PciD31F0RegBase = MmPciAddress (0,
+ 0,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ 0
+ );
+ IoBase = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;
+
+ MmioConf0 = IoBase + SSUSOffset + PConf0Offset;
+ MmioPadval = IoBase + SSUSOffset + PValueOffset;
+ //0xFED0E200/0xFED0E208 is pad_Conf/pad_val register address of GPIO_S5_4
+ DEBUG ((EFI_D_ERROR, "MmioConf0[0x%x], MmioPadval[0x%x]\n", MmioConf0, MmioPadval));
+
+ MmioWrite32 (MmioConf0, 0x2003CC00);
+
+ TmpVal = MmioRead32 (MmioPadval);
+ TmpVal &= ~0x6; //Clear bit 1:2
+ TmpVal |= 0x2; // Set the pin as GPI
+ MmioWrite32 (MmioPadval, TmpVal);
+
+ GpioValue = MmioRead32 (MmioPadval);
+
+ DEBUG ((EFI_D_ERROR, "Gpio_S5_4 value is 0x%x\n", GpioValue));
+ return (GpioValue & 0x1);
+}
+
+
+
EFI_STATUS
FtpmPolicyInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
@@ -854,6 +905,7 @@ ReadPlatformIds ( UINTN DataSize;
EFI_PLATFORM_INFO_HOB TmpHob;
EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;
+ UINT32 CompatibleBoard = 0;
Status = (**PeiServices).LocatePpi (
PeiServices,
@@ -882,9 +934,15 @@ ReadPlatformIds ( return Status;
}
-
- PlatformInfoHob->BoardId = BOARD_ID_MINNOW2;
- DEBUG ((EFI_D_INFO, "I'm Minnow2!\n"));
+ CompatibleBoard = DetermineCompatibleBoard();
+ if (1 == CompatibleBoard) {
+ PlatformInfoHob->BoardId = BOARD_ID_MINNOW2_COMPATIBLE;
+ DEBUG ((EFI_D_INFO, "I'm MinnowBoard Compatible!\n"));
+ } else {
+ PlatformInfoHob->BoardId = BOARD_ID_MINNOW2;
+ DEBUG ((EFI_D_INFO, "I'm MinnowBoard Max!\n"));
+ }
+
PlatformInfoHob->MemCfgID = 0;
PlatformInfoHob->BoardRev = FabId + 1; // FabId = 0 means FAB1 (BoardRev = 1), FabId = 1 means FAB2 (BoardRev = 2)...
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