diff options
7 files changed, 951 insertions, 0 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInit.c new file mode 100644 index 0000000000..bb82d4e2dc --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInit.c @@ -0,0 +1,184 @@ +/** @file
+ Board Init driver.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Guid/PlatformInfo_Aplk.h>
+#include <Ppi/BoardInitSignalling.h>
+#include "BoardInit.h"
+#include "PlatformId.h"
+#include "BoardInitMiscs.h"
+
+EFI_STATUS
+EFIAPI
+MinnowBoard3PreMemInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BOARD_PRE_MEM_INIT_PPI *This
+ );
+
+static PEI_BOARD_PRE_MEM_INIT_PPI mPreMemInitPpiInstance = {
+ MinnowBoard3PreMemInit
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3PreMemInitPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardPreMemInitPpiGuid,
+ &mPreMemInitPpiInstance
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3PreMemInitDonePpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardPreMemInitDoneGuid,
+ NULL
+};
+
+EFI_STATUS
+EFIAPI
+MinnowBoard3PreMemInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BOARD_PRE_MEM_INIT_PPI *This
+ )
+{
+ EFI_STATUS Status;
+ VOID *Instance;
+ UINT8 BoardId;
+ UINT8 FabId;
+
+ BoardId = 0;
+ FabId = 0;
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitDoneGuid,
+ 0,
+ NULL,
+ &Instance
+ );
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO, "Minnow Board 3 Pre Mem Init: Skip\n"));
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((EFI_D_INFO, "Minnow Board 3 Pre Mem Init\n"));
+
+ //
+ // Pre Mem Board Init
+ //
+ Status = GetEmbeddedBoardIdFabId (PeiServices, &BoardId, &FabId);
+
+ if (BoardId != (UINT8) BOARD_ID_MINNOW) {
+ DEBUG ((EFI_D_INFO, "Not a Minnow Board - skip\n"));
+ return EFI_SUCCESS;
+ }
+
+ PcdSet8 (PcdBoardId, BoardId);
+ PcdSet8 (PcdFabId, FabId);
+
+ //
+ // Set board specific function as dynamic PCD to be called by common platform code
+ //
+ PcdSet64 (PcdUpdateFspmUpdFunc, (UINT64) (UINTN) mMb3UpdateFspmUpdPtr);
+ PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) mMb3DramCreatePolicyDefaultsPtr);
+
+ //
+ // Install a flag signalling a board is detected and pre-mem init is done
+ //
+ Status = PeiServicesInstallPpi (&mMinnowBoard3PreMemInitDonePpi);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function performs Board initialization in Pre-Memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory).
+
+**/
+EFI_STATUS
+EFIAPI
+MinnowBoard3InitConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *Ppi;
+ EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor;
+ UINTN Instance;
+
+ DEBUG ((EFI_D_INFO, "MinnowBoard3 Pre Mem Init Constructor \n"));
+
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitDoneGuid,
+ 0,
+ &PeiPpiDescriptor,
+ &Ppi
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // Board detection previously done, so this is a re-invocation shadowed in memory.
+ // Reinstall PPIs to eliminate PPI descriptors in torn down temp RAM.
+ //
+ //
+ // Reinstall PreMemInit Done PPI
+ //
+ DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init Done PPI\n"));
+ Status = PeiServicesReInstallPpi (
+ PeiPpiDescriptor,
+ &mMinnowBoard3PreMemInitDonePpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Reinstall all instances of Pre Mem Init PPIs.
+ // These PPIs are no longer used so it doesn't matter which board's instance is finally installed.
+ // According to PeiServicesReInstallPpi behavior:
+ // The first run of this loop would replace all descrioptors with a singe in-RAM descriptor;
+ // Subsequent runs of this loop will only replace the first (already in-RAM) descriptor.
+ // As long as all descriptors are in ram, we are fine.
+ //
+ Instance = 0;
+ do {
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitPpiGuid,
+ Instance,
+ &PeiPpiDescriptor,
+ &Ppi
+ );
+ if (Status == EFI_NOT_FOUND) {
+ break;
+ }
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init PPI\n"));
+ Status = PeiServicesReInstallPpi (
+ PeiPpiDescriptor,
+ &mMinnowBoard3PreMemInitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Instance++;
+ } while (TRUE);
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO, "Install Pre Mem Init PPI \n"));
+ Status = PeiServicesInstallPpi (&mMinnowBoard3PreMemInitPpi);
+ return Status;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInit.h new file mode 100644 index 0000000000..373b203127 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInit.h @@ -0,0 +1,29 @@ +/** @file
+ GPIO setting for CherryView.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BOARDINIT_H_
+#define _BOARDINIT_H_
+
+#include <PiPei.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/Timerlib.h>
+#include <Guid/PlatformInfo_Aplk.h>
+
+VOID GpioTest (VOID);
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c new file mode 100644 index 0000000000..edf6147b18 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c @@ -0,0 +1,274 @@ +/** @file
+ This file does Multiplatform initialization.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInitMiscs.h"
+
+UPDATE_FSPM_UPD_FUNC mMb3UpdateFspmUpdPtr = Mb3UpdateFspmUpd;
+DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3DramCreatePolicyDefaultsPtr = Mb3DramCreatePolicyDefaults;
+
+EFI_STATUS
+EFIAPI
+Mb3UpdateFspmUpd (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN FSPM_UPD *FspUpdRgn
+ )
+{
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL;
+ DRAM_POLICY_PPI *DramPolicy;
+ EFI_STATUS Status;
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gDramPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &DramPolicy
+ );
+
+ if (!EFI_ERROR (Status)) {
+ FspUpdRgn->FspmConfig.Package = DramPolicy->Package;
+ FspUpdRgn->FspmConfig.Profile = DramPolicy->Profile;
+ FspUpdRgn->FspmConfig.MemoryDown = DramPolicy->MemoryDown;
+ FspUpdRgn->FspmConfig.DDR3LPageSize = DramPolicy->DDR3LPageSize;
+ FspUpdRgn->FspmConfig.DDR3LASR = DramPolicy->DDR3LASR;
+ FspUpdRgn->FspmConfig.MemorySizeLimit = DramPolicy->SystemMemorySizeLimit;
+ FspUpdRgn->FspmConfig.DIMM0SPDAddress = DramPolicy->SpdAddress[0];
+ FspUpdRgn->FspmConfig.DIMM1SPDAddress = DramPolicy->SpdAddress[1];
+ FspUpdRgn->FspmConfig.DDR3LPageSize = DramPolicy->DDR3LPageSize;
+ FspUpdRgn->FspmConfig.DDR3LASR = DramPolicy->DDR3LASR;
+ FspUpdRgn->FspmConfig.HighMemoryMaxValue = DramPolicy->HighMemMaxVal;
+ FspUpdRgn->FspmConfig.LowMemoryMaxValue = DramPolicy->LowMemMaxVal;
+ FspUpdRgn->FspmConfig.DisableFastBoot = DramPolicy->DisableFastBoot;
+ FspUpdRgn->FspmConfig.RmtMode = DramPolicy->RmtMode;
+ FspUpdRgn->FspmConfig.RmtCheckRun = DramPolicy->RmtCheckRun;
+ FspUpdRgn->FspmConfig.RmtMarginCheckScaleHighThreshold = DramPolicy->RmtMarginCheckScaleHighThreshold;
+ FspUpdRgn->FspmConfig.MsgLevelMask = DramPolicy->MsgLevelMask;
+
+ FspUpdRgn->FspmConfig.ChannelHashMask = DramPolicy->ChannelHashMask;
+ FspUpdRgn->FspmConfig.SliceHashMask = DramPolicy->SliceHashMask;
+ FspUpdRgn->FspmConfig.ChannelsSlicesEnable = DramPolicy->ChannelsSlicesEnabled;
+ FspUpdRgn->FspmConfig.ScramblerSupport = DramPolicy->ScramblerSupport;
+ FspUpdRgn->FspmConfig.InterleavedMode = DramPolicy->InterleavedMode;
+ FspUpdRgn->FspmConfig.MinRefRate2xEnable = DramPolicy->MinRefRate2xEnabled;
+ FspUpdRgn->FspmConfig.DualRankSupportEnable = DramPolicy->DualRankSupportEnabled;
+ FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr;
+ FspUpdRgn->FspmConfig.MrcBootDataPtr = (VOID *)(UINT32)DramPolicy->MrcBootDataPtr;
+
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof(DramPolicy->ChDrp));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));
+ }
+ //
+ // override RankEnable settings for Minnow
+ //
+ FspUpdRgn->FspmConfig.Ch0_RankEnable = 1;
+ FspUpdRgn->FspmConfig.Ch1_RankEnable = 1;
+ FspUpdRgn->FspmConfig.Ch2_RankEnable = 1;
+ FspUpdRgn->FspmConfig.Ch3_RankEnable = 1;
+
+ DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));
+ Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (Hob.Raw != NULL);
+ PlatformInfo = GET_GUID_HOB_DATA (Hob.Raw);
+
+ DEBUG ((DEBUG_INFO, "**** MBv3 - UpdateFspmUpd,BoardId = %d\n", PlatformInfo->BoardId));
+ if (PlatformInfo->BoardId != BOARD_ID_MINNOW) {
+ //
+ // ASSERT false if BoardId isn't Minnow
+ //
+ ASSERT (FALSE);
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ DramCreatePolicyDefaults creates the default setting of Dram Policy.
+
+ @param[out] DramPolicyPpi The pointer to get Dram Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+Mb3DramCreatePolicyDefaults (
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi,
+ OUT DRAM_POLICY_PPI **DramPolicyPpi,
+ IN IAFWDramConfig *DramConfigData,
+ IN UINTN *MrcTrainingDataAddr,
+ IN UINTN *MrcBootDataAddr,
+ IN UINT8 BoardId
+ )
+{
+ DRAM_POLICY_PPI *DramPolicy;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ UINTN VariableSize;
+ EFI_STATUS Status;
+ DRP_DRAM_POLICY *DrpPtr;
+ UINT8 (*ChSwizlePtr)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
+ PlatfromDramConf *DramConfig;
+ BOOLEAN ReadSetupVars;
+ EFI_PLATFORM_INFO_HOB *PlatformInfoHob = NULL;
+ EFI_PEI_HOB_POINTERS Hob;
+
+ DEBUG ((EFI_D_INFO, "*** Minnow Board 3 DramCreatePolicyDefaults\n"));
+ DramPolicy = (DRAM_POLICY_PPI *) AllocateZeroPool (sizeof (DRAM_POLICY_PPI));
+ if (DramPolicy == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ReadSetupVars = FALSE;
+ DrpPtr = NULL;
+ ChSwizlePtr = NULL;
+ DramConfig = NULL;
+
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+
+#if !(ONLY_USE_SMIP_DRAM_POLICY == 1)
+ Status = EFI_UNSUPPORTED;
+#endif
+
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO, "Using setup options data for DRAM policy\n"));
+ ReadSetupVars = TRUE;
+ DramPolicy->ChannelHashMask = SystemConfiguration.ChannelHashMask;
+ DramPolicy->SliceHashMask = SystemConfiguration.SliceHashMask;
+ DramPolicy->ChannelsSlicesEnabled = SystemConfiguration.ChannelsSlicesEnabled;
+ DramPolicy->ScramblerSupport = SystemConfiguration.ScramblerSupport;
+ DramPolicy->InterleavedMode = SystemConfiguration.InterleavedMode;
+ DramPolicy->MinRefRate2xEnabled = SystemConfiguration.MinRefRate2xEnabled;
+ DramPolicy->DualRankSupportEnabled = SystemConfiguration.DualRankSupportEnabled;
+ }
+
+ DramConfig = &(DramConfigData->PlatformDram4);
+
+ DEBUG ((EFI_D_INFO, "Using smip platform override: %d\n", DramConfigData->Platform_override));
+ switch (DramConfigData->Platform_override) {
+ case 0:
+ DramConfig = &(DramConfigData->PlatformDram0);
+ break;
+ case 1:
+ DramConfig = &(DramConfigData->PlatformDram1);
+ break;
+ case 2:
+ DramConfig = &(DramConfigData->PlatformDram2);
+ break;
+ case 3:
+ DramConfig = &(DramConfigData->PlatformDram3);
+ break;
+ case 4:
+ DramConfig = &(DramConfigData->PlatformDram4);
+ break;
+ default:
+ //
+ // Do nothing if the override value does not exist. 0xFF is the
+ // default Platform_override value when no override is selected
+ //
+ break;
+ }
+
+ DramPolicy->Package = DramConfig->Package;
+ DramPolicy->Profile = DramConfig->Profile;
+ DramPolicy->MemoryDown = DramConfig->MemoryDown;
+ DramPolicy->DDR3LPageSize = DramConfig->DDR3LPageSize;
+ DramPolicy->DDR3LASR = DramConfig->DDR3LASR;
+ DramPolicy->SystemMemorySizeLimit = DramConfig->MemorySizeLimit;
+ DramPolicy->SpdAddress[0] = DramConfig->SpdAddress0;
+ DramPolicy->SpdAddress[1] = DramConfig->SpdAddress1;
+ DramPolicy->DDR3LPageSize = DramConfig->DDR3LPageSize;
+ DramPolicy->DDR3LASR = DramConfig->DDR3LASR;
+ DramPolicy->HighMemMaxVal = DramConfig->HighMemMaxVal;
+ DramPolicy->LowMemMaxVal = DramConfig->LowMemMaxVal;
+ DramPolicy->DisableFastBoot = DramConfig->DisableFastBoot;
+ DramPolicy->RmtMode = DramConfig->RmtMode;
+ DramPolicy->RmtCheckRun = DramConfig->RmtCheckRun;
+ DramPolicy->RmtMarginCheckScaleHighThreshold = DramConfig->RmtMarginCheckScaleHighThreshold;
+
+ DramPolicy->MsgLevelMask = DramConfigData->Message_level_mask;
+ DrpPtr = (DRP_DRAM_POLICY *) (&(DramConfig->Ch0RankEnabled));
+ ChSwizlePtr = (UINT8(*)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]) (&(DramConfig->Ch0_Bit00_swizzling));
+
+ if (!ReadSetupVars) {
+ DEBUG ((EFI_D_INFO, "Using smip data for DRAM policy\n"));
+ DramPolicy->ChannelHashMask = DramConfig->ChannelHashMask;
+ DramPolicy->SliceHashMask = DramConfig->SliceHashMask;
+ DramPolicy->ChannelsSlicesEnabled = DramConfig->ChannelsSlicesEnabled;
+ DramPolicy->ScramblerSupport = DramConfig->ScramblerSupport;
+ DramPolicy->InterleavedMode = DramConfig->InterleavedMode;
+ DramPolicy->MinRefRate2xEnabled = DramConfig->MinRefRate2xEnabled;
+ DramPolicy->DualRankSupportEnabled = DramConfig->DualRankSupportEnabled;
+}
+
+ if (DrpPtr != NULL) {
+ CopyMem (DramPolicy->ChDrp, DrpPtr, sizeof (DramPolicy->ChDrp));
+ }
+
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+
+ if (!EFI_ERROR (Status)) {
+ if (SystemConfiguration.Max2G == 0) {
+ DramPolicy->SystemMemorySizeLimit = 0x800;
+ }
+ }
+
+ if (ChSwizlePtr != NULL) CopyMem (DramPolicy->ChSwizzle, ChSwizlePtr, sizeof (DramPolicy->ChSwizzle));
+
+ DramPolicy->MrcTrainingDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcTrainingDataAddr;
+ DramPolicy->MrcBootDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcBootDataAddr;
+
+ //
+ // WA for MH board to 6GB. We just apply it if memory size has not been override in smip XML.
+ //
+ if (DramPolicy->SystemMemorySizeLimit == 0) {
+ DramPolicy->SystemMemorySizeLimit = 0x1800;
+ if ((DramPolicy->ChDrp[2].RankEnable == 0) && (DramPolicy->ChDrp[3].RankEnable == 0)) { //half config
+ DramPolicy->SystemMemorySizeLimit /= 2;
+ }
+ }
+
+ //
+ // Get Platform Info HOB
+ //
+ Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (Hob.Raw != NULL);
+ PlatformInfoHob = GET_GUID_HOB_DATA (Hob.Raw);
+
+ DEBUG ((EFI_D_INFO, "Minnow has single rank memory\n"));
+ DramPolicy->DualRankSupportEnabled = FALSE;
+
+ *DramPolicyPpi = DramPolicy;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.h new file mode 100644 index 0000000000..bb8c4aa967 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.h @@ -0,0 +1,46 @@ +/** @file
+ Multiplatform initialization header file.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MULTIPLATFORM_LIB_H_
+#define _MULTIPLATFORM_LIB_H_
+
+#include <BoardFunctionsPei.h>
+#include <Guid/SetupVariable.h>
+#include <Library/MemoryAllocationLib.h>
+
+extern UPDATE_FSPM_UPD_FUNC mMb3UpdateFspmUpdPtr;
+extern DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3DramCreatePolicyDefaultsPtr;
+
+EFI_STATUS
+EFIAPI
+Mb3UpdateFspmUpd (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN FSPM_UPD *FspUpdRgn
+ );
+
+EFI_STATUS
+EFIAPI
+Mb3DramCreatePolicyDefaults (
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi,
+ OUT DRAM_POLICY_PPI **DramPolicyPpi,
+ IN IAFWDramConfig *DramConfigData,
+ IN UINTN *MrcTrainingDataAddr,
+ IN UINTN *MrcBootDataAddr,
+ IN UINT8 BoardId
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf new file mode 100644 index 0000000000..81448e365b --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf @@ -0,0 +1,57 @@ +## @file
+# Board detected module for Intel(R) Atom(TM) x5 Processor Series.
+# It will detect the board ID.
+#
+# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = MinnowBoard3InitPreMem
+ FILE_GUID = 88F945EB-889A-4FD3-9444-F41734B0E9C1
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ CONSTRUCTOR = MinnowBoard3InitConstructor
+
+[Sources]
+ BoardInit.c
+ PlatformId.c
+ BoardInitMiscs.c
+
+[LibraryClasses]
+ PeiServicesLib
+ PcdLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BroxtonPlatformPkg/PlatformPkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+ BroxtonFspPkg/BroxtonFspPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdBoardId
+ gPlatformModuleTokenSpaceGuid.PcdFabId
+ gPlatformModuleTokenSpaceGuid.PcdUpdateFspmUpdFunc
+ gPlatformModuleTokenSpaceGuid.PcdDramCreatePolicyDefaultsFunc
+ gMinnowModuleTokenSpaceGuid.PcdDefaultFabId ## CONSUMES
+ gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetectionRun ## CONSUMES
+ gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetected ## CONSUMES
+
+[Guids]
+
+[Ppis]
+ gBoardPreMemInitPpiGuid
+ gBoardPreMemInitDoneGuid
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.c new file mode 100644 index 0000000000..e7135a9dc8 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.c @@ -0,0 +1,280 @@ +/** @file
+ Implement Platform ID code.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/I2CLib.h>
+#include <Library/GpioLib.h>
+#include <Guid/PlatformInfo.h>
+#include "PlatformId.h"
+
+/**
+ Read in GPIO state and return it.
+
+**/
+BOOLEAN
+IsThisMinnow (
+ VOID
+ )
+{
+ UINT32 CommAndOffset = NW_GPIO_215;
+ BXT_CONF_PAD0 PadConfg0;
+ BXT_CONF_PAD1 PadConfg1;
+ BOOLEAN ReturnValue;
+
+ if (PcdGetBool (PcdMinnowBoardDetectionRun)) {
+ //
+ // Already detected this. Return stored value.
+ //
+ ReturnValue = PcdGetBool (PcdMinnowBoardDetected);
+ DEBUG ((EFI_D_INFO, "Already detected. Returning stored value = %x\n", ReturnValue));
+ } else {
+ //
+ // Enable GPI mode with a pull-up
+ //
+ PadConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ PadConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+ PadConfg0.r.PMode = M0; // Set to GPIO mode
+ PadConfg0.r.GPIORxTxDis = GPI; // Set to GPI
+ PadConfg1.r.IOSTerm = EnPu; // Enable pull-up
+ PadConfg1.r.Term = P_20K_H; // Set to 20K pull-up
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, PadConfg0.padCnf0);
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, PadConfg1.padCnf1);
+
+ //
+ // Read in GPI state and set return value
+ //
+ PadConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ ReturnValue = (BOOLEAN) PadConfg0.r.GPIORxState;
+
+ //
+ // Set detection PCDs
+ //
+ PcdSetBoolS (PcdMinnowBoardDetectionRun, TRUE);
+ PcdSetBoolS (PcdMinnowBoardDetected, ReturnValue);
+ }
+
+ //
+ // Return answer
+ //
+ return ReturnValue;
+}
+
+
+EFI_STATUS
+EFIAPI
+GetEmbeddedBoardIdFabId(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId,
+ OUT UINT8 *FabId
+ )
+{
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ IN UINT32 CommAndOffset;
+
+ DEBUG ((DEBUG_INFO, "GetEmbeddedBoardIdFabId++\n"));
+
+ //
+ // Set BoardId & FabId
+ //
+ if (IsThisMinnow ()) {
+ //
+ // NW_PMIC_PWRGOOD says this is a Minnow board. Force Minnow defaults.
+ //
+ *BoardId = BOARD_ID_MINNOW;
+ *FabId = PcdGet8 (PcdDefaultFabId);
+
+ DEBUG ((EFI_D_INFO, "BoardId forced from NW_GPIO_215 detection: %02X\n", *BoardId));
+ DEBUG ((EFI_D_INFO, " FabId forced from NW_GPIO_215 detection: %02X\n", *FabId));
+ } else {
+ //
+ // Board_ID0: PMIC_STDBY
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00F0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0; // Set to GPIO mode
+ padConfg0.r.GPIORxTxDis = 0x1; // Set to GPI
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+ //
+ // Set to Pull Up 20K
+ //
+ padConfg1.r.Term = 0xC;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Board_ID1: PMIC_SDWN_B
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00D0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ //
+ // Board_ID2: PMIC_RESET_B
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00C8);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ //
+ // Board_ID3: PMIC_PWRGOOD
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00C0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ *BoardId = (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00F0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2));
+
+ DEBUG ((DEBUG_INFO, "BoardId from PMIC strap: %02X\n", *BoardId));
+
+ //
+ // Fab_ID0: PMIC_I2C_SDA
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x0108);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ //
+ // Set to Pull Up 20K
+ //
+ padConfg1.r.Term = 0xC;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Fab_ID1: PMIC_I2C_SCL
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x0100);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ //Set to Pull Up 20K
+ padConfg1.r.Term = 0xC;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Fab_ID2: PMIC_BCUDISW2
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00D8);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ //
+ // Set to Pull Up 20K
+ //
+ padConfg1.r.Term = 0xC;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Fab_ID3: PMIC_BCUDISCRIT
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00E0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ //
+ // Set to Pull Up 20K
+ //
+ padConfg1.r.Term = 0xC;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+
+ *FabId = (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0108) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0100) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00E0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3));
+
+ DEBUG ((EFI_D_INFO, "FabId from PMIC strap: %02X\n", *FabId));
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+GetIVIBoardIdFabId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId,
+ OUT UINT8 *FabId
+ )
+{
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ IN UINT32 CommAndOffset;
+
+ DEBUG ((DEBUG_INFO, "GetIVIBoardIdFabId++\n"));
+
+ //
+ // Board_ID0: GPIO_62
+ //
+ CommAndOffset = GetCommOffset (NORTH, 0x0190);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+ padConfg1.r.IOSTerm = 0x3; //Enable Pullup
+ padConfg1.r.Term = 0xC; //20k wpu
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Board_ID1: GPIO_63
+ //
+ CommAndOffset = GetCommOffset (NORTH, 0x0198);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+ padConfg1.r.IOSTerm = 0x3; //Enable Pullup
+ padConfg1.r.Term = 0xC; //20k wpu
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Board_ID2: GPIO_64
+ //
+ CommAndOffset = GetCommOffset (NORTH, 0x01A0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+ padConfg1.r.IOSTerm = 0x3; //Enable Pullup
+ padConfg1.r.Term = 0xC; //20k wpu
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Board_ID3: GPIO_65
+ //
+ CommAndOffset = GetCommOffset (NORTH, 0x01A8);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+ padConfg1.r.IOSTerm = 0x3; //Enable Pullup
+ padConfg1.r.Term = 0xC; //20k wpu
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+
+ *BoardId = (UINT8) (((GpioPadRead (GetCommOffset (NORTH, 0x0190) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \
+ (((GpioPadRead (GetCommOffset (NORTH, 0x0198) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \
+ (((GpioPadRead (GetCommOffset (NORTH, 0x01A0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \
+ (((GpioPadRead (GetCommOffset (NORTH, 0x01A8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3));
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.h new file mode 100644 index 0000000000..3999aaa726 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/PlatformId.h @@ -0,0 +1,81 @@ +/** @file
+ Header file for the Platform ID code.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PLATFORM_ID_H__
+#define __PLATFORM_ID_H__
+
+//
+// Strap Fw Cfg ID define
+//
+#define IO_EXPANDER_I2C_BUS_NO 0x06
+#define IO_EXPANDER_SLAVE_ADDR 0x22
+#define IO_EXPANDER_INPUT_REG_0 0x00
+#define IO_EXPANDER_INPUT_REG_1 0x01
+#define IO_EXPANDER_INPUT_REG_2 0x02
+
+EFI_STATUS
+EFIAPI
+GetFwCfgId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *FwCfgId
+ );
+
+EFI_STATUS
+EFIAPI
+GetBoardIdFabId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId,
+ OUT UINT8 *FabId
+ );
+
+EFI_STATUS
+EFIAPI
+GetEmbeddedBoardIdFabId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId,
+ OUT UINT8 *FabId
+ );
+
+EFI_STATUS
+EFIAPI
+GetIVIBoardIdFabId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId,
+ OUT UINT8 *FabId
+ );
+
+EFI_STATUS
+EFIAPI
+GetDockId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *DockId
+ );
+
+EFI_STATUS
+EFIAPI
+GetOsSelPss (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *OsSelPss
+ );
+
+EFI_STATUS
+EFIAPI
+GetBomIdPss (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BomIdPss
+ );
+
+#endif
+
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