diff options
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 13 | ||||
| -rw-r--r-- | ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S | 3 | ||||
| -rw-r--r-- | ArmPlatformPkg/Sec/AArch64/Helper.S | 6 |
3 files changed, 10 insertions, 12 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index a57e976979..76007505f3 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -146,7 +146,7 @@ ASM_PFX(ArmDisableMmu): 2: mrs x0, sctlr_el2 // Read System Control Register EL2
b 4f
3: mrs x0, sctlr_el3 // Read System Control Register EL3
-4: bic x0, x0, #CTRL_M_BIT // Clear MMU enable bit
+4: and x0, x0, #~CTRL_M_BIT // Clear MMU enable bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back
tlbi vmalle1
@@ -168,9 +168,8 @@ ASM_PFX(ArmDisableCachesAndMmu): 2: mrs x0, sctlr_el2 // Get control register EL2
b 4f
3: mrs x0, sctlr_el3 // Get control register EL3
-4: bic x0, x0, #CTRL_M_BIT // Disable MMU
- bic x0, x0, #CTRL_C_BIT // Disable D Cache
- bic x0, x0, #CTRL_I_BIT // Disable I Cache
+4: mov x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT) // Disable MMU, D & I caches
+ and x0, x0, x1
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back control register
b 4f
@@ -219,7 +218,7 @@ ASM_PFX(ArmDisableDataCache): 2: mrs x0, sctlr_el2 // Get control register EL2
b 4f
3: mrs x0, sctlr_el3 // Get control register EL3
-4: bic x0, x0, #CTRL_C_BIT // Clear C bit
+4: and x0, x0, #~CTRL_C_BIT // Clear C bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back control register
b 4f
@@ -257,7 +256,7 @@ ASM_PFX(ArmDisableInstructionCache): 2: mrs x0, sctlr_el2 // Get control register EL2
b 4f
3: mrs x0, sctlr_el3 // Get control register EL3
-4: bic x0, x0, #CTRL_I_BIT // Clear I bit
+4: and x0, x0, #~CTRL_I_BIT // Clear I bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back control register
b 4f
@@ -291,7 +290,7 @@ ASM_PFX(ArmDisableAlignmentCheck): 2: mrs x0, sctlr_el2 // Get control register EL2
b 4f
3: mrs x0, sctlr_el3 // Get control register EL3
-4: bic x0, x0, #CTRL_A_BIT // Clear A (alignment check) bit
+4: and x0, x0, #~CTRL_A_BIT // Clear A (alignment check) bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back control register
b 4f
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S index 7d9c25c769..035e095493 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S @@ -12,6 +12,7 @@ //
#include <AsmMacroIoLibV8.h>
+#include <Chipset/AArch64.h>
#ifndef __clang__
// Register definitions used by GCC for GICv3 access.
@@ -64,6 +65,6 @@ ASM_PFX(InitializeGicV3): // Remove the SCR.NS bit
mrs x0, scr_el3
- bic x0, x0, #1
+ and x0, x0, #~SCR_NS
msr scr_el3, x0
ret
diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S index 259aca4856..3b58e12292 100644 --- a/ArmPlatformPkg/Sec/AArch64/Helper.S +++ b/ArmPlatformPkg/Sec/AArch64/Helper.S @@ -1,5 +1,5 @@ #========================================================================================
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -31,9 +31,7 @@ ASM_PFX(SwitchToNSExceptionLevel1): orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
// Send all interrupts to their respective Exception levels for EL2
- bic x0, x0, #(1 << 3) // Disable virtual FIQ
- bic x0, x0, #(1 << 4) // Disable virtual IRQ
- bic x0, x0, #(1 << 5) // Disable virtual SError and Abort
+ and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort
msr hcr_el2, x0 // Write back our settings
msr cptr_el2, xzr // Disable copro traps to EL2
|