diff options
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c | 7 | ||||
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c | 9 | ||||
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c | 2 | ||||
| -rw-r--r-- | OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c | 2 | ||||
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 6 |
5 files changed, 12 insertions, 14 deletions
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c index c20f299304..490cf803be 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -22,7 +22,6 @@ // Power Management PCI Configuration Register fields
//
#define PMBA_RTE BIT0
-#define PIIX4_PMIOSE BIT0
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -58,9 +57,9 @@ AcpiTimerLibConstructor ( HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
- AcpiEnBit = PIIX4_PMIOSE;
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c index 55f3572eef..50a3391b75 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c @@ -23,7 +23,6 @@ // Power Management PCI Configuration Register fields
//
#define PMBA_RTE BIT0
-#define PIIX4_PMIOSE BIT0
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -56,9 +55,9 @@ AcpiTimerLibConstructor ( HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
- AcpiEnBit = PIIX4_PMIOSE;
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
@@ -114,7 +113,7 @@ InternalAcpiGetTimerTick ( HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c index 649b5c9a4d..0c42ed2c5c 100644 --- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c @@ -61,7 +61,7 @@ AcpiTimerLibConstructor ( HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
diff --git a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c index 2521ea4e6a..1eb2a8b91e 100644 --- a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c +++ b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c @@ -860,7 +860,7 @@ PciAcpiInitialization ( mHostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
switch (mHostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
//
// 00:01.0 ISA Bridge (PIIX4) LNK routing targets
//
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 4ce358ccbc..1126c6529a 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -252,9 +252,9 @@ MiscInitialization ( switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
- AcpiEnBit = BIT0; // PIIX4_PMIOSE
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
|