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-rw-r--r--ArmPkg/Drivers/PL35xSmc/InitializeSMC.S80
-rw-r--r--ArmPkg/Drivers/PL35xSmc/InitializeSMC.asm166
-rw-r--r--ArmPkg/Include/Drivers/PL354Smc.h57
-rw-r--r--ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S62
-rw-r--r--ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm32
5 files changed, 238 insertions, 159 deletions
diff --git a/ArmPkg/Drivers/PL35xSmc/InitializeSMC.S b/ArmPkg/Drivers/PL35xSmc/InitializeSMC.S
index b3b597a50c..108cd6ae65 100644
--- a/ArmPkg/Drivers/PL35xSmc/InitializeSMC.S
+++ b/ArmPkg/Drivers/PL35xSmc/InitializeSMC.S
@@ -14,7 +14,7 @@
#include <AsmMacroIoLib.h>
#include <Library/PcdLib.h>
#include <AutoGen.h>
-#include <AsmMacroIoLib.h>
+#include <Drivers/PL354Smc.h>
#Start of the code section
.text
@@ -22,13 +22,12 @@
#Maintain 8 byte alignment
.align 3
-#Export Initialize SMC symbol
-GCC_ASM_EXPORT(InitializeSMC)
-# Static memory configuation definitions for SMC
-.set SmcDirectCmd, 0x10
-.set SmcSetCycles, 0x14
-.set SmcSetOpMode, 0x18
+GCC_ASM_EXPORT(SMCInitializeNOR)
+GCC_ASM_EXPORT(SMCInitializeSRAM)
+GCC_ASM_EXPORT(SMCInitializePeripherals)
+GCC_ASM_EXPORT(SMCInitializeVRAM)
+
# CS0 CS0-Interf0 NOR1 flash on the motherboard
# CS1 CS1-Interf0 Reserved for the motherboard
@@ -39,125 +38,134 @@ GCC_ASM_EXPORT(InitializeSMC)
# CS6 CS2-Interf1 memory-mapped peripherals
# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
-# IN r1 SmcBase
-# IN r2 VideoSRamBase
-# NOTE: This code is been called before any stack has been setup. It means some registers
-# could be overwritten (case of 'r0')
-
-
-ASM_PFX(InitializeSMC):
+// IN r1 SmcBase
+// IN r2 ChipSelect
+// NOTE: This code is been called before any stack has been setup. It means some registers
+// could be overwritten (case of 'r0')
+ASM_PFX(SMCInitializeNOR):
#
# Setup NOR1 (CS0-Interface0)
#
- #Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
+ # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
#Read cycle timeout = 0xA (0:3)
#Write cycle timeout = 0x3(7:4)
#OE Assertion Delay = 0x9(11:8)
#WE Assertion delay = 0x3(15:12)
#Page cycle timeout = 0x2(19:16)
LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
- #Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
+ # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
# 0x00000002 = MemoryWidth: 32bit
# 0x00000028 = ReadMemoryBurstLength:continuous
# 0x00000280 = WriteMemoryBurstLength:continuous
# 0x00000800 = Set Address Valid
LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA
- str r0, [r1, #SmcSetOpMode]
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
- #Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
+ # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
# 0x00000000 = ChipSelect0-Interface 0
# 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000
- str r0, [r1, #SmcDirectCmd]
-
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
+ bx lr
+
+ASM_PFX(SMCInitializeSRAM):
#
# Setup SRAM (CS2-Interface0)
#
LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit
# 0x00000800 = Set Address Valid
LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802
- str r0, [r1, #SmcSetOpMode]
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x01000000 = ChipSelect2-Interface 0
# 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000
- str r0, [r1, #SmcDirectCmd]
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
+
+ bx lr
+ASM_PFX(SMCInitializePeripherals):
#
# USB/Eth/VRAM (CS3-Interface0)
#
LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit
# 0x00000004 = Memory reads are synchronous
# 0x00000040 = Memory writes are synchronous
LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
- str r0, [r1, #SmcSetOpMode]
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x01800000 = ChipSelect3-Interface 0
# 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000
- str r0, [r1, #SmcDirectCmd]
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
#
# Setup NOR3 (CS0-Interface1)
#
LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit
# 0x00000028 = ReadMemoryBurstLength:continuous
# 0x00000280 = WriteMemoryBurstLength:continuous
# 0x00000800 = Set Address Valid
LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA
- str r0, [r1, #SmcSetOpMode]
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x02000000 = ChipSelect0-Interface 1
# 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000
- str r0, [r1, #SmcDirectCmd]
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
#
# Setup Peripherals (CS3-Interface1)
#
LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit
# 0x00000004 = Memory reads are synchronous
# 0x00000040 = Memory writes are synchronous
LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
- str r0, [r1, #SmcSetOpMode]
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x03800000 = ChipSelect3-Interface 1
# 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000
- str r0, [r1, #SmcDirectCmd]
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
+ bx lr
+// IN r1 SmcBase
+// IN r2 VideoSRamBase
+// NOTE: This code is been called before any stack has been setup. It means some registers
+// could be overwritten (case of 'r0')
+ASM_PFX(SMCInitializeVRAM):
#
# Setup VRAM (CS1-Interface0)
#
LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit
# 0x00000004 = Memory reads are synchronous
# 0x00000040 = Memory writes are synchronous
LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
- str r0, [r1, #SmcSetOpMode]
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x00800000 = ChipSelect1-Interface 0
# 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000
- str r0, [r1, #SmcDirectCmd]
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
#
# Page mode setup for VRAM
diff --git a/ArmPkg/Drivers/PL35xSmc/InitializeSMC.asm b/ArmPkg/Drivers/PL35xSmc/InitializeSMC.asm
index ebf6a7980e..f868660336 100644
--- a/ArmPkg/Drivers/PL35xSmc/InitializeSMC.asm
+++ b/ArmPkg/Drivers/PL35xSmc/InitializeSMC.asm
@@ -13,20 +13,19 @@
#include <AsmMacroIoLib.h>
#include <Library/PcdLib.h>
+#include <Drivers/PL354Smc.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
- EXPORT InitializeSMC
+ EXPORT SMCInitializeNOR
+ EXPORT SMCInitializeSRAM
+ EXPORT SMCInitializePeripherals
+ EXPORT SMCInitializeVRAM
PRESERVE8
AREA ModuleInitializeSMC, CODE, READONLY
-// Static memory configuation definitions for SMC
-SmcDirectCmd EQU 0x10
-SmcSetCycles EQU 0x14
-SmcSetOpMode EQU 0x18
-
// CS0 CS0-Interf0 NOR1 flash on the motherboard
// CS1 CS1-Interf0 Reserved for the motherboard
// CS2 CS2-Interf0 SRAM on the motherboard
@@ -37,133 +36,104 @@ SmcSetOpMode EQU 0x18
// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
// IN r1 SmcBase
-// IN r2 VideoSRamBase
+// IN r2 ChipSelect
// NOTE: This code is been called before any stack has been setup. It means some registers
// could be overwritten (case of 'r0')
-InitializeSMC
-//
-// Setup NOR1 (CS0-Interface0)
-//
-
- //Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
- //Read cycle timeout = 0xA (0:3)
- //Write cycle timeout = 0x3(7:4)
- //OE Assertion Delay = 0x9(11:8)
- //WE Assertion delay = 0x3(15:12)
- //Page cycle timeout = 0x2(19:16)
+SMCInitializeNOR
+ // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
+ // - Read cycle timeout = 0xA (0:3)
+ // - Write cycle timeout = 0x3(7:4)
+ // - OE Assertion Delay = 0x9(11:8)
+ // - WE Assertion delay = 0x3(15:12)
+ // - Page cycle timeout = 0x2(19:16)
ldr r0, = 0x0002393A
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
- //Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
- // 0x00000002 = MemoryWidth: 32bit
- // 0x00000028 = ReadMemoryBurstLength:continuous
- // 0x00000280 = WriteMemoryBurstLength:continuous
- // 0x00000800 = Set Address Valid
- ldr r0, = 0x00000AAA
- str r0, [r1, #SmcSetOpMode]
-
- //Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
- // 0x00000000 = ChipSelect0-Interface 0
- // 0x00400000 = CmdTypes: UpdateRegs
- ldr r0, = 0x00400000
- str r0, [r1, #SmcDirectCmd]
+ // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
+ ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
+
+ // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
+ ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
+ orr r0, r0, r2
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
+ bx lr
+
+
//
// Setup SRAM (CS2-Interface0)
//
+SMCInitializeSRAM
ldr r0, = 0x00027158
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
- // 0x00000002 = MemoryWidth: 32bit
- // 0x00000800 = Set Address Valid
- ldr r0, = 0x00000802
- str r0, [r1, #SmcSetOpMode]
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
- // 0x01000000 = ChipSelect2-Interface 0
- // 0x00400000 = CmdTypes: UpdateRegs
- ldr r0, = 0x01400000
- str r0, [r1, #SmcDirectCmd]
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
+
+ bx lr
+SMCInitializePeripherals
//
// USB/Eth/VRAM (CS3-Interface0)
//
ldr r0, = 0x000CD2AA
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
- // 0x00000002 = MemoryWidth: 32bit
- // 0x00000004 = Memory reads are synchronous
- // 0x00000040 = Memory writes are synchronous
- ldr r0, = 0x00000046
- str r0, [r1, #SmcSetOpMode]
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
- // 0x01800000 = ChipSelect3-Interface 0
- // 0x00400000 = CmdTypes: UpdateRegs
- ldr r0, = 0x01C00000
- str r0, [r1, #SmcDirectCmd]
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
+
-//
-// Setup NOR3 (CS0-Interface1)
-//
- ldr r0, = 0x0002393A
- str r0, [r1, #SmcSetCycles]
-
- // 0x00000002 = MemoryWidth: 32bit
- // 0x00000028 = ReadMemoryBurstLength:continuous
- // 0x00000280 = WriteMemoryBurstLength:continuous
- // 0x00000800 = Set Address Valid
- ldr r0, = 0x00000AAA
- str r0, [r1, #SmcSetOpMode]
-
- // 0x02000000 = ChipSelect0-Interface 1
- // 0x00400000 = CmdTypes: UpdateRegs
- ldr r0, = 0x02400000
- str r0, [r1, #SmcDirectCmd]
-
//
// Setup Peripherals (CS3-Interface1)
//
ldr r0, = 0x00025156
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
- // 0x00000002 = MemoryWidth: 32bit
- // 0x00000004 = Memory reads are synchronous
- // 0x00000040 = Memory writes are synchronous
- ldr r0, = 0x00000046
- str r0, [r1, #SmcSetOpMode]
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
- // 0x03800000 = ChipSelect3-Interface 1
- // 0x00400000 = CmdTypes: UpdateRegs
- ldr r0, = 0x03C00000
- str r0, [r1, #SmcDirectCmd]
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-//
-// Setup VRAM (CS1-Interface0)
-//
+ bx lr
+
+
+// IN r1 SmcBase
+// IN r2 VideoSRamBase
+// NOTE: This code is been called before any stack has been setup. It means some registers
+// could be overwritten (case of 'r0')
+SMCInitializeVRAM
+ //
+ // Setup VRAM (CS1-Interface0)
+ //
ldr r0, = 0x00049249
- str r0, [r1, #SmcSetCycles]
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
- // 0x00000002 = MemoryWidth: 32bit
- // 0x00000004 = Memory reads are synchronous
- // 0x00000040 = Memory writes are synchronous
- ldr r0, = 0x00000046
- str r0, [r1, #SmcSetOpMode]
+ ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
- // 0x00800000 = ChipSelect1-Interface 0
- // 0x00400000 = CmdTypes: UpdateRegs
- ldr r0, = 0x00C00000
- str r0, [r1, #SmcDirectCmd]
+ ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-//
-// Page mode setup for VRAM
-//
- //read current state
+ //
+ // Page mode setup for VRAM
+ //
+
+ // Read current state
ldr r0, [r2, #0]
ldr r0, [r2, #0]
ldr r0, = 0x00000000
str r0, [r2, #0]
ldr r0, [r2, #0]
- //enable page mode
+ // Enable page mode
ldr r0, [r2, #0]
ldr r0, [r2, #0]
ldr r0, = 0x00000000
@@ -171,7 +141,7 @@ InitializeSMC
ldr r0, = 0x00900090
str r0, [r2, #0]
- //confirm page mode enabled
+ // Confirm page mode enabled
ldr r0, [r2, #0]
ldr r0, [r2, #0]
ldr r0, = 0x00000000
diff --git a/ArmPkg/Include/Drivers/PL354Smc.h b/ArmPkg/Include/Drivers/PL354Smc.h
new file mode 100644
index 0000000000..0da47f9982
--- /dev/null
+++ b/ArmPkg/Include/Drivers/PL354Smc.h
@@ -0,0 +1,57 @@
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef PL354SMC_H_
+#define PL354SMC_H_
+
+#define PL354_SMC_DIRECT_CMD_OFFSET 0x10
+#define PL354_SMC_SET_CYCLES_OFFSET 0x14
+#define PL354_SMC_SET_OPMODE_OFFSET 0x18
+
+#define PL354_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
+#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
+#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip) (((interf) << 25) | ((chip) << 23))
+
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
+#define PL354_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
+#define PL354_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
+#define PL354_SMC_SET_OPMODE_SET_BAA (1 << 10)
+#define PL354_SMC_SET_OPMODE_SET_ADV (1 << 11)
+#define PL354_SMC_SET_OPMODE_SET_BLS (1 << 12)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
+
+
+#endif
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
index fe63904d62..2987cbee53 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
@@ -1,36 +1,32 @@
-#------------------------------------------------------------------------------
-#
-# ARM VE Entry point. Reset vector in FV header will brach to
-# _ModuleEntryPoint.
-#
-# We use crazy macros, like LoadConstantToReg, since Xcode assembler
-# does not support = assembly syntax for ldr.
-#
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
+//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Drivers/PL354Smc.h>
#include <AutoGen.h>
-#Start of Code section
.text
.align 3
GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)
GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
-.extern ASM_PFX(InitializeSMC)
+.extern ASM_PFX(SMCInitializeNOR)
+.extern ASM_PFX(SMCInitializeSRAM)
+.extern ASM_PFX(SMCInitializePeripherals)
+.extern ASM_PFX(SMCInitializeVRAM)
/**
Called at the early stage of the Boot phase to know if the memory has already been initialized
@@ -65,10 +61,32 @@ ASM_PFX(ArmPlatformIsMemoryInitialized):
**/
ASM_PFX(ArmPlatformInitializeBootMemory):
mov r5, lr
+
+ //
// Initialize PL354 SMC
+ //
LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
+
+ // NOR Flash 0
+ LoadConstantToReg (PL354_SMC_DIRECT_CMD_ADDR_CS(0,0), r2)
+ blx ASM_PFX(SMCInitializeNOR)
+
+ // NOR Flash 1
+ LoadConstantToReg (PL354_SMC_DIRECT_CMD_ADDR_CS(1,0), r2)
+ blx ASM_PFX(SMCInitializeNOR)
+
+ // Setup SRAM
+ blx ASM_PFX(SMCInitializeSRAM)
+
+ // Memory Mapped Peripherals
+ blx ASM_PFX(SMCInitializePeripherals)
+
+ // Initialize VRAM
+ //TODO: Check if we really must inititialize Video SRAM in UEFI. Does Linux can do it ? Does the Video driver can do it ?
+ // It will be faster (only initialize if required) and easier (remove assembly code because of a stack available) to move this initialization.
LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
- blx ASM_PFX(InitializeSMC)
+ blx ASM_PFX(SMCInitializeVRAM)
+
bx r5
.end
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
index 7d59f5017d..3b353558e6 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
@@ -15,13 +15,17 @@
#include <Base.h>
#include <Library/PcdLib.h>
#include <ArmPlatform.h>
+#include <Drivers/PL354Smc.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
EXPORT ArmPlatformIsMemoryInitialized
EXPORT ArmPlatformInitializeBootMemory
- IMPORT InitializeSMC
+ IMPORT SMCInitializeNOR
+ IMPORT SMCInitializeSRAM
+ IMPORT SMCInitializePeripherals
+ IMPORT SMCInitializeVRAM
PRESERVE8
AREA CTA9x4Helper, CODE, READONLY
@@ -59,10 +63,32 @@ ArmPlatformIsMemoryInitialized
**/
ArmPlatformInitializeBootMemory
mov r5, lr
+
+ //
// Initialize PL354 SMC
+ //
LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
+
+ // NOR Flash 0
+ mov r2, PL354_SMC_DIRECT_CMD_ADDR_CS(0,0)
+ blx SMCInitializeNOR
+
+ // NOR Flash 1
+ mov r2, PL354_SMC_DIRECT_CMD_ADDR_CS(1,0)
+ blx SMCInitializeNOR
+
+ // Setup SRAM
+ blx SMCInitializeSRAM
+
+ // Memory Mapped Peripherals
+ blx SMCInitializePeripherals
+
+ // Initialize VRAM
+ //TODO: Check if we really must inititialize Video SRAM in UEFI. Does Linux can do it ? Does the Video driver can do it ?
+ // It will be faster (only initialize if required) and easier (remove assembly code because of a stack available) to move this initialization.
LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
- blx InitializeSMC
+ blx SMCInitializeVRAM
+
bx r5
-
+
END
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-02 22:24:57 +0000